2 * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
4 * All Alchemy development boards (except, of course, the weird PB1000)
5 * have a few registers in a CPLD with standardised layout; they mostly
6 * only differ in base address.
7 * All registers are 16bits wide with 32bit spacing.
10 #include <linux/interrupt.h>
11 #include <linux/module.h>
12 #include <linux/spinlock.h>
13 #include <asm/addrspace.h>
15 #include <asm/mach-db1x00/bcsr.h>
17 static struct bcsr_reg {
20 } bcsr_regs[BCSR_CNT];
22 static void __iomem *bcsr_virt; /* KSEG1 addr of BCSR base */
23 static int bcsr_csc_base; /* linux-irq of first cascaded irq */
25 void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys)
29 bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys));
30 bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys));
32 bcsr_virt = (void __iomem *)bcsr1_phys;
34 for (i = 0; i < BCSR_CNT; i++) {
35 if (i >= BCSR_HEXLEDS)
36 bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys +
37 (0x04 * (i - BCSR_HEXLEDS));
39 bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys +
42 spin_lock_init(&bcsr_regs[i].lock);
46 unsigned short bcsr_read(enum bcsr_id reg)
51 spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
52 r = __raw_readw(bcsr_regs[reg].raddr);
53 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
56 EXPORT_SYMBOL_GPL(bcsr_read);
58 void bcsr_write(enum bcsr_id reg, unsigned short val)
62 spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
63 __raw_writew(val, bcsr_regs[reg].raddr);
65 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
67 EXPORT_SYMBOL_GPL(bcsr_write);
69 void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set)
74 spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
75 r = __raw_readw(bcsr_regs[reg].raddr);
78 __raw_writew(r, bcsr_regs[reg].raddr);
80 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
82 EXPORT_SYMBOL_GPL(bcsr_mod);
85 * DB1200/PB1200 CPLD IRQ muxer
87 static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
89 unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
91 for ( ; bisr; bisr &= bisr - 1)
92 generic_handle_irq(bcsr_csc_base + __ffs(bisr));
95 /* NOTE: both the enable and mask bits must be cleared, otherwise the
96 * CPLD generates tons of spurious interrupts (at least on my DB1200).
99 static void bcsr_irq_mask(unsigned int irq_nr)
101 unsigned short v = 1 << (irq_nr - bcsr_csc_base);
102 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
103 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
107 static void bcsr_irq_maskack(unsigned int irq_nr)
109 unsigned short v = 1 << (irq_nr - bcsr_csc_base);
110 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
111 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
112 __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */
116 static void bcsr_irq_unmask(unsigned int irq_nr)
118 unsigned short v = 1 << (irq_nr - bcsr_csc_base);
119 __raw_writew(v, bcsr_virt + BCSR_REG_INTSET);
120 __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
124 static struct irq_chip bcsr_irq_type = {
126 .mask = bcsr_irq_mask,
127 .mask_ack = bcsr_irq_maskack,
128 .unmask = bcsr_irq_unmask,
131 void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
135 /* mask & disable & ack all */
136 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTCLR);
137 __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR);
138 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT);
141 bcsr_csc_base = csc_start;
143 for (irq = csc_start; irq <= csc_end; irq++)
144 set_irq_chip_and_handler_name(irq, &bcsr_irq_type,
145 handle_level_irq, "level");
147 set_irq_chained_handler(hook_irq, bcsr_csc_handler);