1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
8 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
9 select ARCH_HAS_FORTIFY_SOURCE
11 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
12 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
13 select ARCH_HAS_STRNCPY_FROM_USER
14 select ARCH_HAS_STRNLEN_USER
15 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
16 select ARCH_HAS_UBSAN_SANITIZE_ALL
17 select ARCH_HAS_GCOV_PROFILE_ALL
18 select ARCH_KEEP_MEMBLOCK
19 select ARCH_SUPPORTS_UPROBES
20 select ARCH_USE_BUILTIN_BSWAP
21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
22 select ARCH_USE_MEMTEST
23 select ARCH_USE_QUEUED_RWLOCKS
24 select ARCH_USE_QUEUED_SPINLOCKS
25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
27 select ARCH_WANT_IPC_PARSE_VERSION
28 select ARCH_WANT_LD_ORPHAN_WARN
29 select BUILDTIME_TABLE_SORT
30 select CLONE_BACKWARDS
31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
32 select CPU_PM if CPU_IDLE
33 select GENERIC_ATOMIC64 if !64BIT
34 select GENERIC_CMOS_UPDATE
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_GETTIMEOFDAY
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_ISA_DMA if EISA
41 select GENERIC_LIB_ASHLDI3
42 select GENERIC_LIB_ASHRDI3
43 select GENERIC_LIB_CMPDI2
44 select GENERIC_LIB_LSHRDI3
45 select GENERIC_LIB_UCMPDI2
46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
47 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_TIME_VSYSCALL
49 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
50 select HAVE_ARCH_COMPILER_H
51 select HAVE_ARCH_JUMP_LABEL
52 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
53 select HAVE_ARCH_MMAP_RND_BITS if MMU
54 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
55 select HAVE_ARCH_SECCOMP_FILTER
56 select HAVE_ARCH_TRACEHOOK
57 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
58 select HAVE_ASM_MODVERSIONS
59 select HAVE_CONTEXT_TRACKING_USER
61 select HAVE_C_RECORDMCOUNT
62 select HAVE_DEBUG_KMEMLEAK
63 select HAVE_DEBUG_STACKOVERFLOW
64 select HAVE_DMA_CONTIGUOUS
65 select HAVE_DYNAMIC_FTRACE
66 select HAVE_EBPF_JIT if !CPU_MICROMIPS
67 select HAVE_EXIT_THREAD
69 select HAVE_FTRACE_MCOUNT_RECORD
70 select HAVE_FUNCTION_GRAPH_TRACER
71 select HAVE_FUNCTION_TRACER
72 select HAVE_GCC_PLUGINS
73 select HAVE_GENERIC_VDSO
74 select HAVE_IOREMAP_PROT
75 select HAVE_IRQ_EXIT_ON_IRQ_STACK
76 select HAVE_IRQ_TIME_ACCOUNTING
78 select HAVE_KRETPROBES
79 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
80 select HAVE_MOD_ARCH_SPECIFIC
82 select HAVE_PERF_EVENTS
84 select HAVE_PERF_USER_STACK_DUMP
85 select HAVE_REGS_AND_STACK_ACCESS_API
87 select HAVE_SPARSE_SYSCALL_NR
88 select HAVE_STACKPROTECTOR
89 select HAVE_SYSCALL_TRACEPOINTS
90 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
91 select IRQ_FORCED_THREADING
93 select MODULES_USE_ELF_REL if MODULES
94 select MODULES_USE_ELF_RELA if MODULES && 64BIT
95 select PERF_USE_VMALLOC
96 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
98 select SYSCTL_EXCEPTION_TRACE
99 select TRACE_IRQFLAGS_SUPPORT
100 select ARCH_HAS_ELFCORE_COMPAT
101 select HAVE_ARCH_KCSAN if 64BIT
103 config MIPS_FIXUP_BIGPHYS_ADDR
111 select SYS_SUPPORTS_32BIT_KERNEL
112 select SYS_SUPPORTS_LITTLE_ENDIAN
113 select SYS_SUPPORTS_ZBOOT
114 select DMA_NONCOHERENT
115 select ARCH_HAS_SYNC_DMA_FOR_CPU
120 select GENERIC_IRQ_CHIP
121 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
123 select CPU_SUPPORTS_CPUFREQ
124 select MIPS_EXTERNAL_TIMER
126 menu "Machine selection"
130 default MIPS_GENERIC_KERNEL
132 config MIPS_GENERIC_KERNEL
133 bool "Generic board-agnostic MIPS kernel"
134 select ARCH_HAS_SETUP_DMA_OPS
139 select CLKSRC_MIPS_GIC
141 select CPU_MIPSR2_IRQ_EI
142 select CPU_MIPSR2_IRQ_VI
144 select DMA_NONCOHERENT
147 select MIPS_AUTO_PFN_OFFSET
148 select MIPS_CPU_SCACHE
150 select MIPS_L1_CACHE_SHIFT_7
151 select NO_EXCEPT_FILL
152 select PCI_DRIVERS_GENERIC
155 select SYS_HAS_CPU_MIPS32_R1
156 select SYS_HAS_CPU_MIPS32_R2
157 select SYS_HAS_CPU_MIPS32_R6
158 select SYS_HAS_CPU_MIPS64_R1
159 select SYS_HAS_CPU_MIPS64_R2
160 select SYS_HAS_CPU_MIPS64_R6
161 select SYS_SUPPORTS_32BIT_KERNEL
162 select SYS_SUPPORTS_64BIT_KERNEL
163 select SYS_SUPPORTS_BIG_ENDIAN
164 select SYS_SUPPORTS_HIGHMEM
165 select SYS_SUPPORTS_LITTLE_ENDIAN
166 select SYS_SUPPORTS_MICROMIPS
167 select SYS_SUPPORTS_MIPS16
168 select SYS_SUPPORTS_MIPS_CPS
169 select SYS_SUPPORTS_MULTITHREADING
170 select SYS_SUPPORTS_RELOCATABLE
171 select SYS_SUPPORTS_SMARTMIPS
172 select SYS_SUPPORTS_ZBOOT
174 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
175 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
176 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
177 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
178 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
179 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
182 Select this to build a kernel which aims to support multiple boards,
183 generally using a flattened device tree passed from the bootloader
184 using the boot protocol defined in the UHI (Unified Hosting
185 Interface) specification.
188 bool "Alchemy processor based machines"
189 select PHYS_ADDR_T_64BIT
193 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
194 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
195 select SYS_HAS_CPU_MIPS32_R1
196 select SYS_SUPPORTS_32BIT_KERNEL
197 select SYS_SUPPORTS_APM_EMULATION
199 select SYS_SUPPORTS_ZBOOT
203 bool "Texas Instruments AR7"
206 select DMA_NONCOHERENT
210 select NO_EXCEPT_FILL
212 select SYS_HAS_CPU_MIPS32_R1
213 select SYS_HAS_EARLY_PRINTK
214 select SYS_SUPPORTS_32BIT_KERNEL
215 select SYS_SUPPORTS_LITTLE_ENDIAN
216 select SYS_SUPPORTS_MIPS16
217 select SYS_SUPPORTS_ZBOOT_UART16550
221 Support for the Texas Instruments AR7 System-on-a-Chip
222 family: TNETD7100, 7200 and 7300.
225 bool "Atheros AR231x/AR531x SoC support"
228 select DMA_NONCOHERENT
231 select SYS_HAS_CPU_MIPS32_R1
232 select SYS_SUPPORTS_BIG_ENDIAN
233 select SYS_SUPPORTS_32BIT_KERNEL
234 select SYS_HAS_EARLY_PRINTK
236 Support for Atheros AR231x and Atheros AR531x based boards
239 bool "Atheros AR71XX/AR724X/AR913X based boards"
240 select ARCH_HAS_RESET_CONTROLLER
244 select DMA_NONCOHERENT
249 select SYS_HAS_CPU_MIPS32_R2
250 select SYS_HAS_EARLY_PRINTK
251 select SYS_SUPPORTS_32BIT_KERNEL
252 select SYS_SUPPORTS_BIG_ENDIAN
253 select SYS_SUPPORTS_MIPS16
254 select SYS_SUPPORTS_ZBOOT_UART_PROM
256 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
258 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
261 bool "Broadcom Generic BMIPS kernel"
262 select ARCH_HAS_RESET_CONTROLLER
263 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
265 select NO_EXCEPT_FILL
271 select BCM6345_L1_IRQ
272 select BCM7038_L1_IRQ
273 select BCM7120_L2_IRQ
274 select BRCMSTB_L2_IRQ
276 select DMA_NONCOHERENT
277 select SYS_SUPPORTS_32BIT_KERNEL
278 select SYS_SUPPORTS_LITTLE_ENDIAN
279 select SYS_SUPPORTS_BIG_ENDIAN
280 select SYS_SUPPORTS_HIGHMEM
281 select SYS_HAS_CPU_BMIPS32_3300
282 select SYS_HAS_CPU_BMIPS4350
283 select SYS_HAS_CPU_BMIPS4380
284 select SYS_HAS_CPU_BMIPS5000
286 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
287 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
288 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
289 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
290 select HARDIRQS_SW_RESEND
292 select PCI_DRIVERS_GENERIC
295 Build a generic DT-based kernel image that boots on select
296 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
297 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
298 must be set appropriately for your board.
301 bool "Broadcom BCM47XX based boards"
305 select DMA_NONCOHERENT
308 select SYS_HAS_CPU_MIPS32_R1
309 select NO_EXCEPT_FILL
310 select SYS_SUPPORTS_32BIT_KERNEL
311 select SYS_SUPPORTS_LITTLE_ENDIAN
312 select SYS_SUPPORTS_MIPS16
313 select SYS_SUPPORTS_ZBOOT
314 select SYS_HAS_EARLY_PRINTK
315 select USE_GENERIC_EARLY_PRINTK_8250
317 select LEDS_GPIO_REGISTER
320 select BCM47XX_SSB if !BCM47XX_BCMA
322 Support for BCM47XX based boards
325 bool "Broadcom BCM63XX based boards"
330 select DMA_NONCOHERENT
332 select SYS_SUPPORTS_32BIT_KERNEL
333 select SYS_SUPPORTS_BIG_ENDIAN
334 select SYS_HAS_EARLY_PRINTK
335 select SYS_HAS_CPU_BMIPS32_3300
336 select SYS_HAS_CPU_BMIPS4350
337 select SYS_HAS_CPU_BMIPS4380
340 select MIPS_L1_CACHE_SHIFT_4
341 select HAVE_LEGACY_CLK
343 Support for BCM63XX based boards
350 select DMA_NONCOHERENT
356 select PCI_GT64XXX_PCI0
357 select SYS_HAS_CPU_NEVADA
358 select SYS_HAS_EARLY_PRINTK
359 select SYS_SUPPORTS_32BIT_KERNEL
360 select SYS_SUPPORTS_64BIT_KERNEL
361 select SYS_SUPPORTS_LITTLE_ENDIAN
362 select USE_GENERIC_EARLY_PRINTK_8250
364 config MACH_DECSTATION
368 select CEVT_R4K if CPU_R4X00
370 select CSRC_R4K if CPU_R4X00
371 select CPU_DADDI_WORKAROUNDS if 64BIT
372 select CPU_R4000_WORKAROUNDS if 64BIT
373 select CPU_R4400_WORKAROUNDS if 64BIT
374 select DMA_NONCOHERENT
377 select SYS_HAS_CPU_R3000
378 select SYS_HAS_CPU_R4X00
379 select SYS_SUPPORTS_32BIT_KERNEL
380 select SYS_SUPPORTS_64BIT_KERNEL
381 select SYS_SUPPORTS_LITTLE_ENDIAN
382 select SYS_SUPPORTS_128HZ
383 select SYS_SUPPORTS_256HZ
384 select SYS_SUPPORTS_1024HZ
385 select MIPS_L1_CACHE_SHIFT_4
387 This enables support for DEC's MIPS based workstations. For details
388 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
389 DECstation porting pages on <http://decstation.unix-ag.org/>.
391 If you have one of the following DECstation Models you definitely
392 want to choose R4xx0 for the CPU Type:
399 otherwise choose R3000.
402 bool "Jazz family of machines"
405 select ARCH_MIGHT_HAVE_PC_PARPORT
406 select ARCH_MIGHT_HAVE_PC_SERIO
410 select ARCH_MAY_HAVE_PC_FDC
413 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
414 select GENERIC_ISA_DMA
415 select HAVE_PCSPKR_PLATFORM
420 select SYS_HAS_CPU_R4X00
421 select SYS_SUPPORTS_32BIT_KERNEL
422 select SYS_SUPPORTS_64BIT_KERNEL
423 select SYS_SUPPORTS_100HZ
424 select SYS_SUPPORTS_LITTLE_ENDIAN
426 This a family of machines based on the MIPS R4030 chipset which was
427 used by several vendors to build RISC/os and Windows NT workstations.
428 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
429 Olivetti M700-10 workstations.
431 config MACH_INGENIC_SOC
432 bool "Ingenic SoC based machines"
435 select SYS_SUPPORTS_ZBOOT_UART16550
436 select CPU_SUPPORTS_CPUFREQ
437 select MIPS_EXTERNAL_TIMER
440 bool "Lantiq based platforms"
441 select DMA_NONCOHERENT
445 select NO_EXCEPT_FILL
446 select SYS_HAS_CPU_MIPS32_R1
447 select SYS_HAS_CPU_MIPS32_R2
448 select SYS_SUPPORTS_BIG_ENDIAN
449 select SYS_SUPPORTS_32BIT_KERNEL
450 select SYS_SUPPORTS_MIPS16
451 select SYS_SUPPORTS_MULTITHREADING
452 select SYS_SUPPORTS_VPE_LOADER
453 select SYS_HAS_EARLY_PRINTK
457 select HAVE_LEGACY_CLK
460 select PINCTRL_LANTIQ
461 select ARCH_HAS_RESET_CONTROLLER
462 select RESET_CONTROLLER
464 config MACH_LOONGSON32
465 bool "Loongson 32-bit family of machines"
466 select SYS_SUPPORTS_ZBOOT
468 This enables support for the Loongson-1 family of machines.
470 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
471 the Institute of Computing Technology (ICT), Chinese Academy of
474 config MACH_LOONGSON2EF
475 bool "Loongson-2E/F family of machines"
476 select SYS_SUPPORTS_ZBOOT
478 This enables the support of early Loongson-2E/F family of machines.
480 config MACH_LOONGSON64
481 bool "Loongson 64-bit family of machines"
482 select ARCH_SPARSEMEM_ENABLE
483 select ARCH_MIGHT_HAVE_PC_PARPORT
484 select ARCH_MIGHT_HAVE_PC_SERIO
485 select GENERIC_ISA_DMA_SUPPORT_BROKEN
495 select NO_EXCEPT_FILL
496 select NR_CPUS_DEFAULT_64
497 select USE_GENERIC_EARLY_PRINTK_8250
498 select PCI_DRIVERS_GENERIC
499 select SYS_HAS_CPU_LOONGSON64
500 select SYS_HAS_EARLY_PRINTK
501 select SYS_SUPPORTS_SMP
502 select SYS_SUPPORTS_HOTPLUG_CPU
503 select SYS_SUPPORTS_NUMA
504 select SYS_SUPPORTS_64BIT_KERNEL
505 select SYS_SUPPORTS_HIGHMEM
506 select SYS_SUPPORTS_LITTLE_ENDIAN
507 select SYS_SUPPORTS_ZBOOT
508 select SYS_SUPPORTS_RELOCATABLE
513 select PCI_HOST_GENERIC
514 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
516 This enables the support of Loongson-2/3 family of machines.
518 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
519 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
520 and Loongson-2F which will be removed), developed by the Institute
521 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
524 bool "MIPS Malta board"
525 select ARCH_MAY_HAVE_PC_FDC
526 select ARCH_MIGHT_HAVE_PC_PARPORT
527 select ARCH_MIGHT_HAVE_PC_SERIO
532 select CLKSRC_MIPS_GIC
535 select DMA_NONCOHERENT
536 select GENERIC_ISA_DMA
537 select HAVE_PCSPKR_PLATFORM
543 select MIPS_CPU_SCACHE
545 select MIPS_L1_CACHE_SHIFT_6
547 select PCI_GT64XXX_PCI0
550 select SYS_HAS_CPU_MIPS32_R1
551 select SYS_HAS_CPU_MIPS32_R2
552 select SYS_HAS_CPU_MIPS32_R3_5
553 select SYS_HAS_CPU_MIPS32_R5
554 select SYS_HAS_CPU_MIPS32_R6
555 select SYS_HAS_CPU_MIPS64_R1
556 select SYS_HAS_CPU_MIPS64_R2
557 select SYS_HAS_CPU_MIPS64_R6
558 select SYS_HAS_CPU_NEVADA
559 select SYS_HAS_CPU_RM7000
560 select SYS_SUPPORTS_32BIT_KERNEL
561 select SYS_SUPPORTS_64BIT_KERNEL
562 select SYS_SUPPORTS_BIG_ENDIAN
563 select SYS_SUPPORTS_HIGHMEM
564 select SYS_SUPPORTS_LITTLE_ENDIAN
565 select SYS_SUPPORTS_MICROMIPS
566 select SYS_SUPPORTS_MIPS16
567 select SYS_SUPPORTS_MIPS_CMP
568 select SYS_SUPPORTS_MIPS_CPS
569 select SYS_SUPPORTS_MULTITHREADING
570 select SYS_SUPPORTS_RELOCATABLE
571 select SYS_SUPPORTS_SMARTMIPS
572 select SYS_SUPPORTS_VPE_LOADER
573 select SYS_SUPPORTS_ZBOOT
575 select WAR_ICACHE_REFILLS
576 select ZONE_DMA32 if 64BIT
578 This enables support for the MIPS Technologies Malta evaluation
582 bool "Microchip PIC32 Family"
584 This enables support for the Microchip PIC32 family of platforms.
586 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
589 config MACH_NINTENDO64
590 bool "Nintendo 64 console"
593 select SYS_HAS_CPU_R4300
594 select SYS_SUPPORTS_BIG_ENDIAN
595 select SYS_SUPPORTS_ZBOOT
596 select SYS_SUPPORTS_32BIT_KERNEL
597 select SYS_SUPPORTS_64BIT_KERNEL
598 select DMA_NONCOHERENT
602 bool "Ralink based machines"
607 select DMA_NONCOHERENT
610 select SYS_HAS_CPU_MIPS32_R2
611 select SYS_SUPPORTS_32BIT_KERNEL
612 select SYS_SUPPORTS_LITTLE_ENDIAN
613 select SYS_SUPPORTS_MIPS16
614 select SYS_SUPPORTS_ZBOOT
615 select SYS_HAS_EARLY_PRINTK
616 select ARCH_HAS_RESET_CONTROLLER
617 select RESET_CONTROLLER
619 config MACH_REALTEK_RTL
620 bool "Realtek RTL838x/RTL839x based machines"
622 select DMA_NONCOHERENT
626 select SYS_HAS_CPU_MIPS32_R1
627 select SYS_HAS_CPU_MIPS32_R2
628 select SYS_SUPPORTS_BIG_ENDIAN
629 select SYS_SUPPORTS_32BIT_KERNEL
630 select SYS_SUPPORTS_MIPS16
631 select SYS_SUPPORTS_MULTITHREADING
632 select SYS_SUPPORTS_VPE_LOADER
638 bool "SGI IP22 (Indy/Indigo2)"
643 select ARCH_MIGHT_HAVE_PC_SERIO
647 select DEFAULT_SGI_PARTITION
648 select DMA_NONCOHERENT
652 select IP22_CPU_SCACHE
654 select GENERIC_ISA_DMA_SUPPORT_BROKEN
656 select SGI_HAS_INDYDOG
662 select SYS_HAS_CPU_R4X00
663 select SYS_HAS_CPU_R5000
664 select SYS_HAS_EARLY_PRINTK
665 select SYS_SUPPORTS_32BIT_KERNEL
666 select SYS_SUPPORTS_64BIT_KERNEL
667 select SYS_SUPPORTS_BIG_ENDIAN
668 select WAR_R4600_V1_INDEX_ICACHEOP
669 select WAR_R4600_V1_HIT_CACHEOP
670 select WAR_R4600_V2_HIT_CACHEOP
671 select MIPS_L1_CACHE_SHIFT_7
673 This are the SGI Indy, Challenge S and Indigo2, as well as certain
674 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
675 that runs on these, say Y here.
678 bool "SGI IP27 (Origin200/2000)"
679 select ARCH_HAS_PHYS_TO_DMA
680 select ARCH_SPARSEMEM_ENABLE
683 select ARC_CMDLINE_ONLY
685 select DEFAULT_SGI_PARTITION
687 select SYS_HAS_EARLY_PRINTK
690 select IRQ_DOMAIN_HIERARCHY
691 select NR_CPUS_DEFAULT_64
692 select PCI_DRIVERS_GENERIC
693 select PCI_XTALK_BRIDGE
694 select SYS_HAS_CPU_R10000
695 select SYS_SUPPORTS_64BIT_KERNEL
696 select SYS_SUPPORTS_BIG_ENDIAN
697 select SYS_SUPPORTS_NUMA
698 select SYS_SUPPORTS_SMP
699 select WAR_R10000_LLSC
700 select MIPS_L1_CACHE_SHIFT_7
702 select HAVE_ARCH_NODEDATA_EXTENSION
704 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
705 workstations. To compile a Linux kernel that runs on these, say Y
709 bool "SGI IP28 (Indigo2 R10k)"
714 select ARCH_MIGHT_HAVE_PC_SERIO
718 select DEFAULT_SGI_PARTITION
719 select DMA_NONCOHERENT
720 select GENERIC_ISA_DMA_SUPPORT_BROKEN
726 select SGI_HAS_INDYDOG
732 select SYS_HAS_CPU_R10000
733 select SYS_HAS_EARLY_PRINTK
734 select SYS_SUPPORTS_64BIT_KERNEL
735 select SYS_SUPPORTS_BIG_ENDIAN
736 select WAR_R10000_LLSC
737 select MIPS_L1_CACHE_SHIFT_7
739 This is the SGI Indigo2 with R10000 processor. To compile a Linux
740 kernel that runs on these, say Y here.
743 bool "SGI IP30 (Octane/Octane2)"
744 select ARCH_HAS_PHYS_TO_DMA
751 select SYNC_R4K if SMP
755 select IRQ_DOMAIN_HIERARCHY
756 select PCI_DRIVERS_GENERIC
757 select PCI_XTALK_BRIDGE
758 select SYS_HAS_EARLY_PRINTK
759 select SYS_HAS_CPU_R10000
760 select SYS_SUPPORTS_64BIT_KERNEL
761 select SYS_SUPPORTS_BIG_ENDIAN
762 select SYS_SUPPORTS_SMP
763 select WAR_R10000_LLSC
764 select MIPS_L1_CACHE_SHIFT_7
767 These are the SGI Octane and Octane2 graphics workstations. To
768 compile a Linux kernel that runs on these, say Y here.
774 select ARCH_HAS_PHYS_TO_DMA
780 select DMA_NONCOHERENT
783 select R5000_CPU_SCACHE
784 select RM7000_CPU_SCACHE
785 select SYS_HAS_CPU_R5000
786 select SYS_HAS_CPU_R10000 if BROKEN
787 select SYS_HAS_CPU_RM7000
788 select SYS_HAS_CPU_NEVADA
789 select SYS_SUPPORTS_64BIT_KERNEL
790 select SYS_SUPPORTS_BIG_ENDIAN
791 select WAR_ICACHE_REFILLS
793 If you want this kernel to run on SGI O2 workstation, say Y here.
796 bool "Sibyte BCM91120C-CRhine"
798 select SIBYTE_BCM1120
800 select SYS_HAS_CPU_SB1
801 select SYS_SUPPORTS_BIG_ENDIAN
802 select SYS_SUPPORTS_LITTLE_ENDIAN
805 bool "Sibyte BCM91120x-Carmel"
807 select SIBYTE_BCM1120
809 select SYS_HAS_CPU_SB1
810 select SYS_SUPPORTS_BIG_ENDIAN
811 select SYS_SUPPORTS_LITTLE_ENDIAN
814 bool "Sibyte BCM91125C-CRhone"
816 select SIBYTE_BCM1125
818 select SYS_HAS_CPU_SB1
819 select SYS_SUPPORTS_BIG_ENDIAN
820 select SYS_SUPPORTS_HIGHMEM
821 select SYS_SUPPORTS_LITTLE_ENDIAN
824 bool "Sibyte BCM91125E-Rhone"
826 select SIBYTE_BCM1125H
828 select SYS_HAS_CPU_SB1
829 select SYS_SUPPORTS_BIG_ENDIAN
830 select SYS_SUPPORTS_LITTLE_ENDIAN
833 bool "Sibyte BCM91250A-SWARM"
835 select HAVE_PATA_PLATFORM
838 select SYS_HAS_CPU_SB1
839 select SYS_SUPPORTS_BIG_ENDIAN
840 select SYS_SUPPORTS_HIGHMEM
841 select SYS_SUPPORTS_LITTLE_ENDIAN
842 select ZONE_DMA32 if 64BIT
843 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
845 config SIBYTE_LITTLESUR
846 bool "Sibyte BCM91250C2-LittleSur"
848 select HAVE_PATA_PLATFORM
851 select SYS_HAS_CPU_SB1
852 select SYS_SUPPORTS_BIG_ENDIAN
853 select SYS_SUPPORTS_HIGHMEM
854 select SYS_SUPPORTS_LITTLE_ENDIAN
855 select ZONE_DMA32 if 64BIT
857 config SIBYTE_SENTOSA
858 bool "Sibyte BCM91250E-Sentosa"
862 select SYS_HAS_CPU_SB1
863 select SYS_SUPPORTS_BIG_ENDIAN
864 select SYS_SUPPORTS_LITTLE_ENDIAN
865 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
868 bool "Sibyte BCM91480B-BigSur"
870 select NR_CPUS_DEFAULT_4
871 select SIBYTE_BCM1x80
873 select SYS_HAS_CPU_SB1
874 select SYS_SUPPORTS_BIG_ENDIAN
875 select SYS_SUPPORTS_HIGHMEM
876 select SYS_SUPPORTS_LITTLE_ENDIAN
877 select ZONE_DMA32 if 64BIT
878 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
881 bool "SNI RM200/300/400"
884 select FW_ARC if CPU_LITTLE_ENDIAN
885 select FW_ARC32 if CPU_LITTLE_ENDIAN
886 select FW_SNIPROM if CPU_BIG_ENDIAN
887 select ARCH_MAY_HAVE_PC_FDC
888 select ARCH_MIGHT_HAVE_PC_PARPORT
889 select ARCH_MIGHT_HAVE_PC_SERIO
893 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
894 select DMA_NONCOHERENT
895 select GENERIC_ISA_DMA
897 select HAVE_PCSPKR_PLATFORM
903 select MIPS_L1_CACHE_SHIFT_6
904 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
905 select SYS_HAS_CPU_R4X00
906 select SYS_HAS_CPU_R5000
907 select SYS_HAS_CPU_R10000
908 select R5000_CPU_SCACHE
909 select SYS_HAS_EARLY_PRINTK
910 select SYS_SUPPORTS_32BIT_KERNEL
911 select SYS_SUPPORTS_64BIT_KERNEL
912 select SYS_SUPPORTS_BIG_ENDIAN
913 select SYS_SUPPORTS_HIGHMEM
914 select SYS_SUPPORTS_LITTLE_ENDIAN
915 select WAR_R4600_V2_HIT_CACHEOP
917 The SNI RM200/300/400 are MIPS-based machines manufactured by
918 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
919 Technology and now in turn merged with Fujitsu. Say Y here to
920 support this machine type.
923 bool "Toshiba TX49 series based machines"
924 select WAR_TX49XX_ICACHE_INDEX_INV
926 config MIKROTIK_RB532
927 bool "Mikrotik RB532 boards"
930 select DMA_NONCOHERENT
933 select SYS_HAS_CPU_MIPS32_R1
934 select SYS_SUPPORTS_32BIT_KERNEL
935 select SYS_SUPPORTS_LITTLE_ENDIAN
939 select MIPS_L1_CACHE_SHIFT_4
941 Support the Mikrotik(tm) RouterBoard 532 series,
942 based on the IDT RC32434 SoC.
944 config CAVIUM_OCTEON_SOC
945 bool "Cavium Networks Octeon SoC based boards"
947 select ARCH_HAS_PHYS_TO_DMA
949 select PHYS_ADDR_T_64BIT
950 select SYS_SUPPORTS_64BIT_KERNEL
951 select SYS_SUPPORTS_BIG_ENDIAN
953 select EDAC_ATOMIC_SCRUB
954 select SYS_SUPPORTS_LITTLE_ENDIAN
955 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
956 select SYS_HAS_EARLY_PRINTK
957 select SYS_HAS_CPU_CAVIUM_OCTEON
959 select HAVE_PLAT_DELAY
960 select HAVE_PLAT_FW_INIT_CMDLINE
961 select HAVE_PLAT_MEMCPY
965 select ARCH_SPARSEMEM_ENABLE
966 select SYS_SUPPORTS_SMP
967 select NR_CPUS_DEFAULT_64
968 select MIPS_NR_CPU_NR_MAP_1024
971 select MTD_COMPLEX_MAPPINGS
973 select SYS_SUPPORTS_RELOCATABLE
975 This option supports all of the Octeon reference boards from Cavium
976 Networks. It builds a kernel that dynamically determines the Octeon
977 CPU type and supports all known board reference implementations.
978 Some of the supported boards are:
985 Say Y here for most Octeon reference boards.
989 source "arch/mips/alchemy/Kconfig"
990 source "arch/mips/ath25/Kconfig"
991 source "arch/mips/ath79/Kconfig"
992 source "arch/mips/bcm47xx/Kconfig"
993 source "arch/mips/bcm63xx/Kconfig"
994 source "arch/mips/bmips/Kconfig"
995 source "arch/mips/generic/Kconfig"
996 source "arch/mips/ingenic/Kconfig"
997 source "arch/mips/jazz/Kconfig"
998 source "arch/mips/lantiq/Kconfig"
999 source "arch/mips/pic32/Kconfig"
1000 source "arch/mips/ralink/Kconfig"
1001 source "arch/mips/sgi-ip27/Kconfig"
1002 source "arch/mips/sibyte/Kconfig"
1003 source "arch/mips/txx9/Kconfig"
1004 source "arch/mips/cavium-octeon/Kconfig"
1005 source "arch/mips/loongson2ef/Kconfig"
1006 source "arch/mips/loongson32/Kconfig"
1007 source "arch/mips/loongson64/Kconfig"
1011 config GENERIC_HWEIGHT
1015 config GENERIC_CALIBRATE_DELAY
1019 config SCHED_OMIT_FRAME_POINTER
1024 # Select some configuration options automatically based on user selections.
1029 config ARCH_MAY_HAVE_PC_FDC
1060 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
1066 config MIPS_CLOCK_VSYSCALL
1067 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
1076 config ARCH_SUPPORTS_UPROBES
1079 config DMA_NONCOHERENT
1082 # MIPS allows mixing "slightly different" Cacheability and Coherency
1083 # Attribute bits. It is believed that the uncached access through
1084 # KSEG1 and the implementation specific "uncached accelerated" used
1085 # by pgprot_writcombine can be mixed, and the latter sometimes provides
1086 # significant advantages.
1088 select ARCH_HAS_DMA_WRITE_COMBINE
1089 select ARCH_HAS_DMA_PREP_COHERENT
1090 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
1091 select ARCH_HAS_DMA_SET_UNCACHED
1092 select DMA_NONCOHERENT_MMAP
1093 select NEED_DMA_MAP_STATE
1095 config SYS_HAS_EARLY_PRINTK
1098 config SYS_SUPPORTS_HOTPLUG_CPU
1101 config MIPS_BONITO64
1110 config NO_IOPORT_MAP
1114 def_bool CPU_NO_LOAD_STORE_LR
1116 config GENERIC_ISA_DMA
1118 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
1121 config GENERIC_ISA_DMA_SUPPORT_BROKEN
1123 select GENERIC_ISA_DMA
1125 config HAVE_PLAT_DELAY
1128 config HAVE_PLAT_FW_INIT_CMDLINE
1131 config HAVE_PLAT_MEMCPY
1137 config SYS_SUPPORTS_RELOCATABLE
1140 Selected if the platform supports relocating the kernel.
1141 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
1142 to allow access to command line and entropy sources.
1145 # Endianness selection. Sufficiently obscure so many users don't know what to
1146 # answer,so we try hard to limit the available choices. Also the use of a
1147 # choice statement should be more obvious to the user.
1150 prompt "Endianness selection"
1152 Some MIPS machines can be configured for either little or big endian
1153 byte order. These modes require different kernels and a different
1154 Linux distribution. In general there is one preferred byteorder for a
1155 particular system but some systems are just as commonly used in the
1156 one or the other endianness.
1158 config CPU_BIG_ENDIAN
1160 depends on SYS_SUPPORTS_BIG_ENDIAN
1162 config CPU_LITTLE_ENDIAN
1163 bool "Little endian"
1164 depends on SYS_SUPPORTS_LITTLE_ENDIAN
1171 config SYS_SUPPORTS_APM_EMULATION
1174 config SYS_SUPPORTS_BIG_ENDIAN
1177 config SYS_SUPPORTS_LITTLE_ENDIAN
1180 config MIPS_HUGE_TLB_SUPPORT
1181 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
1195 config PCI_GT64XXX_PCI0
1198 config PCI_XTALK_BRIDGE
1201 config NO_EXCEPT_FILL
1207 config SWAP_IO_SPACE
1210 config SGI_HAS_INDYDOG
1222 config SGI_HAS_ZILOG
1225 config SGI_HAS_I8042
1228 config DEFAULT_SGI_PARTITION
1240 config MIPS_L1_CACHE_SHIFT_4
1243 config MIPS_L1_CACHE_SHIFT_5
1246 config MIPS_L1_CACHE_SHIFT_6
1249 config MIPS_L1_CACHE_SHIFT_7
1252 config MIPS_L1_CACHE_SHIFT
1254 default "7" if MIPS_L1_CACHE_SHIFT_7
1255 default "6" if MIPS_L1_CACHE_SHIFT_6
1256 default "5" if MIPS_L1_CACHE_SHIFT_5
1257 default "4" if MIPS_L1_CACHE_SHIFT_4
1260 config ARC_CMDLINE_ONLY
1264 bool "ARC console support"
1265 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
1279 menu "CPU selection"
1285 config CPU_LOONGSON64
1286 bool "Loongson 64-bit CPU"
1287 depends on SYS_HAS_CPU_LOONGSON64
1288 select ARCH_HAS_PHYS_TO_DMA
1290 select CPU_HAS_PREFETCH
1291 select CPU_SUPPORTS_64BIT_KERNEL
1292 select CPU_SUPPORTS_HIGHMEM
1293 select CPU_SUPPORTS_HUGEPAGES
1294 select CPU_SUPPORTS_MSA
1295 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
1296 select CPU_MIPSR2_IRQ_VI
1297 select WEAK_ORDERING
1298 select WEAK_REORDERING_BEYOND_LLSC
1299 select MIPS_ASID_BITS_VARIABLE
1300 select MIPS_PGD_C0_CONTEXT
1301 select MIPS_L1_CACHE_SHIFT_6
1302 select MIPS_FP_SUPPORT
1307 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1308 cores implements the MIPS64R2 instruction set with many extensions,
1309 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1310 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
1311 Loongson-2E/2F is not covered here and will be removed in future.
1313 config LOONGSON3_ENHANCEMENT
1314 bool "New Loongson-3 CPU Enhancements"
1316 depends on CPU_LOONGSON64
1318 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1319 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1320 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1321 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1322 Fast TLB refill support, etc.
1324 This option enable those enhancements which are not probed at run
1325 time. If you want a generic kernel to run on all Loongson 3 machines,
1326 please say 'N' here. If you want a high-performance kernel to run on
1327 new Loongson-3 machines only, please say 'Y' here.
1329 config CPU_LOONGSON3_WORKAROUNDS
1330 bool "Loongson-3 LLSC Workarounds"
1332 depends on CPU_LOONGSON64
1334 Loongson-3 processors have the llsc issues which require workarounds.
1335 Without workarounds the system may hang unexpectedly.
1337 Say Y, unless you know what you are doing.
1339 config CPU_LOONGSON3_CPUCFG_EMULATION
1340 bool "Emulate the CPUCFG instruction on older Loongson cores"
1342 depends on CPU_LOONGSON64
1344 Loongson-3A R4 and newer have the CPUCFG instruction available for
1345 userland to query CPU capabilities, much like CPUID on x86. This
1346 option provides emulation of the instruction on older Loongson
1347 cores, back to Loongson-3A1000.
1349 If unsure, please say Y.
1351 config CPU_LOONGSON2E
1353 depends on SYS_HAS_CPU_LOONGSON2E
1354 select CPU_LOONGSON2EF
1356 The Loongson 2E processor implements the MIPS III instruction set
1357 with many extensions.
1359 It has an internal FPGA northbridge, which is compatible to
1362 config CPU_LOONGSON2F
1364 depends on SYS_HAS_CPU_LOONGSON2F
1365 select CPU_LOONGSON2EF
1368 The Loongson 2F processor implements the MIPS III instruction set
1369 with many extensions.
1371 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1372 have a similar programming interface with FPGA northbridge used in
1375 config CPU_LOONGSON1B
1377 depends on SYS_HAS_CPU_LOONGSON1B
1378 select CPU_LOONGSON32
1379 select LEDS_GPIO_REGISTER
1381 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1382 Release 1 instruction set and part of the MIPS32 Release 2
1385 config CPU_LOONGSON1C
1387 depends on SYS_HAS_CPU_LOONGSON1C
1388 select CPU_LOONGSON32
1389 select LEDS_GPIO_REGISTER
1391 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
1392 Release 1 instruction set and part of the MIPS32 Release 2
1395 config CPU_MIPS32_R1
1396 bool "MIPS32 Release 1"
1397 depends on SYS_HAS_CPU_MIPS32_R1
1398 select CPU_HAS_PREFETCH
1399 select CPU_SUPPORTS_32BIT_KERNEL
1400 select CPU_SUPPORTS_HIGHMEM
1402 Choose this option to build a kernel for release 1 or later of the
1403 MIPS32 architecture. Most modern embedded systems with a 32-bit
1404 MIPS processor are based on a MIPS32 processor. If you know the
1405 specific type of processor in your system, choose those that one
1406 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1407 Release 2 of the MIPS32 architecture is available since several
1408 years so chances are you even have a MIPS32 Release 2 processor
1409 in which case you should choose CPU_MIPS32_R2 instead for better
1412 config CPU_MIPS32_R2
1413 bool "MIPS32 Release 2"
1414 depends on SYS_HAS_CPU_MIPS32_R2
1415 select CPU_HAS_PREFETCH
1416 select CPU_SUPPORTS_32BIT_KERNEL
1417 select CPU_SUPPORTS_HIGHMEM
1418 select CPU_SUPPORTS_MSA
1421 Choose this option to build a kernel for release 2 or later of the
1422 MIPS32 architecture. Most modern embedded systems with a 32-bit
1423 MIPS processor are based on a MIPS32 processor. If you know the
1424 specific type of processor in your system, choose those that one
1425 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1427 config CPU_MIPS32_R5
1428 bool "MIPS32 Release 5"
1429 depends on SYS_HAS_CPU_MIPS32_R5
1430 select CPU_HAS_PREFETCH
1431 select CPU_SUPPORTS_32BIT_KERNEL
1432 select CPU_SUPPORTS_HIGHMEM
1433 select CPU_SUPPORTS_MSA
1435 select MIPS_O32_FP64_SUPPORT
1437 Choose this option to build a kernel for release 5 or later of the
1438 MIPS32 architecture. New MIPS processors, starting with the Warrior
1439 family, are based on a MIPS32r5 processor. If you own an older
1440 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1442 config CPU_MIPS32_R6
1443 bool "MIPS32 Release 6"
1444 depends on SYS_HAS_CPU_MIPS32_R6
1445 select CPU_HAS_PREFETCH
1446 select CPU_NO_LOAD_STORE_LR
1447 select CPU_SUPPORTS_32BIT_KERNEL
1448 select CPU_SUPPORTS_HIGHMEM
1449 select CPU_SUPPORTS_MSA
1451 select MIPS_O32_FP64_SUPPORT
1453 Choose this option to build a kernel for release 6 or later of the
1454 MIPS32 architecture. New MIPS processors, starting with the Warrior
1455 family, are based on a MIPS32r6 processor. If you own an older
1456 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1458 config CPU_MIPS64_R1
1459 bool "MIPS64 Release 1"
1460 depends on SYS_HAS_CPU_MIPS64_R1
1461 select CPU_HAS_PREFETCH
1462 select CPU_SUPPORTS_32BIT_KERNEL
1463 select CPU_SUPPORTS_64BIT_KERNEL
1464 select CPU_SUPPORTS_HIGHMEM
1465 select CPU_SUPPORTS_HUGEPAGES
1467 Choose this option to build a kernel for release 1 or later of the
1468 MIPS64 architecture. Many modern embedded systems with a 64-bit
1469 MIPS processor are based on a MIPS64 processor. If you know the
1470 specific type of processor in your system, choose those that one
1471 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1472 Release 2 of the MIPS64 architecture is available since several
1473 years so chances are you even have a MIPS64 Release 2 processor
1474 in which case you should choose CPU_MIPS64_R2 instead for better
1477 config CPU_MIPS64_R2
1478 bool "MIPS64 Release 2"
1479 depends on SYS_HAS_CPU_MIPS64_R2
1480 select CPU_HAS_PREFETCH
1481 select CPU_SUPPORTS_32BIT_KERNEL
1482 select CPU_SUPPORTS_64BIT_KERNEL
1483 select CPU_SUPPORTS_HIGHMEM
1484 select CPU_SUPPORTS_HUGEPAGES
1485 select CPU_SUPPORTS_MSA
1488 Choose this option to build a kernel for release 2 or later of the
1489 MIPS64 architecture. Many modern embedded systems with a 64-bit
1490 MIPS processor are based on a MIPS64 processor. If you know the
1491 specific type of processor in your system, choose those that one
1492 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1494 config CPU_MIPS64_R5
1495 bool "MIPS64 Release 5"
1496 depends on SYS_HAS_CPU_MIPS64_R5
1497 select CPU_HAS_PREFETCH
1498 select CPU_SUPPORTS_32BIT_KERNEL
1499 select CPU_SUPPORTS_64BIT_KERNEL
1500 select CPU_SUPPORTS_HIGHMEM
1501 select CPU_SUPPORTS_HUGEPAGES
1502 select CPU_SUPPORTS_MSA
1503 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
1506 Choose this option to build a kernel for release 5 or later of the
1507 MIPS64 architecture. This is a intermediate MIPS architecture
1508 release partly implementing release 6 features. Though there is no
1509 any hardware known to be based on this release.
1511 config CPU_MIPS64_R6
1512 bool "MIPS64 Release 6"
1513 depends on SYS_HAS_CPU_MIPS64_R6
1514 select CPU_HAS_PREFETCH
1515 select CPU_NO_LOAD_STORE_LR
1516 select CPU_SUPPORTS_32BIT_KERNEL
1517 select CPU_SUPPORTS_64BIT_KERNEL
1518 select CPU_SUPPORTS_HIGHMEM
1519 select CPU_SUPPORTS_HUGEPAGES
1520 select CPU_SUPPORTS_MSA
1521 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
1524 Choose this option to build a kernel for release 6 or later of the
1525 MIPS64 architecture. New MIPS processors, starting with the Warrior
1526 family, are based on a MIPS64r6 processor. If you own an older
1527 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
1530 bool "MIPS Warrior P5600"
1531 depends on SYS_HAS_CPU_P5600
1532 select CPU_HAS_PREFETCH
1533 select CPU_SUPPORTS_32BIT_KERNEL
1534 select CPU_SUPPORTS_HIGHMEM
1535 select CPU_SUPPORTS_MSA
1536 select CPU_SUPPORTS_CPUFREQ
1537 select CPU_MIPSR2_IRQ_VI
1538 select CPU_MIPSR2_IRQ_EI
1540 select MIPS_O32_FP64_SUPPORT
1542 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
1543 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
1544 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
1545 level features like up to six P5600 calculation cores, CM2 with L2
1546 cache, IOCU/IOMMU (though might be unused depending on the system-
1547 specific IP core configuration), GIC, CPC, virtualisation module,
1552 depends on SYS_HAS_CPU_R3000
1555 select CPU_SUPPORTS_32BIT_KERNEL
1556 select CPU_SUPPORTS_HIGHMEM
1558 Please make sure to pick the right CPU type. Linux/MIPS is not
1559 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
1560 *not* work on R4000 machines and vice versa. However, since most
1561 of the supported machines have an R4000 (or similar) CPU, R4x00
1562 might be a safe bet. If the resulting kernel does not work,
1563 try to recompile with R3000.
1567 depends on SYS_HAS_CPU_R4300
1568 select CPU_SUPPORTS_32BIT_KERNEL
1569 select CPU_SUPPORTS_64BIT_KERNEL
1571 MIPS Technologies R4300-series processors.
1575 depends on SYS_HAS_CPU_R4X00
1576 select CPU_SUPPORTS_32BIT_KERNEL
1577 select CPU_SUPPORTS_64BIT_KERNEL
1578 select CPU_SUPPORTS_HUGEPAGES
1580 MIPS Technologies R4000-series processors other than 4300, including
1581 the R4000, R4400, R4600, and 4700.
1585 depends on SYS_HAS_CPU_TX49XX
1586 select CPU_HAS_PREFETCH
1587 select CPU_SUPPORTS_32BIT_KERNEL
1588 select CPU_SUPPORTS_64BIT_KERNEL
1589 select CPU_SUPPORTS_HUGEPAGES
1593 depends on SYS_HAS_CPU_R5000
1594 select CPU_SUPPORTS_32BIT_KERNEL
1595 select CPU_SUPPORTS_64BIT_KERNEL
1596 select CPU_SUPPORTS_HUGEPAGES
1598 MIPS Technologies R5000-series processors other than the Nevada.
1602 depends on SYS_HAS_CPU_R5500
1603 select CPU_SUPPORTS_32BIT_KERNEL
1604 select CPU_SUPPORTS_64BIT_KERNEL
1605 select CPU_SUPPORTS_HUGEPAGES
1607 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1612 depends on SYS_HAS_CPU_NEVADA
1613 select CPU_SUPPORTS_32BIT_KERNEL
1614 select CPU_SUPPORTS_64BIT_KERNEL
1615 select CPU_SUPPORTS_HUGEPAGES
1617 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1621 depends on SYS_HAS_CPU_R10000
1622 select CPU_HAS_PREFETCH
1623 select CPU_SUPPORTS_32BIT_KERNEL
1624 select CPU_SUPPORTS_64BIT_KERNEL
1625 select CPU_SUPPORTS_HIGHMEM
1626 select CPU_SUPPORTS_HUGEPAGES
1628 MIPS Technologies R10000-series processors.
1632 depends on SYS_HAS_CPU_RM7000
1633 select CPU_HAS_PREFETCH
1634 select CPU_SUPPORTS_32BIT_KERNEL
1635 select CPU_SUPPORTS_64BIT_KERNEL
1636 select CPU_SUPPORTS_HIGHMEM
1637 select CPU_SUPPORTS_HUGEPAGES
1641 depends on SYS_HAS_CPU_SB1
1642 select CPU_SUPPORTS_32BIT_KERNEL
1643 select CPU_SUPPORTS_64BIT_KERNEL
1644 select CPU_SUPPORTS_HIGHMEM
1645 select CPU_SUPPORTS_HUGEPAGES
1646 select WEAK_ORDERING
1648 config CPU_CAVIUM_OCTEON
1649 bool "Cavium Octeon processor"
1650 depends on SYS_HAS_CPU_CAVIUM_OCTEON
1651 select CPU_HAS_PREFETCH
1652 select CPU_SUPPORTS_64BIT_KERNEL
1653 select WEAK_ORDERING
1654 select CPU_SUPPORTS_HIGHMEM
1655 select CPU_SUPPORTS_HUGEPAGES
1656 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
1657 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
1658 select MIPS_L1_CACHE_SHIFT_7
1661 The Cavium Octeon processor is a highly integrated chip containing
1662 many ethernet hardware widgets for networking tasks. The processor
1663 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
1664 Full details can be found at http://www.caviumnetworks.com.
1667 bool "Broadcom BMIPS"
1668 depends on SYS_HAS_CPU_BMIPS
1670 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
1671 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
1672 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
1673 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
1674 select CPU_SUPPORTS_32BIT_KERNEL
1675 select DMA_NONCOHERENT
1677 select SWAP_IO_SPACE
1678 select WEAK_ORDERING
1679 select CPU_SUPPORTS_HIGHMEM
1680 select CPU_HAS_PREFETCH
1681 select CPU_SUPPORTS_CPUFREQ
1682 select MIPS_EXTERNAL_TIMER
1683 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
1685 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
1689 config CPU_MIPS32_3_5_FEATURES
1690 bool "MIPS32 Release 3.5 Features"
1691 depends on SYS_HAS_CPU_MIPS32_R3_5
1692 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
1695 Choose this option to build a kernel for release 2 or later of the
1696 MIPS32 architecture including features from the 3.5 release such as
1697 support for Enhanced Virtual Addressing (EVA).
1699 config CPU_MIPS32_3_5_EVA
1700 bool "Enhanced Virtual Addressing (EVA)"
1701 depends on CPU_MIPS32_3_5_FEATURES
1705 Choose this option if you want to enable the Enhanced Virtual
1706 Addressing (EVA) on your MIPS32 core (such as proAptiv).
1707 One of its primary benefits is an increase in the maximum size
1708 of lowmem (up to 3GB). If unsure, say 'N' here.
1710 config CPU_MIPS32_R5_FEATURES
1711 bool "MIPS32 Release 5 Features"
1712 depends on SYS_HAS_CPU_MIPS32_R5
1713 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
1715 Choose this option to build a kernel for release 2 or later of the
1716 MIPS32 architecture including features from release 5 such as
1717 support for Extended Physical Addressing (XPA).
1719 config CPU_MIPS32_R5_XPA
1720 bool "Extended Physical Addressing (XPA)"
1721 depends on CPU_MIPS32_R5_FEATURES
1723 depends on !PAGE_SIZE_4KB
1724 depends on SYS_SUPPORTS_HIGHMEM
1727 select PHYS_ADDR_T_64BIT
1730 Choose this option if you want to enable the Extended Physical
1731 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
1732 benefit is to increase physical addressing equal to or greater
1733 than 40 bits. Note that this has the side effect of turning on
1734 64-bit addressing which in turn makes the PTEs 64-bit in size.
1735 If unsure, say 'N' here.
1738 config CPU_NOP_WORKAROUNDS
1741 config CPU_JUMP_WORKAROUNDS
1744 config CPU_LOONGSON2F_WORKAROUNDS
1745 bool "Loongson 2F Workarounds"
1747 select CPU_NOP_WORKAROUNDS
1748 select CPU_JUMP_WORKAROUNDS
1750 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1751 require workarounds. Without workarounds the system may hang
1752 unexpectedly. For more information please refer to the gas
1753 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1755 Loongson 2F03 and later have fixed these issues and no workarounds
1756 are needed. The workarounds have no significant side effect on them
1757 but may decrease the performance of the system so this option should
1758 be disabled unless the kernel is intended to be run on 2F01 or 2F02
1761 If unsure, please say Y.
1762 endif # CPU_LOONGSON2F
1764 config SYS_SUPPORTS_ZBOOT
1766 select HAVE_KERNEL_GZIP
1767 select HAVE_KERNEL_BZIP2
1768 select HAVE_KERNEL_LZ4
1769 select HAVE_KERNEL_LZMA
1770 select HAVE_KERNEL_LZO
1771 select HAVE_KERNEL_XZ
1772 select HAVE_KERNEL_ZSTD
1774 config SYS_SUPPORTS_ZBOOT_UART16550
1776 select SYS_SUPPORTS_ZBOOT
1778 config SYS_SUPPORTS_ZBOOT_UART_PROM
1780 select SYS_SUPPORTS_ZBOOT
1782 config CPU_LOONGSON2EF
1784 select CPU_SUPPORTS_32BIT_KERNEL
1785 select CPU_SUPPORTS_64BIT_KERNEL
1786 select CPU_SUPPORTS_HIGHMEM
1787 select CPU_SUPPORTS_HUGEPAGES
1788 select ARCH_HAS_PHYS_TO_DMA
1790 config CPU_LOONGSON32
1794 select CPU_HAS_PREFETCH
1795 select CPU_SUPPORTS_32BIT_KERNEL
1796 select CPU_SUPPORTS_HIGHMEM
1797 select CPU_SUPPORTS_CPUFREQ
1799 config CPU_BMIPS32_3300
1800 select SMP_UP if SMP
1803 config CPU_BMIPS4350
1805 select SYS_SUPPORTS_SMP
1806 select SYS_SUPPORTS_HOTPLUG_CPU
1808 config CPU_BMIPS4380
1810 select MIPS_L1_CACHE_SHIFT_6
1811 select SYS_SUPPORTS_SMP
1812 select SYS_SUPPORTS_HOTPLUG_CPU
1815 config CPU_BMIPS5000
1817 select MIPS_CPU_SCACHE
1818 select MIPS_L1_CACHE_SHIFT_7
1819 select SYS_SUPPORTS_SMP
1820 select SYS_SUPPORTS_HOTPLUG_CPU
1823 config SYS_HAS_CPU_LOONGSON64
1825 select CPU_SUPPORTS_CPUFREQ
1828 config SYS_HAS_CPU_LOONGSON2E
1831 config SYS_HAS_CPU_LOONGSON2F
1833 select CPU_SUPPORTS_CPUFREQ
1834 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1836 config SYS_HAS_CPU_LOONGSON1B
1839 config SYS_HAS_CPU_LOONGSON1C
1842 config SYS_HAS_CPU_MIPS32_R1
1845 config SYS_HAS_CPU_MIPS32_R2
1848 config SYS_HAS_CPU_MIPS32_R3_5
1851 config SYS_HAS_CPU_MIPS32_R5
1853 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1855 config SYS_HAS_CPU_MIPS32_R6
1857 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1859 config SYS_HAS_CPU_MIPS64_R1
1862 config SYS_HAS_CPU_MIPS64_R2
1865 config SYS_HAS_CPU_MIPS64_R5
1867 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1869 config SYS_HAS_CPU_MIPS64_R6
1871 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1873 config SYS_HAS_CPU_P5600
1875 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1877 config SYS_HAS_CPU_R3000
1880 config SYS_HAS_CPU_R4300
1883 config SYS_HAS_CPU_R4X00
1886 config SYS_HAS_CPU_TX49XX
1889 config SYS_HAS_CPU_R5000
1892 config SYS_HAS_CPU_R5500
1895 config SYS_HAS_CPU_NEVADA
1898 config SYS_HAS_CPU_R10000
1900 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1902 config SYS_HAS_CPU_RM7000
1905 config SYS_HAS_CPU_SB1
1908 config SYS_HAS_CPU_CAVIUM_OCTEON
1911 config SYS_HAS_CPU_BMIPS
1914 config SYS_HAS_CPU_BMIPS32_3300
1916 select SYS_HAS_CPU_BMIPS
1918 config SYS_HAS_CPU_BMIPS4350
1920 select SYS_HAS_CPU_BMIPS
1922 config SYS_HAS_CPU_BMIPS4380
1924 select SYS_HAS_CPU_BMIPS
1926 config SYS_HAS_CPU_BMIPS5000
1928 select SYS_HAS_CPU_BMIPS
1929 select ARCH_HAS_SYNC_DMA_FOR_CPU
1932 # CPU may reorder R->R, R->W, W->R, W->W
1933 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1935 config WEAK_ORDERING
1939 # CPU may reorder reads and writes beyond LL/SC
1940 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1942 config WEAK_REORDERING_BEYOND_LLSC
1947 # These two indicate any level of the MIPS32 and MIPS64 architecture
1951 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
1952 CPU_MIPS32_R6 || CPU_P5600
1956 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
1957 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1960 # These indicate the revision of the architecture
1964 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1968 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1970 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1975 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
1977 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1982 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
1984 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1985 select HAVE_ARCH_BITREVERSE
1986 select MIPS_ASID_BITS_VARIABLE
1987 select MIPS_CRC_SUPPORT
1990 config TARGET_ISA_REV
1992 default 1 if CPU_MIPSR1
1993 default 2 if CPU_MIPSR2
1994 default 5 if CPU_MIPSR5
1995 default 6 if CPU_MIPSR6
1998 Reflects the ISA revision being targeted by the kernel build. This
1999 is effectively the Kconfig equivalent of MIPS_ISA_REV.
2007 config SYS_SUPPORTS_32BIT_KERNEL
2009 config SYS_SUPPORTS_64BIT_KERNEL
2011 config CPU_SUPPORTS_32BIT_KERNEL
2013 config CPU_SUPPORTS_64BIT_KERNEL
2015 config CPU_SUPPORTS_CPUFREQ
2017 config CPU_SUPPORTS_ADDRWINCFG
2019 config CPU_SUPPORTS_HUGEPAGES
2021 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
2022 config MIPS_PGD_C0_CONTEXT
2025 default y if (CPU_MIPSR2 || CPU_MIPSR6)
2028 # Set to y for ptrace access to watch registers.
2030 config HARDWARE_WATCHPOINTS
2032 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
2037 prompt "Kernel code model"
2039 You should only select this option if you have a workload that
2040 actually benefits from 64-bit processing or if your machine has
2041 large memory. You will only be presented a single option in this
2042 menu if your system does not support both 32-bit and 64-bit kernels.
2045 bool "32-bit kernel"
2046 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
2049 Select this option if you want to build a 32-bit kernel.
2052 bool "64-bit kernel"
2053 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
2055 Select this option if you want to build a 64-bit kernel.
2059 config MIPS_VA_BITS_48
2060 bool "48 bits virtual memory"
2063 Support a maximum at least 48 bits of application virtual
2064 memory. Default is 40 bits or less, depending on the CPU.
2065 For page sizes 16k and above, this option results in a small
2066 memory overhead for page tables. For 4k page size, a fourth
2067 level of page tables is added which imposes both a memory
2068 overhead as well as slower TLB fault handling.
2072 config ZBOOT_LOAD_ADDRESS
2073 hex "Compressed kernel load address"
2074 default 0xffffffff80400000 if BCM47XX
2076 depends on SYS_SUPPORTS_ZBOOT
2078 The address to load compressed kernel, aka vmlinuz.
2080 This is only used if non-zero.
2083 prompt "Kernel page size"
2084 default PAGE_SIZE_4KB
2086 config PAGE_SIZE_4KB
2088 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
2090 This option select the standard 4kB Linux page size. On some
2091 R3000-family processors this is the only available page size. Using
2092 4kB page size will minimize memory consumption and is therefore
2093 recommended for low memory systems.
2095 config PAGE_SIZE_8KB
2097 depends on CPU_CAVIUM_OCTEON
2098 depends on !MIPS_VA_BITS_48
2100 Using 8kB page size will result in higher performance kernel at
2101 the price of higher memory consumption. This option is available
2102 only on cnMIPS processors. Note that you will need a suitable Linux
2103 distribution to support this.
2105 config PAGE_SIZE_16KB
2107 depends on !CPU_R3000
2109 Using 16kB page size will result in higher performance kernel at
2110 the price of higher memory consumption. This option is available on
2111 all non-R3000 family processors. Note that you will need a suitable
2112 Linux distribution to support this.
2114 config PAGE_SIZE_32KB
2116 depends on CPU_CAVIUM_OCTEON
2117 depends on !MIPS_VA_BITS_48
2119 Using 32kB page size will result in higher performance kernel at
2120 the price of higher memory consumption. This option is available
2121 only on cnMIPS cores. Note that you will need a suitable Linux
2122 distribution to support this.
2124 config PAGE_SIZE_64KB
2126 depends on !CPU_R3000
2128 Using 64kB page size will result in higher performance kernel at
2129 the price of higher memory consumption. This option is available on
2130 all non-R3000 family processor. Not that at the time of this
2131 writing this option is still high experimental.
2135 config ARCH_FORCE_MAX_ORDER
2136 int "Maximum zone order"
2137 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
2138 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
2139 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
2140 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
2141 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
2142 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
2146 The kernel memory allocator divides physically contiguous memory
2147 blocks into "zones", where each zone is a power of two number of
2148 pages. This option selects the largest power of two that the kernel
2149 keeps in the memory allocator. If you need to allocate very large
2150 blocks of physically contiguous memory, then you may need to
2151 increase this value.
2153 This config option is actually maximum order plus one. For example,
2154 a value of 11 means that the largest free memory block is 2^10 pages.
2156 The page size is not necessarily 4KB. Keep this in mind
2157 when choosing a value for this option.
2162 config IP22_CPU_SCACHE
2167 # Support for a MIPS32 / MIPS64 style S-caches
2169 config MIPS_CPU_SCACHE
2173 config R5000_CPU_SCACHE
2177 config RM7000_CPU_SCACHE
2181 config SIBYTE_DMA_PAGEOPS
2182 bool "Use DMA to clear/copy pages"
2185 Instead of using the CPU to zero and copy pages, use a Data Mover
2186 channel. These DMA channels are otherwise unused by the standard
2187 SiByte Linux port. Seems to give a small performance benefit.
2189 config CPU_HAS_PREFETCH
2192 config CPU_GENERIC_DUMP_TLB
2194 default y if !CPU_R3000
2196 config MIPS_FP_SUPPORT
2197 bool "Floating Point support" if EXPERT
2200 Select y to include support for floating point in the kernel
2201 including initialization of FPU hardware, FP context save & restore
2202 and emulation of an FPU where necessary. Without this support any
2203 userland program attempting to use floating point instructions will
2206 If you know that your userland will not attempt to use floating point
2207 instructions then you can say n here to shrink the kernel a little.
2211 config CPU_R2300_FPU
2213 depends on MIPS_FP_SUPPORT
2214 default y if CPU_R3000
2221 depends on MIPS_FP_SUPPORT
2222 default y if !CPU_R2300_FPU
2224 config CPU_R4K_CACHE_TLB
2226 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
2229 bool "MIPS MT SMP support (1 TC on each available VPE)"
2231 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
2232 select CPU_MIPSR2_IRQ_VI
2233 select CPU_MIPSR2_IRQ_EI
2238 select SYS_SUPPORTS_SMP
2239 select SYS_SUPPORTS_SCHED_SMT
2240 select MIPS_PERF_SHARED_TC_COUNTERS
2242 This is a kernel model which is known as SMVP. This is supported
2243 on cores with the MT ASE and uses the available VPEs to implement
2244 virtual processors which supports SMP. This is equivalent to the
2245 Intel Hyperthreading feature. For further information go to
2246 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2252 bool "SMT (multithreading) scheduler support"
2253 depends on SYS_SUPPORTS_SCHED_SMT
2256 SMT scheduler support improves the CPU scheduler's decision making
2257 when dealing with MIPS MT enabled cores at a cost of slightly
2258 increased overhead in some places. If unsure say N here.
2260 config SYS_SUPPORTS_SCHED_SMT
2263 config SYS_SUPPORTS_MULTITHREADING
2266 config MIPS_MT_FPAFF
2267 bool "Dynamic FPU affinity for FP-intensive threads"
2269 depends on MIPS_MT_SMP
2271 config MIPSR2_TO_R6_EMULATOR
2272 bool "MIPS R2-to-R6 emulator"
2273 depends on CPU_MIPSR6
2274 depends on MIPS_FP_SUPPORT
2277 Choose this option if you want to run non-R6 MIPS userland code.
2278 Even if you say 'Y' here, the emulator will still be disabled by
2279 default. You can enable it using the 'mipsr2emu' kernel option.
2280 The only reason this is a build-time option is to save ~14K from the
2283 config SYS_SUPPORTS_VPE_LOADER
2285 depends on SYS_SUPPORTS_MULTITHREADING
2287 Indicates that the platform supports the VPE loader, and provides
2290 config MIPS_VPE_LOADER
2291 bool "VPE loader support."
2292 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
2293 select CPU_MIPSR2_IRQ_VI
2294 select CPU_MIPSR2_IRQ_EI
2297 Includes a loader for loading an elf relocatable object
2298 onto another VPE and running it.
2300 config MIPS_VPE_LOADER_CMP
2303 depends on MIPS_VPE_LOADER && MIPS_CMP
2305 config MIPS_VPE_LOADER_MT
2308 depends on MIPS_VPE_LOADER && !MIPS_CMP
2310 config MIPS_VPE_LOADER_TOM
2311 bool "Load VPE program into memory hidden from linux"
2312 depends on MIPS_VPE_LOADER
2315 The loader can use memory that is present but has been hidden from
2316 Linux using the kernel command line option "mem=xxMB". It's up to
2317 you to ensure the amount you put in the option and the space your
2318 program requires is less or equal to the amount physically present.
2320 config MIPS_VPE_APSP_API
2321 bool "Enable support for AP/SP API (RTLX)"
2322 depends on MIPS_VPE_LOADER
2324 config MIPS_VPE_APSP_API_CMP
2327 depends on MIPS_VPE_APSP_API && MIPS_CMP
2329 config MIPS_VPE_APSP_API_MT
2332 depends on MIPS_VPE_APSP_API && !MIPS_CMP
2335 bool "MIPS CMP framework support (DEPRECATED)"
2336 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
2339 select SYS_SUPPORTS_SMP
2340 select WEAK_ORDERING
2343 Select this if you are using a bootloader which implements the "CMP
2344 framework" protocol (ie. YAMON) and want your kernel to make use of
2345 its ability to start secondary CPUs.
2347 Unless you have a specific need, you should use CONFIG_MIPS_CPS
2351 bool "MIPS Coherent Processing System support"
2352 depends on SYS_SUPPORTS_MIPS_CPS
2354 select MIPS_CPS_PM if HOTPLUG_CPU
2356 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
2357 select SYS_SUPPORTS_HOTPLUG_CPU
2358 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
2359 select SYS_SUPPORTS_SMP
2360 select WEAK_ORDERING
2361 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
2363 Select this if you wish to run an SMP kernel across multiple cores
2364 within a MIPS Coherent Processing System. When this option is
2365 enabled the kernel will probe for other cores and boot them with
2366 no external assistance. It is safe to enable this when hardware
2367 support is unavailable.
2380 config SB1_PASS_2_WORKAROUNDS
2382 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
2385 config SB1_PASS_2_1_WORKAROUNDS
2387 depends on CPU_SB1 && CPU_SB1_PASS_2
2391 prompt "SmartMIPS or microMIPS ASE support"
2393 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
2396 Select this if you want neither microMIPS nor SmartMIPS support
2398 config CPU_HAS_SMARTMIPS
2399 depends on SYS_SUPPORTS_SMARTMIPS
2402 SmartMIPS is a extension of the MIPS32 architecture aimed at
2403 increased security at both hardware and software level for
2404 smartcards. Enabling this option will allow proper use of the
2405 SmartMIPS instructions by Linux applications. However a kernel with
2406 this option will not work on a MIPS core without SmartMIPS core. If
2407 you don't know you probably don't have SmartMIPS and should say N
2410 config CPU_MICROMIPS
2411 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
2414 When this option is enabled the kernel will be built using the
2420 bool "Support for the MIPS SIMD Architecture"
2421 depends on CPU_SUPPORTS_MSA
2422 depends on MIPS_FP_SUPPORT
2423 depends on 64BIT || MIPS_O32_FP64_SUPPORT
2425 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
2426 and a set of SIMD instructions to operate on them. When this option
2427 is enabled the kernel will support allocating & switching MSA
2428 vector register contexts. If you know that your kernel will only be
2429 running on CPUs which do not support MSA or that your userland will
2430 not be making use of it then you may wish to say N here to reduce
2431 the size & complexity of your kernel.
2442 depends on !CPU_DIEI_BROKEN
2445 config CPU_DIEI_BROKEN
2451 config CPU_NO_LOAD_STORE_LR
2454 CPU lacks support for unaligned load and store instructions:
2455 LWL, LWR, SWL, SWR (Load/store word left/right).
2456 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
2460 # Vectored interrupt mode is an R2 feature
2462 config CPU_MIPSR2_IRQ_VI
2466 # Extended interrupt mode is an R2 feature
2468 config CPU_MIPSR2_IRQ_EI
2473 depends on !CPU_R3000
2480 # Work around the "daddi" and "daddiu" CPU errata:
2482 # - The `daddi' instruction fails to trap on overflow.
2483 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2486 # - The `daddiu' instruction can produce an incorrect result.
2487 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2489 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2491 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
2492 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
2493 config CPU_DADDI_WORKAROUNDS
2496 # Work around certain R4000 CPU errata (as implemented by GCC):
2498 # - A double-word or a variable shift may give an incorrect result
2499 # if executed immediately after starting an integer division:
2500 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2502 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2505 # - A double-word or a variable shift may give an incorrect result
2506 # if executed while an integer multiplication is in progress:
2507 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2510 # - An integer division may give an incorrect result if started in
2511 # a delay slot of a taken branch or a jump:
2512 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2514 config CPU_R4000_WORKAROUNDS
2516 select CPU_R4400_WORKAROUNDS
2518 # Work around certain R4400 CPU errata (as implemented by GCC):
2520 # - A double-word or a variable shift may give an incorrect result
2521 # if executed immediately after starting an integer division:
2522 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
2523 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
2524 config CPU_R4400_WORKAROUNDS
2527 config CPU_R4X00_BUGS64
2529 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
2531 config MIPS_ASID_SHIFT
2533 default 6 if CPU_R3000
2536 config MIPS_ASID_BITS
2538 default 0 if MIPS_ASID_BITS_VARIABLE
2539 default 6 if CPU_R3000
2542 config MIPS_ASID_BITS_VARIABLE
2545 config MIPS_CRC_SUPPORT
2548 # R4600 erratum. Due to the lack of errata information the exact
2549 # technical details aren't known. I've experimentally found that disabling
2550 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2552 config WAR_R4600_V1_INDEX_ICACHEOP
2555 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
2557 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
2558 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
2559 # executed if there is no other dcache activity. If the dcache is
2560 # accessed for another instruction immediately preceding when these
2561 # cache instructions are executing, it is possible that the dcache
2562 # tag match outputs used by these cache instructions will be
2563 # incorrect. These cache instructions should be preceded by at least
2564 # four instructions that are not any kind of load or store
2567 # This is not allowed: lw
2571 # cache Hit_Writeback_Invalidate_D
2573 # This is allowed: lw
2578 # cache Hit_Writeback_Invalidate_D
2579 config WAR_R4600_V1_HIT_CACHEOP
2582 # Writeback and invalidate the primary cache dcache before DMA.
2584 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
2585 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
2586 # operate correctly if the internal data cache refill buffer is empty. These
2587 # CACHE instructions should be separated from any potential data cache miss
2588 # by a load instruction to an uncached address to empty the response buffer."
2589 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
2591 config WAR_R4600_V2_HIT_CACHEOP
2594 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
2595 # the line which this instruction itself exists, the following
2596 # operation is not guaranteed."
2598 # Workaround: do two phase flushing for Index_Invalidate_I
2599 config WAR_TX49XX_ICACHE_INDEX_INV
2602 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2603 # opposes it being called that) where invalid instructions in the same
2604 # I-cache line worth of instructions being fetched may case spurious
2606 config WAR_ICACHE_REFILLS
2609 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
2610 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2611 config WAR_R10000_LLSC
2614 # 34K core erratum: "Problems Executing the TLBR Instruction"
2615 config WAR_MIPS34K_MISSED_ITLB
2619 # - Highmem only makes sense for the 32-bit kernel.
2620 # - The current highmem code will only work properly on physically indexed
2621 # caches such as R3000, SB1, R7000 or those that look like they're virtually
2622 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
2623 # moment we protect the user and offer the highmem option only on machines
2624 # where it's known to be safe. This will not offer highmem on a few systems
2625 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
2626 # indexed CPUs but we're playing safe.
2627 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2628 # know they might have memory configurations that could make use of highmem
2632 bool "High Memory Support"
2633 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
2636 config CPU_SUPPORTS_HIGHMEM
2639 config SYS_SUPPORTS_HIGHMEM
2642 config SYS_SUPPORTS_SMARTMIPS
2645 config SYS_SUPPORTS_MICROMIPS
2648 config SYS_SUPPORTS_MIPS16
2651 This option must be set if a kernel might be executed on a MIPS16-
2652 enabled CPU even if MIPS16 is not actually being used. In other
2653 words, it makes the kernel MIPS16-tolerant.
2655 config CPU_SUPPORTS_MSA
2658 config ARCH_FLATMEM_ENABLE
2660 depends on !NUMA && !CPU_LOONGSON2EF
2662 config ARCH_SPARSEMEM_ENABLE
2667 depends on SYS_SUPPORTS_NUMA
2669 select HAVE_SETUP_PER_CPU_AREA
2670 select NEED_PER_CPU_EMBED_FIRST_CHUNK
2672 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2673 Access). This option improves performance on systems with more
2674 than two nodes; on two node systems it is generally better to
2675 leave it disabled; on single node systems leave this option
2678 config SYS_SUPPORTS_NUMA
2681 config HAVE_ARCH_NODEDATA_EXTENSION
2685 bool "Relocatable kernel"
2686 depends on SYS_SUPPORTS_RELOCATABLE
2687 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
2688 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
2689 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
2690 CPU_P5600 || CAVIUM_OCTEON_SOC || \
2693 This builds a kernel image that retains relocation information
2694 so it can be loaded someplace besides the default 1MB.
2695 The relocations make the kernel binary about 15% larger,
2696 but are discarded at runtime
2698 config RELOCATION_TABLE_SIZE
2699 hex "Relocation table size"
2700 depends on RELOCATABLE
2701 range 0x0 0x01000000
2702 default "0x00200000" if CPU_LOONGSON64
2703 default "0x00100000"
2705 A table of relocation data will be appended to the kernel binary
2706 and parsed at boot to fix up the relocated kernel.
2708 This option allows the amount of space reserved for the table to be
2709 adjusted, although the default of 1Mb should be ok in most cases.
2711 The build will fail and a valid size suggested if this is too small.
2713 If unsure, leave at the default value.
2715 config RANDOMIZE_BASE
2716 bool "Randomize the address of the kernel image"
2717 depends on RELOCATABLE
2719 Randomizes the physical and virtual address at which the
2720 kernel image is loaded, as a security feature that
2721 deters exploit attempts relying on knowledge of the location
2722 of kernel internals.
2724 Entropy is generated using any coprocessor 0 registers available.
2726 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
2730 config RANDOMIZE_BASE_MAX_OFFSET
2731 hex "Maximum kASLR offset" if EXPERT
2732 depends on RANDOMIZE_BASE
2733 range 0x0 0x40000000 if EVA || 64BIT
2734 range 0x0 0x08000000
2735 default "0x01000000"
2737 When kASLR is active, this provides the maximum offset that will
2738 be applied to the kernel image. It should be set according to the
2739 amount of physical RAM available in the target system minus
2740 PHYSICAL_START and must be a power of 2.
2742 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2743 EVA or 64-bit. The default is 16Mb.
2750 config HW_PERF_EVENTS
2751 bool "Enable hardware performance counter support for perf events"
2752 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
2755 Enable hardware performance counter support for perf events. If
2756 disabled, perf events will use software events only.
2759 bool "Enable DMI scanning"
2760 depends on MACH_LOONGSON64
2761 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
2764 Enabled scanning of DMI to identify machine quirks. Say Y
2765 here unless you have verified that your setup is not
2766 affected by entries in the DMI blacklist. Required by PNP
2770 bool "Multi-Processing support"
2771 depends on SYS_SUPPORTS_SMP
2773 This enables support for systems with more than one CPU. If you have
2774 a system with only one CPU, say N. If you have a system with more
2775 than one CPU, say Y.
2777 If you say N here, the kernel will run on uni- and multiprocessor
2778 machines, but will use only one CPU of a multiprocessor machine. If
2779 you say Y here, the kernel will run on many, but not all,
2780 uniprocessor machines. On a uniprocessor machine, the kernel
2781 will run faster if you say N here.
2783 People using multiprocessor machines who say Y here should also say
2784 Y to "Enhanced Real Time Clock Support", below.
2786 See also the SMP-HOWTO available at
2787 <https://www.tldp.org/docs.html#howto>.
2789 If you don't know what to do here, say N.
2792 bool "Support for hot-pluggable CPUs"
2793 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
2795 Say Y here to allow turning CPUs off and on. CPUs can be
2796 controlled through /sys/devices/system/cpu.
2797 (Note: power management support will enable this option
2798 automatically on SMP systems. )
2799 Say N if you want to disable CPU hotplug.
2804 config SYS_SUPPORTS_MIPS_CMP
2807 config SYS_SUPPORTS_MIPS_CPS
2810 config SYS_SUPPORTS_SMP
2813 config NR_CPUS_DEFAULT_4
2816 config NR_CPUS_DEFAULT_8
2819 config NR_CPUS_DEFAULT_16
2822 config NR_CPUS_DEFAULT_32
2825 config NR_CPUS_DEFAULT_64
2829 int "Maximum number of CPUs (2-256)"
2832 default "4" if NR_CPUS_DEFAULT_4
2833 default "8" if NR_CPUS_DEFAULT_8
2834 default "16" if NR_CPUS_DEFAULT_16
2835 default "32" if NR_CPUS_DEFAULT_32
2836 default "64" if NR_CPUS_DEFAULT_64
2838 This allows you to specify the maximum number of CPUs which this
2839 kernel will support. The maximum supported value is 32 for 32-bit
2840 kernel and 64 for 64-bit kernels; the minimum value which makes
2841 sense is 1 for Qemu (useful only for kernel debugging purposes)
2842 and 2 for all others.
2844 This is purely to save memory - each supported CPU adds
2845 approximately eight kilobytes to the kernel image. For best
2846 performance should round up your number of processors to the next
2849 config MIPS_PERF_SHARED_TC_COUNTERS
2852 config MIPS_NR_CPU_NR_MAP_1024
2855 config MIPS_NR_CPU_NR_MAP
2858 default 1024 if MIPS_NR_CPU_NR_MAP_1024
2859 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
2862 # Timer Interrupt Frequency Configuration
2866 prompt "Timer frequency"
2869 Allows the configuration of the timer frequency.
2872 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2875 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2878 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2881 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2884 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2887 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2890 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2893 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2897 config SYS_SUPPORTS_24HZ
2900 config SYS_SUPPORTS_48HZ
2903 config SYS_SUPPORTS_100HZ
2906 config SYS_SUPPORTS_128HZ
2909 config SYS_SUPPORTS_250HZ
2912 config SYS_SUPPORTS_256HZ
2915 config SYS_SUPPORTS_1000HZ
2918 config SYS_SUPPORTS_1024HZ
2921 config SYS_SUPPORTS_ARBIT_HZ
2923 default y if !SYS_SUPPORTS_24HZ && \
2924 !SYS_SUPPORTS_48HZ && \
2925 !SYS_SUPPORTS_100HZ && \
2926 !SYS_SUPPORTS_128HZ && \
2927 !SYS_SUPPORTS_250HZ && \
2928 !SYS_SUPPORTS_256HZ && \
2929 !SYS_SUPPORTS_1000HZ && \
2930 !SYS_SUPPORTS_1024HZ
2936 default 100 if HZ_100
2937 default 128 if HZ_128
2938 default 250 if HZ_250
2939 default 256 if HZ_256
2940 default 1000 if HZ_1000
2941 default 1024 if HZ_1024
2944 def_bool HIGH_RES_TIMERS
2947 bool "Kexec system call"
2950 kexec is a system call that implements the ability to shutdown your
2951 current kernel, and to start another kernel. It is like a reboot
2952 but it is independent of the system firmware. And like a reboot
2953 you can start any kernel with it, not just Linux.
2955 The name comes from the similarity to the exec system call.
2957 It is an ongoing process to be certain the hardware in a machine
2958 is properly shutdown, so do not be surprised if this code does not
2959 initially work for you. As of this writing the exact hardware
2960 interface is strongly in flux, so no good recommendation can be
2964 bool "Kernel crash dumps"
2966 Generate crash dump after being started by kexec.
2967 This should be normally only set in special crash dump kernels
2968 which are loaded in the main kernel with kexec-tools into
2969 a specially reserved region and then later executed after
2970 a crash by kdump/kexec. The crash dump kernel must be compiled
2971 to a memory address not used by the main kernel or firmware using
2974 config PHYSICAL_START
2975 hex "Physical address where the kernel is loaded"
2976 default "0xffffffff84000000"
2977 depends on CRASH_DUMP
2979 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
2980 If you plan to use kernel for capturing the crash dump change
2981 this value to start of the reserved region (the "X" value as
2982 specified in the "crashkernel=YM@XM" command line boot parameter
2983 passed to the panic-ed kernel).
2985 config MIPS_O32_FP64_SUPPORT
2986 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
2987 depends on 32BIT || MIPS32_O32
2989 When this is enabled, the kernel will support use of 64-bit floating
2990 point registers with binaries using the O32 ABI along with the
2991 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
2992 32-bit MIPS systems this support is at the cost of increasing the
2993 size and complexity of the compiled FPU emulator. Thus if you are
2994 running a MIPS32 system and know that none of your userland binaries
2995 will require 64-bit floating point, you may wish to reduce the size
2996 of your kernel & potentially improve FP emulation performance by
2999 Although binutils currently supports use of this flag the details
3000 concerning its effect upon the O32 ABI in userland are still being
3001 worked on. In order to avoid userland becoming dependent upon current
3002 behaviour before the details have been finalised, this option should
3003 be considered experimental and only enabled by those working upon
3011 select OF_EARLY_FLATTREE
3021 prompt "Kernel appended dtb support" if USE_OF
3022 default MIPS_NO_APPENDED_DTB
3024 config MIPS_NO_APPENDED_DTB
3027 Do not enable appended dtb support.
3029 config MIPS_ELF_APPENDED_DTB
3032 With this option, the boot code will look for a device tree binary
3033 DTB) included in the vmlinux ELF section .appended_dtb. By default
3034 it is empty and the DTB can be appended using binutils command
3037 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
3039 This is meant as a backward compatibility convenience for those
3040 systems with a bootloader that can't be upgraded to accommodate
3041 the documented boot protocol using a device tree.
3043 config MIPS_RAW_APPENDED_DTB
3044 bool "vmlinux.bin or vmlinuz.bin"
3046 With this option, the boot code will look for a device tree binary
3047 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
3048 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
3050 This is meant as a backward compatibility convenience for those
3051 systems with a bootloader that can't be upgraded to accommodate
3052 the documented boot protocol using a device tree.
3054 Beware that there is very little in terms of protection against
3055 this option being confused by leftover garbage in memory that might
3056 look like a DTB header after a reboot if no actual DTB is appended
3057 to vmlinux.bin. Do not leave this option active in a production kernel
3058 if you don't intend to always append a DTB.
3062 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
3063 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
3064 !MACH_LOONGSON64 && !MIPS_MALTA && \
3066 default MIPS_CMDLINE_FROM_BOOTLOADER
3068 config MIPS_CMDLINE_FROM_DTB
3070 bool "Dtb kernel arguments if available"
3072 config MIPS_CMDLINE_DTB_EXTEND
3074 bool "Extend dtb kernel arguments with bootloader arguments"
3076 config MIPS_CMDLINE_FROM_BOOTLOADER
3077 bool "Bootloader kernel arguments if available"
3079 config MIPS_CMDLINE_BUILTIN_EXTEND
3080 depends on CMDLINE_BOOL
3081 bool "Extend builtin kernel arguments with bootloader arguments"
3086 config LOCKDEP_SUPPORT
3090 config STACKTRACE_SUPPORT
3094 config PGTABLE_LEVELS
3096 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
3097 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
3100 config MIPS_AUTO_PFN_OFFSET
3103 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
3105 config PCI_DRIVERS_GENERIC
3106 select PCI_DOMAINS_GENERIC if PCI
3109 config PCI_DRIVERS_LEGACY
3110 def_bool !PCI_DRIVERS_GENERIC
3111 select NO_GENERIC_PCI_IOPORT_MAP
3112 select PCI_DOMAINS if PCI
3115 # ISA support is now enabled via select. Too many systems still have the one
3116 # or other ISA chip on the board that users don't know about so don't expect
3117 # users to choose the right thing ...
3123 bool "TURBOchannel support"
3124 depends on MACH_DECSTATION
3126 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
3127 processors. TURBOchannel programming specifications are available
3129 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
3131 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
3132 Linux driver support status is documented at:
3133 <http://www.linux-mips.org/wiki/DECstation>
3139 config ARCH_MMAP_RND_BITS_MIN
3143 config ARCH_MMAP_RND_BITS_MAX
3147 config ARCH_MMAP_RND_COMPAT_BITS_MIN
3150 config ARCH_MMAP_RND_COMPAT_BITS_MAX
3157 select MIPS_EXTERNAL_TIMER
3163 config MIPS32_COMPAT
3170 bool "Kernel support for o32 binaries"
3172 select ARCH_WANT_OLD_COMPAT_IPC
3174 select MIPS32_COMPAT
3176 Select this option if you want to run o32 binaries. These are pure
3177 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3178 existing binaries are in this format.
3183 bool "Kernel support for n32 binaries"
3185 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
3187 select MIPS32_COMPAT
3189 Select this option if you want to run n32 binaries. These are
3190 64-bit binaries using 32-bit quantities for addressing and certain
3191 data that would normally be 64-bit. They are used in special
3196 config CC_HAS_MNO_BRANCH_LIKELY
3198 depends on $(cc-option,-mno-branch-likely)
3200 # https://github.com/llvm/llvm-project/issues/61045
3201 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
3202 def_bool y if CC_IS_CLANG
3204 menu "Power management options"
3206 config ARCH_HIBERNATION_POSSIBLE
3208 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3210 config ARCH_SUSPEND_POSSIBLE
3212 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3214 source "kernel/power/Kconfig"
3218 config MIPS_EXTERNAL_TIMER
3221 menu "CPU Power Management"
3223 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3224 source "drivers/cpufreq/Kconfig"
3225 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3227 source "drivers/cpuidle/Kconfig"
3231 source "arch/mips/kvm/Kconfig"
3233 source "arch/mips/vdso/Kconfig"