1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ARCH_HAS_CPU_CACHE_ALIASING
8 select ARCH_HAS_CPU_FINALIZE_INIT
9 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
10 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
11 select ARCH_HAS_DMA_OPS if MACH_JAZZ
12 select ARCH_HAS_FORTIFY_SOURCE
14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
15 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
16 select ARCH_HAS_STRNCPY_FROM_USER
17 select ARCH_HAS_STRNLEN_USER
18 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_KEEP_MEMBLOCK
22 select ARCH_USE_BUILTIN_BSWAP
23 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
24 select ARCH_USE_MEMTEST
25 select ARCH_USE_QUEUED_RWLOCKS
26 select ARCH_USE_QUEUED_SPINLOCKS
27 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
28 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
29 select ARCH_WANT_IPC_PARSE_VERSION
30 select ARCH_WANT_LD_ORPHAN_WARN
31 select BUILDTIME_TABLE_SORT
32 select CLONE_BACKWARDS
33 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
34 select CPU_PM if CPU_IDLE || SUSPEND
35 select GENERIC_ATOMIC64 if !64BIT
36 select GENERIC_CMOS_UPDATE
37 select GENERIC_CPU_AUTOPROBE
38 select GENERIC_GETTIMEOFDAY
40 select GENERIC_IRQ_PROBE
41 select GENERIC_IRQ_SHOW
42 select GENERIC_ISA_DMA if EISA
43 select GENERIC_LIB_ASHLDI3
44 select GENERIC_LIB_ASHRDI3
45 select GENERIC_LIB_CMPDI2
46 select GENERIC_LIB_LSHRDI3
47 select GENERIC_LIB_UCMPDI2
48 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
49 select GENERIC_SMP_IDLE_THREAD
50 select GENERIC_IDLE_POLL_SETUP
51 select GENERIC_TIME_VSYSCALL
52 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
53 select HAS_IOPORT if !NO_IOPORT_MAP || ISA
54 select HAVE_ARCH_COMPILER_H
55 select HAVE_ARCH_JUMP_LABEL
56 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
57 select HAVE_ARCH_MMAP_RND_BITS if MMU
58 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
59 select HAVE_ARCH_SECCOMP_FILTER
60 select HAVE_ARCH_TRACEHOOK
61 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
62 select HAVE_ASM_MODVERSIONS
63 select HAVE_CONTEXT_TRACKING_USER
65 select HAVE_C_RECORDMCOUNT
66 select HAVE_DEBUG_KMEMLEAK
67 select HAVE_DEBUG_STACKOVERFLOW
68 select HAVE_DMA_CONTIGUOUS
69 select HAVE_DYNAMIC_FTRACE
70 select HAVE_EBPF_JIT if !CPU_MICROMIPS
71 select HAVE_EXIT_THREAD
73 select HAVE_FTRACE_MCOUNT_RECORD
74 select HAVE_FUNCTION_GRAPH_TRACER
75 select HAVE_FUNCTION_TRACER
76 select HAVE_GCC_PLUGINS
77 select HAVE_GENERIC_VDSO
78 select HAVE_IOREMAP_PROT
79 select HAVE_IRQ_EXIT_ON_IRQ_STACK
80 select HAVE_IRQ_TIME_ACCOUNTING
82 select HAVE_KRETPROBES
83 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
84 select HAVE_MOD_ARCH_SPECIFIC
86 select HAVE_PAGE_SIZE_4KB if !CPU_LOONGSON2EF && !CPU_LOONGSON64
87 select HAVE_PAGE_SIZE_16KB if !CPU_R3000
88 select HAVE_PAGE_SIZE_64KB if !CPU_R3000
89 select HAVE_PERF_EVENTS
91 select HAVE_PERF_USER_STACK_DUMP
92 select HAVE_REGS_AND_STACK_ACCESS_API
94 select HAVE_SPARSE_SYSCALL_NR
95 select HAVE_STACKPROTECTOR
96 select HAVE_SYSCALL_TRACEPOINTS
97 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
98 select IRQ_FORCED_THREADING
100 select LOCK_MM_AND_FIND_VMA
101 select MODULES_USE_ELF_REL if MODULES
102 select MODULES_USE_ELF_RELA if MODULES && 64BIT
103 select PERF_USE_VMALLOC
104 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
106 select SYSCTL_EXCEPTION_TRACE
107 select TRACE_IRQFLAGS_SUPPORT
108 select ARCH_HAS_ELFCORE_COMPAT
109 select HAVE_ARCH_KCSAN if 64BIT
111 config MIPS_FIXUP_BIGPHYS_ADDR
117 config MACH_GENERIC_CORE
122 select SYS_SUPPORTS_32BIT_KERNEL
123 select SYS_SUPPORTS_LITTLE_ENDIAN
124 select SYS_SUPPORTS_ZBOOT
125 select DMA_NONCOHERENT
130 select GENERIC_IRQ_CHIP
131 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
133 select CPU_SUPPORTS_CPUFREQ
134 select MIPS_EXTERNAL_TIMER
136 menu "Machine selection"
140 default MIPS_GENERIC_KERNEL
142 config MIPS_GENERIC_KERNEL
143 bool "Generic board-agnostic MIPS kernel"
148 select CLKSRC_MIPS_GIC
150 select CPU_MIPSR2_IRQ_EI
151 select CPU_MIPSR2_IRQ_VI
153 select DMA_NONCOHERENT
156 select MACH_GENERIC_CORE
157 select MIPS_AUTO_PFN_OFFSET
158 select MIPS_CPU_SCACHE
160 select MIPS_L1_CACHE_SHIFT_7
161 select NO_EXCEPT_FILL
162 select PCI_DRIVERS_GENERIC
165 select SYS_HAS_CPU_MIPS32_R1
166 select SYS_HAS_CPU_MIPS32_R2
167 select SYS_HAS_CPU_MIPS32_R5
168 select SYS_HAS_CPU_MIPS32_R6
169 select SYS_HAS_CPU_MIPS64_R1
170 select SYS_HAS_CPU_MIPS64_R2
171 select SYS_HAS_CPU_MIPS64_R5
172 select SYS_HAS_CPU_MIPS64_R6
173 select SYS_SUPPORTS_32BIT_KERNEL
174 select SYS_SUPPORTS_64BIT_KERNEL
175 select SYS_SUPPORTS_BIG_ENDIAN
176 select SYS_SUPPORTS_HIGHMEM
177 select SYS_SUPPORTS_LITTLE_ENDIAN
178 select SYS_SUPPORTS_MICROMIPS
179 select SYS_SUPPORTS_MIPS16
180 select SYS_SUPPORTS_MIPS_CPS
181 select SYS_SUPPORTS_MULTITHREADING
182 select SYS_SUPPORTS_RELOCATABLE
183 select SYS_SUPPORTS_SMARTMIPS
184 select SYS_SUPPORTS_ZBOOT
186 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
187 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
188 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
189 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
190 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
191 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
194 Select this to build a kernel which aims to support multiple boards,
195 generally using a flattened device tree passed from the bootloader
196 using the boot protocol defined in the UHI (Unified Hosting
197 Interface) specification.
200 bool "Alchemy processor based machines"
201 select PHYS_ADDR_T_64BIT
205 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
206 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
207 select SYS_HAS_CPU_MIPS32_R1
208 select SYS_SUPPORTS_32BIT_KERNEL
209 select SYS_SUPPORTS_APM_EMULATION
211 select SYS_SUPPORTS_ZBOOT
215 bool "Atheros AR231x/AR531x SoC support"
218 select DMA_NONCOHERENT
221 select SYS_HAS_CPU_MIPS32_R1
222 select SYS_SUPPORTS_BIG_ENDIAN
223 select SYS_SUPPORTS_32BIT_KERNEL
224 select SYS_HAS_EARLY_PRINTK
226 Support for Atheros AR231x and Atheros AR531x based boards
229 bool "Atheros AR71XX/AR724X/AR913X based boards"
230 select ARCH_HAS_RESET_CONTROLLER
234 select DMA_NONCOHERENT
239 select SYS_HAS_CPU_MIPS32_R2
240 select SYS_HAS_EARLY_PRINTK
241 select SYS_SUPPORTS_32BIT_KERNEL
242 select SYS_SUPPORTS_BIG_ENDIAN
243 select SYS_SUPPORTS_MIPS16
244 select SYS_SUPPORTS_ZBOOT_UART_PROM
246 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
248 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
251 bool "Broadcom Generic BMIPS kernel"
252 select ARCH_HAS_RESET_CONTROLLER
253 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
255 select NO_EXCEPT_FILL
261 select BCM6345_L1_IRQ
262 select BCM7038_L1_IRQ
263 select BCM7120_L2_IRQ
264 select BRCMSTB_L2_IRQ
266 select DMA_NONCOHERENT
267 select SYS_SUPPORTS_32BIT_KERNEL
268 select SYS_SUPPORTS_LITTLE_ENDIAN
269 select SYS_SUPPORTS_BIG_ENDIAN
270 select SYS_SUPPORTS_HIGHMEM
271 select SYS_HAS_CPU_BMIPS32_3300
272 select SYS_HAS_CPU_BMIPS4350
273 select SYS_HAS_CPU_BMIPS4380
274 select SYS_HAS_CPU_BMIPS5000
276 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
277 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
278 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
279 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
280 select HARDIRQS_SW_RESEND
282 select PCI_DRIVERS_GENERIC
285 Build a generic DT-based kernel image that boots on select
286 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
287 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
288 must be set appropriately for your board.
291 bool "Broadcom BCM47XX based boards"
295 select DMA_NONCOHERENT
298 select SYS_HAS_CPU_MIPS32_R1
299 select NO_EXCEPT_FILL
300 select SYS_SUPPORTS_32BIT_KERNEL
301 select SYS_SUPPORTS_LITTLE_ENDIAN
302 select SYS_SUPPORTS_MIPS16
303 select SYS_SUPPORTS_ZBOOT
304 select SYS_HAS_EARLY_PRINTK
305 select USE_GENERIC_EARLY_PRINTK_8250
307 select LEDS_GPIO_REGISTER
310 select BCM47XX_SSB if !BCM47XX_BCMA
312 Support for BCM47XX based boards
315 bool "Broadcom BCM63XX based boards"
320 select DMA_NONCOHERENT
322 select SYS_SUPPORTS_32BIT_KERNEL
323 select SYS_SUPPORTS_BIG_ENDIAN
324 select SYS_HAS_EARLY_PRINTK
325 select SYS_HAS_CPU_BMIPS32_3300
326 select SYS_HAS_CPU_BMIPS4350
327 select SYS_HAS_CPU_BMIPS4380
330 select MIPS_L1_CACHE_SHIFT_4
331 select HAVE_LEGACY_CLK
333 Support for BCM63XX based boards
340 select DMA_NONCOHERENT
346 select PCI_GT64XXX_PCI0
347 select SYS_HAS_CPU_NEVADA
348 select SYS_HAS_EARLY_PRINTK
349 select SYS_SUPPORTS_32BIT_KERNEL
350 select SYS_SUPPORTS_64BIT_KERNEL
351 select SYS_SUPPORTS_LITTLE_ENDIAN
352 select USE_GENERIC_EARLY_PRINTK_8250
354 config MACH_DECSTATION
358 select CEVT_R4K if CPU_R4X00
360 select CSRC_R4K if CPU_R4X00
361 select CPU_DADDI_WORKAROUNDS if 64BIT
362 select CPU_R4000_WORKAROUNDS if 64BIT
363 select CPU_R4400_WORKAROUNDS if 64BIT
364 select DMA_NONCOHERENT
367 select SYS_HAS_CPU_R3000
368 select SYS_HAS_CPU_R4X00
369 select SYS_SUPPORTS_32BIT_KERNEL
370 select SYS_SUPPORTS_64BIT_KERNEL
371 select SYS_SUPPORTS_LITTLE_ENDIAN
372 select SYS_SUPPORTS_128HZ
373 select SYS_SUPPORTS_256HZ
374 select SYS_SUPPORTS_1024HZ
375 select MIPS_L1_CACHE_SHIFT_4
377 This enables support for DEC's MIPS based workstations. For details
378 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
379 DECstation porting pages on <http://decstation.unix-ag.org/>.
381 If you have one of the following DECstation Models you definitely
382 want to choose R4xx0 for the CPU Type:
389 otherwise choose R3000.
392 bool "Jazz family of machines"
395 select ARCH_MIGHT_HAVE_PC_PARPORT
396 select ARCH_MIGHT_HAVE_PC_SERIO
399 select ARCH_MAY_HAVE_PC_FDC
402 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
403 select GENERIC_ISA_DMA
404 select HAVE_PCSPKR_PLATFORM
409 select SYS_HAS_CPU_R4X00
410 select SYS_SUPPORTS_32BIT_KERNEL
411 select SYS_SUPPORTS_64BIT_KERNEL
412 select SYS_SUPPORTS_100HZ
413 select SYS_SUPPORTS_LITTLE_ENDIAN
415 This a family of machines based on the MIPS R4030 chipset which was
416 used by several vendors to build RISC/os and Windows NT workstations.
417 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
418 Olivetti M700-10 workstations.
420 config MACH_INGENIC_SOC
421 bool "Ingenic SoC based machines"
424 select MACH_GENERIC_CORE
425 select SYS_SUPPORTS_ZBOOT_UART16550
426 select CPU_SUPPORTS_CPUFREQ
427 select MIPS_EXTERNAL_TIMER
430 bool "Lantiq based platforms"
431 select DMA_NONCOHERENT
435 select NO_EXCEPT_FILL
436 select SYS_HAS_CPU_MIPS32_R1
437 select SYS_HAS_CPU_MIPS32_R2
438 select SYS_SUPPORTS_BIG_ENDIAN
439 select SYS_SUPPORTS_32BIT_KERNEL
440 select SYS_SUPPORTS_MIPS16
441 select SYS_SUPPORTS_MULTITHREADING
442 select SYS_SUPPORTS_VPE_LOADER
443 select SYS_HAS_EARLY_PRINTK
447 select HAVE_LEGACY_CLK
450 select PINCTRL_LANTIQ
451 select ARCH_HAS_RESET_CONTROLLER
452 select RESET_CONTROLLER
454 config MACH_LOONGSON32
455 bool "Loongson 32-bit family of machines"
456 select SYS_SUPPORTS_ZBOOT
458 This enables support for the Loongson-1 family of machines.
460 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
461 the Institute of Computing Technology (ICT), Chinese Academy of
464 config MACH_LOONGSON2EF
465 bool "Loongson-2E/F family of machines"
466 select SYS_SUPPORTS_ZBOOT
468 This enables the support of early Loongson-2E/F family of machines.
470 config MACH_LOONGSON64
471 bool "Loongson 64-bit family of machines"
472 select ARCH_DMA_DEFAULT_COHERENT
473 select ARCH_SPARSEMEM_ENABLE
474 select ARCH_MIGHT_HAVE_PC_PARPORT
475 select ARCH_MIGHT_HAVE_PC_SERIO
476 select GENERIC_ISA_DMA_SUPPORT_BROKEN
486 select NO_EXCEPT_FILL
487 select NR_CPUS_DEFAULT_64
488 select USE_GENERIC_EARLY_PRINTK_8250
489 select PCI_DRIVERS_GENERIC
490 select SYS_HAS_CPU_LOONGSON64
491 select SYS_HAS_EARLY_PRINTK
492 select SYS_SUPPORTS_SMP
493 select SYS_SUPPORTS_HOTPLUG_CPU
494 select SYS_SUPPORTS_NUMA
495 select SYS_SUPPORTS_64BIT_KERNEL
496 select SYS_SUPPORTS_HIGHMEM
497 select SYS_SUPPORTS_LITTLE_ENDIAN
498 select SYS_SUPPORTS_ZBOOT
499 select SYS_SUPPORTS_RELOCATABLE
504 select PCI_HOST_GENERIC
505 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
507 This enables the support of Loongson-2/3 family of machines.
509 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
510 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
511 and Loongson-2F which will be removed), developed by the Institute
512 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
515 bool "MIPS Malta board"
516 select ARCH_MAY_HAVE_PC_FDC
517 select ARCH_MIGHT_HAVE_PC_PARPORT
518 select ARCH_MIGHT_HAVE_PC_SERIO
523 select CLKSRC_MIPS_GIC
526 select DMA_NONCOHERENT
527 select GENERIC_ISA_DMA
528 select HAVE_PCSPKR_PLATFORM
534 select MIPS_CPU_SCACHE
536 select MIPS_L1_CACHE_SHIFT_6
538 select PCI_GT64XXX_PCI0
541 select SYS_HAS_CPU_MIPS32_R1
542 select SYS_HAS_CPU_MIPS32_R2
543 select SYS_HAS_CPU_MIPS32_R3_5
544 select SYS_HAS_CPU_MIPS32_R5
545 select SYS_HAS_CPU_MIPS32_R6
546 select SYS_HAS_CPU_MIPS64_R1
547 select SYS_HAS_CPU_MIPS64_R2
548 select SYS_HAS_CPU_MIPS64_R6
549 select SYS_HAS_CPU_NEVADA
550 select SYS_HAS_CPU_RM7000
551 select SYS_SUPPORTS_32BIT_KERNEL
552 select SYS_SUPPORTS_64BIT_KERNEL
553 select SYS_SUPPORTS_BIG_ENDIAN
554 select SYS_SUPPORTS_HIGHMEM
555 select SYS_SUPPORTS_LITTLE_ENDIAN
556 select SYS_SUPPORTS_MICROMIPS
557 select SYS_SUPPORTS_MIPS16
558 select SYS_SUPPORTS_MIPS_CPS
559 select SYS_SUPPORTS_MULTITHREADING
560 select SYS_SUPPORTS_RELOCATABLE
561 select SYS_SUPPORTS_SMARTMIPS
562 select SYS_SUPPORTS_VPE_LOADER
563 select SYS_SUPPORTS_ZBOOT
565 select WAR_ICACHE_REFILLS
566 select ZONE_DMA32 if 64BIT
568 This enables support for the MIPS Technologies Malta evaluation
572 bool "Microchip PIC32 Family"
574 This enables support for the Microchip PIC32 family of platforms.
576 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
580 bool "Mobileye EyeQ SoC"
581 select MACH_GENERIC_CORE
583 select PHYSICAL_START_BOOL
584 select ARCH_SPARSEMEM_DEFAULT if 64BIT
588 select CLKSRC_MIPS_GIC
590 select CPU_MIPSR2_IRQ_EI
591 select CPU_MIPSR2_IRQ_VI
593 select DMA_NONCOHERENT
596 select MIPS_AUTO_PFN_OFFSET
597 select MIPS_CPU_SCACHE
599 select MIPS_L1_CACHE_SHIFT_7
600 select PCI_DRIVERS_GENERIC
603 select SYS_HAS_CPU_MIPS64_R6
604 select SYS_SUPPORTS_64BIT_KERNEL
605 select SYS_SUPPORTS_HIGHMEM
606 select SYS_SUPPORTS_LITTLE_ENDIAN
607 select SYS_SUPPORTS_MIPS_CPS
608 select SYS_SUPPORTS_RELOCATABLE
609 select SYS_SUPPORTS_ZBOOT
611 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
612 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
613 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
614 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
615 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
616 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
619 Select this to build a kernel supporting EyeQ SoC from Mobileye.
623 config MACH_NINTENDO64
624 bool "Nintendo 64 console"
627 select SYS_HAS_CPU_R4300
628 select SYS_SUPPORTS_BIG_ENDIAN
629 select SYS_SUPPORTS_ZBOOT
630 select SYS_SUPPORTS_32BIT_KERNEL
631 select SYS_SUPPORTS_64BIT_KERNEL
632 select DMA_NONCOHERENT
636 bool "Ralink based machines"
641 select DMA_NONCOHERENT
644 select SYS_HAS_CPU_MIPS32_R2
645 select SYS_SUPPORTS_32BIT_KERNEL
646 select SYS_SUPPORTS_LITTLE_ENDIAN
647 select SYS_SUPPORTS_MIPS16
648 select SYS_SUPPORTS_ZBOOT
649 select SYS_HAS_EARLY_PRINTK
650 select ARCH_HAS_RESET_CONTROLLER
651 select RESET_CONTROLLER
653 config MACH_REALTEK_RTL
654 bool "Realtek RTL838x/RTL839x based machines"
656 select MACH_GENERIC_CORE
657 select DMA_NONCOHERENT
661 select SYS_HAS_CPU_MIPS32_R1
662 select SYS_HAS_CPU_MIPS32_R2
663 select SYS_SUPPORTS_BIG_ENDIAN
664 select SYS_SUPPORTS_32BIT_KERNEL
665 select SYS_SUPPORTS_MIPS16
666 select SYS_SUPPORTS_MULTITHREADING
667 select SYS_SUPPORTS_VPE_LOADER
671 select REALTEK_OTTO_TIMER
674 bool "SGI IP22 (Indy/Indigo2)"
679 select ARCH_MIGHT_HAVE_PC_SERIO
683 select DEFAULT_SGI_PARTITION
684 select DMA_NONCOHERENT
688 select IP22_CPU_SCACHE
690 select GENERIC_ISA_DMA_SUPPORT_BROKEN
692 select SGI_HAS_INDYDOG
698 select SYS_HAS_CPU_R4X00
699 select SYS_HAS_CPU_R5000
700 select SYS_HAS_EARLY_PRINTK
701 select SYS_SUPPORTS_32BIT_KERNEL
702 select SYS_SUPPORTS_64BIT_KERNEL
703 select SYS_SUPPORTS_BIG_ENDIAN
704 select WAR_R4600_V1_INDEX_ICACHEOP
705 select WAR_R4600_V1_HIT_CACHEOP
706 select WAR_R4600_V2_HIT_CACHEOP
707 select MIPS_L1_CACHE_SHIFT_7
709 This are the SGI Indy, Challenge S and Indigo2, as well as certain
710 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
711 that runs on these, say Y here.
714 bool "SGI IP27 (Origin200/2000)"
715 select ARCH_HAS_PHYS_TO_DMA
716 select ARCH_SPARSEMEM_ENABLE
719 select ARC_CMDLINE_ONLY
721 select DEFAULT_SGI_PARTITION
723 select SYS_HAS_EARLY_PRINTK
726 select IRQ_DOMAIN_HIERARCHY
727 select NR_CPUS_DEFAULT_64
728 select PCI_DRIVERS_GENERIC
729 select PCI_XTALK_BRIDGE
730 select SYS_HAS_CPU_R10000
731 select SYS_SUPPORTS_64BIT_KERNEL
732 select SYS_SUPPORTS_BIG_ENDIAN
733 select SYS_SUPPORTS_NUMA
734 select SYS_SUPPORTS_SMP
735 select WAR_R10000_LLSC
736 select MIPS_L1_CACHE_SHIFT_7
738 select HAVE_ARCH_NODEDATA_EXTENSION
740 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
741 workstations. To compile a Linux kernel that runs on these, say Y
745 bool "SGI IP28 (Indigo2 R10k)"
750 select ARCH_MIGHT_HAVE_PC_SERIO
754 select DEFAULT_SGI_PARTITION
755 select DMA_NONCOHERENT
756 select GENERIC_ISA_DMA_SUPPORT_BROKEN
762 select SGI_HAS_INDYDOG
768 select SYS_HAS_CPU_R10000
769 select SYS_HAS_EARLY_PRINTK
770 select SYS_SUPPORTS_64BIT_KERNEL
771 select SYS_SUPPORTS_BIG_ENDIAN
772 select WAR_R10000_LLSC
773 select MIPS_L1_CACHE_SHIFT_7
775 This is the SGI Indigo2 with R10000 processor. To compile a Linux
776 kernel that runs on these, say Y here.
779 bool "SGI IP30 (Octane/Octane2)"
780 select ARCH_HAS_PHYS_TO_DMA
787 select SYNC_R4K if SMP
791 select IRQ_DOMAIN_HIERARCHY
792 select PCI_DRIVERS_GENERIC
793 select PCI_XTALK_BRIDGE
794 select SYS_HAS_EARLY_PRINTK
795 select SYS_HAS_CPU_R10000
796 select SYS_SUPPORTS_64BIT_KERNEL
797 select SYS_SUPPORTS_BIG_ENDIAN
798 select SYS_SUPPORTS_SMP
799 select WAR_R10000_LLSC
800 select MIPS_L1_CACHE_SHIFT_7
803 These are the SGI Octane and Octane2 graphics workstations. To
804 compile a Linux kernel that runs on these, say Y here.
810 select ARCH_HAS_PHYS_TO_DMA
816 select DMA_NONCOHERENT
819 select R5000_CPU_SCACHE
820 select RM7000_CPU_SCACHE
821 select SYS_HAS_CPU_R5000
822 select SYS_HAS_CPU_R10000 if BROKEN
823 select SYS_HAS_CPU_RM7000
824 select SYS_HAS_CPU_NEVADA
825 select SYS_SUPPORTS_64BIT_KERNEL
826 select SYS_SUPPORTS_BIG_ENDIAN
827 select WAR_ICACHE_REFILLS
829 If you want this kernel to run on SGI O2 workstation, say Y here.
832 bool "Sibyte BCM91125C-CRhone"
834 select SIBYTE_BCM1125
836 select SYS_HAS_CPU_SB1
837 select SYS_SUPPORTS_BIG_ENDIAN
838 select SYS_SUPPORTS_HIGHMEM
839 select SYS_SUPPORTS_LITTLE_ENDIAN
842 bool "Sibyte BCM91125E-Rhone"
846 select SYS_HAS_CPU_SB1
847 select SYS_SUPPORTS_BIG_ENDIAN
848 select SYS_SUPPORTS_LITTLE_ENDIAN
851 bool "Sibyte BCM91250A-SWARM"
853 select HAVE_PATA_PLATFORM
856 select SYS_HAS_CPU_SB1
857 select SYS_SUPPORTS_BIG_ENDIAN
858 select SYS_SUPPORTS_HIGHMEM
859 select SYS_SUPPORTS_LITTLE_ENDIAN
860 select ZONE_DMA32 if 64BIT
861 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
863 config SIBYTE_LITTLESUR
864 bool "Sibyte BCM91250C2-LittleSur"
866 select HAVE_PATA_PLATFORM
869 select SYS_HAS_CPU_SB1
870 select SYS_SUPPORTS_BIG_ENDIAN
871 select SYS_SUPPORTS_HIGHMEM
872 select SYS_SUPPORTS_LITTLE_ENDIAN
873 select ZONE_DMA32 if 64BIT
875 config SIBYTE_SENTOSA
876 bool "Sibyte BCM91250E-Sentosa"
880 select SYS_HAS_CPU_SB1
881 select SYS_SUPPORTS_BIG_ENDIAN
882 select SYS_SUPPORTS_LITTLE_ENDIAN
883 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
886 bool "Sibyte BCM91480B-BigSur"
888 select NR_CPUS_DEFAULT_4
889 select SIBYTE_BCM1x80
891 select SYS_HAS_CPU_SB1
892 select SYS_SUPPORTS_BIG_ENDIAN
893 select SYS_SUPPORTS_HIGHMEM
894 select SYS_SUPPORTS_LITTLE_ENDIAN
895 select ZONE_DMA32 if 64BIT
896 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
899 bool "SNI RM200/300/400"
902 select FW_ARC if CPU_LITTLE_ENDIAN
903 select FW_ARC32 if CPU_LITTLE_ENDIAN
904 select FW_SNIPROM if CPU_BIG_ENDIAN
905 select ARCH_MAY_HAVE_PC_FDC
906 select ARCH_MIGHT_HAVE_PC_PARPORT
907 select ARCH_MIGHT_HAVE_PC_SERIO
911 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
912 select DMA_NONCOHERENT
913 select GENERIC_ISA_DMA
915 select HAVE_PCSPKR_PLATFORM
921 select MIPS_L1_CACHE_SHIFT_6
922 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
923 select SYS_HAS_CPU_R4X00
924 select SYS_HAS_CPU_R5000
925 select SYS_HAS_CPU_R10000
926 select R5000_CPU_SCACHE
927 select SYS_HAS_EARLY_PRINTK
928 select SYS_SUPPORTS_32BIT_KERNEL
929 select SYS_SUPPORTS_64BIT_KERNEL
930 select SYS_SUPPORTS_BIG_ENDIAN
931 select SYS_SUPPORTS_HIGHMEM
932 select SYS_SUPPORTS_LITTLE_ENDIAN
933 select WAR_R4600_V2_HIT_CACHEOP
935 The SNI RM200/300/400 are MIPS-based machines manufactured by
936 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
937 Technology and now in turn merged with Fujitsu. Say Y here to
938 support this machine type.
941 bool "Toshiba TX49 series based machines"
942 select WAR_TX49XX_ICACHE_INDEX_INV
944 config MIKROTIK_RB532
945 bool "Mikrotik RB532 boards"
948 select DMA_NONCOHERENT
951 select SYS_HAS_CPU_MIPS32_R1
952 select SYS_SUPPORTS_32BIT_KERNEL
953 select SYS_SUPPORTS_LITTLE_ENDIAN
957 select MIPS_L1_CACHE_SHIFT_4
959 Support the Mikrotik(tm) RouterBoard 532 series,
960 based on the IDT RC32434 SoC.
962 config CAVIUM_OCTEON_SOC
963 bool "Cavium Networks Octeon SoC based boards"
965 select ARCH_HAS_PHYS_TO_DMA
967 select PHYS_ADDR_T_64BIT
968 select SYS_SUPPORTS_64BIT_KERNEL
969 select SYS_SUPPORTS_BIG_ENDIAN
971 select EDAC_ATOMIC_SCRUB
972 select SYS_SUPPORTS_LITTLE_ENDIAN
973 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
974 select SYS_HAS_EARLY_PRINTK
975 select SYS_HAS_CPU_CAVIUM_OCTEON
977 select HAVE_PLAT_DELAY
978 select HAVE_PLAT_FW_INIT_CMDLINE
979 select HAVE_PLAT_MEMCPY
983 select ARCH_SPARSEMEM_ENABLE
984 select SYS_SUPPORTS_SMP
985 select NR_CPUS_DEFAULT_64
986 select MIPS_NR_CPU_NR_MAP_1024
989 select MTD_COMPLEX_MAPPINGS
991 select SYS_SUPPORTS_RELOCATABLE
993 This option supports all of the Octeon reference boards from Cavium
994 Networks. It builds a kernel that dynamically determines the Octeon
995 CPU type and supports all known board reference implementations.
996 Some of the supported boards are:
1003 Say Y here for most Octeon reference boards.
1007 config FIT_IMAGE_FDT_EPM5
1008 bool "Include FDT for Mobileye EyeQ5 development platforms"
1009 depends on MACH_EYEQ5
1012 Enable this to include the FDT for the EyeQ5 development platforms
1013 from Mobileye in the FIT kernel image.
1014 This requires u-boot on the platform.
1016 source "arch/mips/alchemy/Kconfig"
1017 source "arch/mips/ath25/Kconfig"
1018 source "arch/mips/ath79/Kconfig"
1019 source "arch/mips/bcm47xx/Kconfig"
1020 source "arch/mips/bcm63xx/Kconfig"
1021 source "arch/mips/bmips/Kconfig"
1022 source "arch/mips/generic/Kconfig"
1023 source "arch/mips/ingenic/Kconfig"
1024 source "arch/mips/jazz/Kconfig"
1025 source "arch/mips/lantiq/Kconfig"
1026 source "arch/mips/mobileye/Kconfig"
1027 source "arch/mips/pic32/Kconfig"
1028 source "arch/mips/ralink/Kconfig"
1029 source "arch/mips/sgi-ip27/Kconfig"
1030 source "arch/mips/sibyte/Kconfig"
1031 source "arch/mips/txx9/Kconfig"
1032 source "arch/mips/cavium-octeon/Kconfig"
1033 source "arch/mips/loongson2ef/Kconfig"
1034 source "arch/mips/loongson32/Kconfig"
1035 source "arch/mips/loongson64/Kconfig"
1039 config GENERIC_HWEIGHT
1043 config GENERIC_CALIBRATE_DELAY
1047 config SCHED_OMIT_FRAME_POINTER
1052 # Select some configuration options automatically based on user selections.
1057 config ARCH_MAY_HAVE_PC_FDC
1088 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
1089 select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT
1095 config MIPS_CLOCK_VSYSCALL
1096 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
1105 config ARCH_SUPPORTS_UPROBES
1108 config DMA_NONCOHERENT
1111 # MIPS allows mixing "slightly different" Cacheability and Coherency
1112 # Attribute bits. It is believed that the uncached access through
1113 # KSEG1 and the implementation specific "uncached accelerated" used
1114 # by pgprot_writcombine can be mixed, and the latter sometimes provides
1115 # significant advantages.
1117 select ARCH_HAS_SETUP_DMA_OPS
1118 select ARCH_HAS_DMA_WRITE_COMBINE
1119 select ARCH_HAS_DMA_PREP_COHERENT
1120 select ARCH_HAS_SYNC_DMA_FOR_CPU
1121 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
1122 select ARCH_HAS_DMA_SET_UNCACHED
1123 select DMA_NONCOHERENT_MMAP
1124 select NEED_DMA_MAP_STATE
1126 config SYS_HAS_EARLY_PRINTK
1129 config SYS_SUPPORTS_HOTPLUG_CPU
1132 config MIPS_BONITO64
1141 config NO_IOPORT_MAP
1145 def_bool CPU_NO_LOAD_STORE_LR
1147 config GENERIC_ISA_DMA
1149 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
1152 config GENERIC_ISA_DMA_SUPPORT_BROKEN
1154 select GENERIC_ISA_DMA
1156 config HAVE_PLAT_DELAY
1159 config HAVE_PLAT_FW_INIT_CMDLINE
1162 config HAVE_PLAT_MEMCPY
1168 config SYS_SUPPORTS_RELOCATABLE
1171 Selected if the platform supports relocating the kernel.
1172 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
1173 to allow access to command line and entropy sources.
1176 # Endianness selection. Sufficiently obscure so many users don't know what to
1177 # answer,so we try hard to limit the available choices. Also the use of a
1178 # choice statement should be more obvious to the user.
1181 prompt "Endianness selection"
1183 Some MIPS machines can be configured for either little or big endian
1184 byte order. These modes require different kernels and a different
1185 Linux distribution. In general there is one preferred byteorder for a
1186 particular system but some systems are just as commonly used in the
1187 one or the other endianness.
1189 config CPU_BIG_ENDIAN
1191 depends on SYS_SUPPORTS_BIG_ENDIAN
1193 config CPU_LITTLE_ENDIAN
1194 bool "Little endian"
1195 depends on SYS_SUPPORTS_LITTLE_ENDIAN
1202 config SYS_SUPPORTS_APM_EMULATION
1205 config SYS_SUPPORTS_BIG_ENDIAN
1208 config SYS_SUPPORTS_LITTLE_ENDIAN
1211 config MIPS_HUGE_TLB_SUPPORT
1212 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
1220 config PCI_GT64XXX_PCI0
1223 config PCI_XTALK_BRIDGE
1226 config NO_EXCEPT_FILL
1232 config SWAP_IO_SPACE
1235 config SGI_HAS_INDYDOG
1247 config SGI_HAS_ZILOG
1250 config SGI_HAS_I8042
1253 config DEFAULT_SGI_PARTITION
1265 config MIPS_L1_CACHE_SHIFT_4
1268 config MIPS_L1_CACHE_SHIFT_5
1271 config MIPS_L1_CACHE_SHIFT_6
1274 config MIPS_L1_CACHE_SHIFT_7
1277 config MIPS_L1_CACHE_SHIFT
1279 default "7" if MIPS_L1_CACHE_SHIFT_7
1280 default "6" if MIPS_L1_CACHE_SHIFT_6
1281 default "5" if MIPS_L1_CACHE_SHIFT_5
1282 default "4" if MIPS_L1_CACHE_SHIFT_4
1285 config ARC_CMDLINE_ONLY
1289 bool "ARC console support"
1290 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
1304 menu "CPU selection"
1310 config CPU_LOONGSON64
1311 bool "Loongson 64-bit CPU"
1312 depends on SYS_HAS_CPU_LOONGSON64
1313 select ARCH_HAS_PHYS_TO_DMA
1315 select CPU_HAS_PREFETCH
1316 select CPU_SUPPORTS_64BIT_KERNEL
1317 select CPU_SUPPORTS_HIGHMEM
1318 select CPU_SUPPORTS_HUGEPAGES
1319 select CPU_SUPPORTS_MSA
1320 select CPU_SUPPORTS_VZ
1321 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
1322 select CPU_MIPSR2_IRQ_VI
1323 select DMA_NONCOHERENT
1324 select WEAK_ORDERING
1325 select WEAK_REORDERING_BEYOND_LLSC
1326 select MIPS_ASID_BITS_VARIABLE
1327 select MIPS_PGD_C0_CONTEXT
1328 select MIPS_L1_CACHE_SHIFT_6
1329 select MIPS_FP_SUPPORT
1333 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1334 cores implements the MIPS64R2 instruction set with many extensions,
1335 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1336 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
1337 Loongson-2E/2F is not covered here and will be removed in future.
1339 config CPU_LOONGSON2E
1341 depends on SYS_HAS_CPU_LOONGSON2E
1342 select CPU_LOONGSON2EF
1344 The Loongson 2E processor implements the MIPS III instruction set
1345 with many extensions.
1347 It has an internal FPGA northbridge, which is compatible to
1350 config CPU_LOONGSON2F
1352 depends on SYS_HAS_CPU_LOONGSON2F
1353 select CPU_LOONGSON2EF
1355 The Loongson 2F processor implements the MIPS III instruction set
1356 with many extensions.
1358 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1359 have a similar programming interface with FPGA northbridge used in
1362 config CPU_LOONGSON1B
1364 depends on SYS_HAS_CPU_LOONGSON1B
1365 select CPU_LOONGSON32
1366 select LEDS_GPIO_REGISTER
1368 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1369 Release 1 instruction set and part of the MIPS32 Release 2
1372 config CPU_LOONGSON1C
1374 depends on SYS_HAS_CPU_LOONGSON1C
1375 select CPU_LOONGSON32
1376 select LEDS_GPIO_REGISTER
1378 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
1379 Release 1 instruction set and part of the MIPS32 Release 2
1382 config CPU_MIPS32_R1
1383 bool "MIPS32 Release 1"
1384 depends on SYS_HAS_CPU_MIPS32_R1
1385 select CPU_HAS_PREFETCH
1386 select CPU_SUPPORTS_32BIT_KERNEL
1387 select CPU_SUPPORTS_HIGHMEM
1389 Choose this option to build a kernel for release 1 or later of the
1390 MIPS32 architecture. Most modern embedded systems with a 32-bit
1391 MIPS processor are based on a MIPS32 processor. If you know the
1392 specific type of processor in your system, choose those that one
1393 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1394 Release 2 of the MIPS32 architecture is available since several
1395 years so chances are you even have a MIPS32 Release 2 processor
1396 in which case you should choose CPU_MIPS32_R2 instead for better
1399 config CPU_MIPS32_R2
1400 bool "MIPS32 Release 2"
1401 depends on SYS_HAS_CPU_MIPS32_R2
1402 select CPU_HAS_PREFETCH
1403 select CPU_SUPPORTS_32BIT_KERNEL
1404 select CPU_SUPPORTS_HIGHMEM
1405 select CPU_SUPPORTS_MSA
1407 Choose this option to build a kernel for release 2 or later of the
1408 MIPS32 architecture. Most modern embedded systems with a 32-bit
1409 MIPS processor are based on a MIPS32 processor. If you know the
1410 specific type of processor in your system, choose those that one
1411 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1413 config CPU_MIPS32_R5
1414 bool "MIPS32 Release 5"
1415 depends on SYS_HAS_CPU_MIPS32_R5
1416 select CPU_HAS_PREFETCH
1417 select CPU_SUPPORTS_32BIT_KERNEL
1418 select CPU_SUPPORTS_HIGHMEM
1419 select CPU_SUPPORTS_MSA
1420 select CPU_SUPPORTS_VZ
1421 select MIPS_O32_FP64_SUPPORT
1423 Choose this option to build a kernel for release 5 or later of the
1424 MIPS32 architecture. New MIPS processors, starting with the Warrior
1425 family, are based on a MIPS32r5 processor. If you own an older
1426 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1428 config CPU_MIPS32_R6
1429 bool "MIPS32 Release 6"
1430 depends on SYS_HAS_CPU_MIPS32_R6
1431 select CPU_HAS_PREFETCH
1432 select CPU_NO_LOAD_STORE_LR
1433 select CPU_SUPPORTS_32BIT_KERNEL
1434 select CPU_SUPPORTS_HIGHMEM
1435 select CPU_SUPPORTS_MSA
1436 select CPU_SUPPORTS_VZ
1437 select MIPS_O32_FP64_SUPPORT
1439 Choose this option to build a kernel for release 6 or later of the
1440 MIPS32 architecture. New MIPS processors, starting with the Warrior
1441 family, are based on a MIPS32r6 processor. If you own an older
1442 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1444 config CPU_MIPS64_R1
1445 bool "MIPS64 Release 1"
1446 depends on SYS_HAS_CPU_MIPS64_R1
1447 select CPU_HAS_PREFETCH
1448 select CPU_SUPPORTS_32BIT_KERNEL
1449 select CPU_SUPPORTS_64BIT_KERNEL
1450 select CPU_SUPPORTS_HIGHMEM
1451 select CPU_SUPPORTS_HUGEPAGES
1453 Choose this option to build a kernel for release 1 or later of the
1454 MIPS64 architecture. Many modern embedded systems with a 64-bit
1455 MIPS processor are based on a MIPS64 processor. If you know the
1456 specific type of processor in your system, choose those that one
1457 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1458 Release 2 of the MIPS64 architecture is available since several
1459 years so chances are you even have a MIPS64 Release 2 processor
1460 in which case you should choose CPU_MIPS64_R2 instead for better
1463 config CPU_MIPS64_R2
1464 bool "MIPS64 Release 2"
1465 depends on SYS_HAS_CPU_MIPS64_R2
1466 select CPU_HAS_PREFETCH
1467 select CPU_SUPPORTS_32BIT_KERNEL
1468 select CPU_SUPPORTS_64BIT_KERNEL
1469 select CPU_SUPPORTS_HIGHMEM
1470 select CPU_SUPPORTS_HUGEPAGES
1471 select CPU_SUPPORTS_MSA
1473 Choose this option to build a kernel for release 2 or later of the
1474 MIPS64 architecture. Many modern embedded systems with a 64-bit
1475 MIPS processor are based on a MIPS64 processor. If you know the
1476 specific type of processor in your system, choose those that one
1477 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1479 config CPU_MIPS64_R5
1480 bool "MIPS64 Release 5"
1481 depends on SYS_HAS_CPU_MIPS64_R5
1482 select CPU_HAS_PREFETCH
1483 select CPU_SUPPORTS_32BIT_KERNEL
1484 select CPU_SUPPORTS_64BIT_KERNEL
1485 select CPU_SUPPORTS_HIGHMEM
1486 select CPU_SUPPORTS_HUGEPAGES
1487 select CPU_SUPPORTS_MSA
1488 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
1489 select CPU_SUPPORTS_VZ
1491 Choose this option to build a kernel for release 5 or later of the
1492 MIPS64 architecture. This is a intermediate MIPS architecture
1493 release partly implementing release 6 features. Though there is no
1494 any hardware known to be based on this release.
1496 config CPU_MIPS64_R6
1497 bool "MIPS64 Release 6"
1498 depends on SYS_HAS_CPU_MIPS64_R6
1499 select CPU_HAS_PREFETCH
1500 select CPU_NO_LOAD_STORE_LR
1501 select CPU_SUPPORTS_32BIT_KERNEL
1502 select CPU_SUPPORTS_64BIT_KERNEL
1503 select CPU_SUPPORTS_HIGHMEM
1504 select CPU_SUPPORTS_HUGEPAGES
1505 select CPU_SUPPORTS_MSA
1506 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
1507 select CPU_SUPPORTS_VZ
1509 Choose this option to build a kernel for release 6 or later of the
1510 MIPS64 architecture. New MIPS processors, starting with the Warrior
1511 family, are based on a MIPS64r6 processor. If you own an older
1512 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
1515 bool "MIPS Warrior P5600"
1516 depends on SYS_HAS_CPU_P5600
1517 select CPU_HAS_PREFETCH
1518 select CPU_SUPPORTS_32BIT_KERNEL
1519 select CPU_SUPPORTS_HIGHMEM
1520 select CPU_SUPPORTS_MSA
1521 select CPU_SUPPORTS_CPUFREQ
1522 select CPU_SUPPORTS_VZ
1523 select CPU_MIPSR2_IRQ_VI
1524 select CPU_MIPSR2_IRQ_EI
1525 select MIPS_O32_FP64_SUPPORT
1527 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
1528 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
1529 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
1530 level features like up to six P5600 calculation cores, CM2 with L2
1531 cache, IOCU/IOMMU (though might be unused depending on the system-
1532 specific IP core configuration), GIC, CPC, virtualisation module,
1537 depends on SYS_HAS_CPU_R3000
1540 select CPU_SUPPORTS_32BIT_KERNEL
1541 select CPU_SUPPORTS_HIGHMEM
1543 Please make sure to pick the right CPU type. Linux/MIPS is not
1544 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
1545 *not* work on R4000 machines and vice versa. However, since most
1546 of the supported machines have an R4000 (or similar) CPU, R4x00
1547 might be a safe bet. If the resulting kernel does not work,
1548 try to recompile with R3000.
1552 depends on SYS_HAS_CPU_R4300
1553 select CPU_SUPPORTS_32BIT_KERNEL
1554 select CPU_SUPPORTS_64BIT_KERNEL
1556 MIPS Technologies R4300-series processors.
1560 depends on SYS_HAS_CPU_R4X00
1561 select CPU_SUPPORTS_32BIT_KERNEL
1562 select CPU_SUPPORTS_64BIT_KERNEL
1563 select CPU_SUPPORTS_HUGEPAGES
1565 MIPS Technologies R4000-series processors other than 4300, including
1566 the R4000, R4400, R4600, and 4700.
1570 depends on SYS_HAS_CPU_TX49XX
1571 select CPU_HAS_PREFETCH
1572 select CPU_SUPPORTS_32BIT_KERNEL
1573 select CPU_SUPPORTS_64BIT_KERNEL
1574 select CPU_SUPPORTS_HUGEPAGES
1578 depends on SYS_HAS_CPU_R5000
1579 select CPU_SUPPORTS_32BIT_KERNEL
1580 select CPU_SUPPORTS_64BIT_KERNEL
1581 select CPU_SUPPORTS_HUGEPAGES
1583 MIPS Technologies R5000-series processors other than the Nevada.
1587 depends on SYS_HAS_CPU_R5500
1588 select CPU_SUPPORTS_32BIT_KERNEL
1589 select CPU_SUPPORTS_64BIT_KERNEL
1590 select CPU_SUPPORTS_HUGEPAGES
1592 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1597 depends on SYS_HAS_CPU_NEVADA
1598 select CPU_SUPPORTS_32BIT_KERNEL
1599 select CPU_SUPPORTS_64BIT_KERNEL
1600 select CPU_SUPPORTS_HUGEPAGES
1602 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1606 depends on SYS_HAS_CPU_R10000
1607 select CPU_HAS_PREFETCH
1608 select CPU_SUPPORTS_32BIT_KERNEL
1609 select CPU_SUPPORTS_64BIT_KERNEL
1610 select CPU_SUPPORTS_HIGHMEM
1611 select CPU_SUPPORTS_HUGEPAGES
1613 MIPS Technologies R10000-series processors.
1617 depends on SYS_HAS_CPU_RM7000
1618 select CPU_HAS_PREFETCH
1619 select CPU_SUPPORTS_32BIT_KERNEL
1620 select CPU_SUPPORTS_64BIT_KERNEL
1621 select CPU_SUPPORTS_HIGHMEM
1622 select CPU_SUPPORTS_HUGEPAGES
1626 depends on SYS_HAS_CPU_SB1
1627 select CPU_SUPPORTS_32BIT_KERNEL
1628 select CPU_SUPPORTS_64BIT_KERNEL
1629 select CPU_SUPPORTS_HIGHMEM
1630 select CPU_SUPPORTS_HUGEPAGES
1631 select WEAK_ORDERING
1633 config CPU_CAVIUM_OCTEON
1634 bool "Cavium Octeon processor"
1635 depends on SYS_HAS_CPU_CAVIUM_OCTEON
1636 select CPU_HAS_PREFETCH
1637 select CPU_SUPPORTS_64BIT_KERNEL
1638 select HAVE_PAGE_SIZE_8KB if !MIPS_VA_BITS_48
1639 select HAVE_PAGE_SIZE_32KB if !MIPS_VA_BITS_48
1640 select WEAK_ORDERING
1641 select CPU_SUPPORTS_HIGHMEM
1642 select CPU_SUPPORTS_HUGEPAGES
1643 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
1644 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
1645 select MIPS_L1_CACHE_SHIFT_7
1646 select CPU_SUPPORTS_VZ
1648 The Cavium Octeon processor is a highly integrated chip containing
1649 many ethernet hardware widgets for networking tasks. The processor
1650 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
1651 Full details can be found at http://www.caviumnetworks.com.
1654 bool "Broadcom BMIPS"
1655 depends on SYS_HAS_CPU_BMIPS
1657 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
1658 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
1659 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
1660 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
1661 select CPU_SUPPORTS_32BIT_KERNEL
1662 select DMA_NONCOHERENT
1664 select SWAP_IO_SPACE
1665 select WEAK_ORDERING
1666 select CPU_SUPPORTS_HIGHMEM
1667 select CPU_HAS_PREFETCH
1668 select CPU_SUPPORTS_CPUFREQ
1669 select MIPS_EXTERNAL_TIMER
1670 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
1672 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
1676 config LOONGSON3_ENHANCEMENT
1677 bool "New Loongson-3 CPU Enhancements"
1679 depends on CPU_LOONGSON64
1681 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1682 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1683 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1684 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1685 Fast TLB refill support, etc.
1687 This option enable those enhancements which are not probed at run
1688 time. If you want a generic kernel to run on all Loongson 3 machines,
1689 please say 'N' here. If you want a high-performance kernel to run on
1690 new Loongson-3 machines only, please say 'Y' here.
1692 config CPU_LOONGSON3_WORKAROUNDS
1693 bool "Loongson-3 LLSC Workarounds"
1695 depends on CPU_LOONGSON64
1697 Loongson-3 processors have the llsc issues which require workarounds.
1698 Without workarounds the system may hang unexpectedly.
1700 Say Y, unless you know what you are doing.
1702 config CPU_LOONGSON3_CPUCFG_EMULATION
1703 bool "Emulate the CPUCFG instruction on older Loongson cores"
1705 depends on CPU_LOONGSON64
1707 Loongson-3A R4 and newer have the CPUCFG instruction available for
1708 userland to query CPU capabilities, much like CPUID on x86. This
1709 option provides emulation of the instruction on older Loongson
1710 cores, back to Loongson-3A1000.
1712 If unsure, please say Y.
1714 config CPU_MIPS32_3_5_FEATURES
1715 bool "MIPS32 Release 3.5 Features"
1716 depends on SYS_HAS_CPU_MIPS32_R3_5
1717 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
1720 Choose this option to build a kernel for release 2 or later of the
1721 MIPS32 architecture including features from the 3.5 release such as
1722 support for Enhanced Virtual Addressing (EVA).
1724 config CPU_MIPS32_3_5_EVA
1725 bool "Enhanced Virtual Addressing (EVA)"
1726 depends on CPU_MIPS32_3_5_FEATURES
1730 Choose this option if you want to enable the Enhanced Virtual
1731 Addressing (EVA) on your MIPS32 core (such as proAptiv).
1732 One of its primary benefits is an increase in the maximum size
1733 of lowmem (up to 3GB). If unsure, say 'N' here.
1735 config CPU_MIPS32_R5_FEATURES
1736 bool "MIPS32 Release 5 Features"
1737 depends on SYS_HAS_CPU_MIPS32_R5
1738 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
1740 Choose this option to build a kernel for release 2 or later of the
1741 MIPS32 architecture including features from release 5 such as
1742 support for Extended Physical Addressing (XPA).
1744 config CPU_MIPS32_R5_XPA
1745 bool "Extended Physical Addressing (XPA)"
1746 depends on CPU_MIPS32_R5_FEATURES
1748 depends on !PAGE_SIZE_4KB
1749 depends on SYS_SUPPORTS_HIGHMEM
1752 select PHYS_ADDR_T_64BIT
1755 Choose this option if you want to enable the Extended Physical
1756 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
1757 benefit is to increase physical addressing equal to or greater
1758 than 40 bits. Note that this has the side effect of turning on
1759 64-bit addressing which in turn makes the PTEs 64-bit in size.
1760 If unsure, say 'N' here.
1763 config CPU_NOP_WORKAROUNDS
1766 config CPU_JUMP_WORKAROUNDS
1769 config CPU_LOONGSON2F_WORKAROUNDS
1770 bool "Loongson 2F Workarounds"
1772 select CPU_NOP_WORKAROUNDS
1773 select CPU_JUMP_WORKAROUNDS
1775 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1776 require workarounds. Without workarounds the system may hang
1777 unexpectedly. For more information please refer to the gas
1778 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1780 Loongson 2F03 and later have fixed these issues and no workarounds
1781 are needed. The workarounds have no significant side effect on them
1782 but may decrease the performance of the system so this option should
1783 be disabled unless the kernel is intended to be run on 2F01 or 2F02
1786 If unsure, please say Y.
1787 endif # CPU_LOONGSON2F
1789 config SYS_SUPPORTS_ZBOOT
1791 select HAVE_KERNEL_GZIP
1792 select HAVE_KERNEL_BZIP2
1793 select HAVE_KERNEL_LZ4
1794 select HAVE_KERNEL_LZMA
1795 select HAVE_KERNEL_LZO
1796 select HAVE_KERNEL_XZ
1797 select HAVE_KERNEL_ZSTD
1799 config SYS_SUPPORTS_ZBOOT_UART16550
1801 select SYS_SUPPORTS_ZBOOT
1803 config SYS_SUPPORTS_ZBOOT_UART_PROM
1805 select SYS_SUPPORTS_ZBOOT
1807 config CPU_LOONGSON2EF
1809 select CPU_SUPPORTS_32BIT_KERNEL
1810 select CPU_SUPPORTS_64BIT_KERNEL
1811 select CPU_SUPPORTS_HIGHMEM
1812 select CPU_SUPPORTS_HUGEPAGES
1814 config CPU_LOONGSON32
1818 select CPU_HAS_PREFETCH
1819 select CPU_SUPPORTS_32BIT_KERNEL
1820 select CPU_SUPPORTS_HIGHMEM
1821 select CPU_SUPPORTS_CPUFREQ
1823 config CPU_BMIPS32_3300
1824 select SMP_UP if SMP
1827 config CPU_BMIPS4350
1829 select SYS_SUPPORTS_SMP
1830 select SYS_SUPPORTS_HOTPLUG_CPU
1832 config CPU_BMIPS4380
1834 select MIPS_L1_CACHE_SHIFT_6
1835 select SYS_SUPPORTS_SMP
1836 select SYS_SUPPORTS_HOTPLUG_CPU
1839 config CPU_BMIPS5000
1841 select MIPS_CPU_SCACHE
1842 select MIPS_L1_CACHE_SHIFT_7
1843 select SYS_SUPPORTS_SMP
1844 select SYS_SUPPORTS_HOTPLUG_CPU
1847 config SYS_HAS_CPU_LOONGSON64
1849 select CPU_SUPPORTS_CPUFREQ
1852 config SYS_HAS_CPU_LOONGSON2E
1855 config SYS_HAS_CPU_LOONGSON2F
1857 select CPU_SUPPORTS_CPUFREQ
1858 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1860 config SYS_HAS_CPU_LOONGSON1B
1863 config SYS_HAS_CPU_LOONGSON1C
1866 config SYS_HAS_CPU_MIPS32_R1
1869 config SYS_HAS_CPU_MIPS32_R2
1872 config SYS_HAS_CPU_MIPS32_R3_5
1875 config SYS_HAS_CPU_MIPS32_R5
1878 config SYS_HAS_CPU_MIPS32_R6
1881 config SYS_HAS_CPU_MIPS64_R1
1884 config SYS_HAS_CPU_MIPS64_R2
1887 config SYS_HAS_CPU_MIPS64_R5
1890 config SYS_HAS_CPU_MIPS64_R6
1893 config SYS_HAS_CPU_P5600
1896 config SYS_HAS_CPU_R3000
1899 config SYS_HAS_CPU_R4300
1902 config SYS_HAS_CPU_R4X00
1905 config SYS_HAS_CPU_TX49XX
1908 config SYS_HAS_CPU_R5000
1911 config SYS_HAS_CPU_R5500
1914 config SYS_HAS_CPU_NEVADA
1917 config SYS_HAS_CPU_R10000
1920 config SYS_HAS_CPU_RM7000
1923 config SYS_HAS_CPU_SB1
1926 config SYS_HAS_CPU_CAVIUM_OCTEON
1929 config SYS_HAS_CPU_BMIPS
1932 config SYS_HAS_CPU_BMIPS32_3300
1934 select SYS_HAS_CPU_BMIPS
1936 config SYS_HAS_CPU_BMIPS4350
1938 select SYS_HAS_CPU_BMIPS
1940 config SYS_HAS_CPU_BMIPS4380
1942 select SYS_HAS_CPU_BMIPS
1944 config SYS_HAS_CPU_BMIPS5000
1946 select SYS_HAS_CPU_BMIPS
1949 # CPU may reorder R->R, R->W, W->R, W->W
1950 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1952 config WEAK_ORDERING
1956 # CPU may reorder reads and writes beyond LL/SC
1957 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1959 config WEAK_REORDERING_BEYOND_LLSC
1964 # These two indicate any level of the MIPS32 and MIPS64 architecture
1968 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
1969 CPU_MIPS32_R6 || CPU_P5600
1973 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
1974 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1977 # These indicate the revision of the architecture
1981 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1985 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1987 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1992 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
1994 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1999 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
2001 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
2002 select HAVE_ARCH_BITREVERSE
2003 select MIPS_ASID_BITS_VARIABLE
2004 select MIPS_CRC_SUPPORT
2007 config TARGET_ISA_REV
2009 default 1 if CPU_MIPSR1
2010 default 2 if CPU_MIPSR2
2011 default 5 if CPU_MIPSR5
2012 default 6 if CPU_MIPSR6
2015 Reflects the ISA revision being targeted by the kernel build. This
2016 is effectively the Kconfig equivalent of MIPS_ISA_REV.
2024 config SYS_SUPPORTS_32BIT_KERNEL
2026 config SYS_SUPPORTS_64BIT_KERNEL
2028 config CPU_SUPPORTS_32BIT_KERNEL
2030 config CPU_SUPPORTS_64BIT_KERNEL
2032 config CPU_SUPPORTS_CPUFREQ
2034 config CPU_SUPPORTS_ADDRWINCFG
2036 config CPU_SUPPORTS_HUGEPAGES
2038 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
2039 config CPU_SUPPORTS_VZ
2041 config MIPS_PGD_C0_CONTEXT
2044 default y if (CPU_MIPSR2 || CPU_MIPSR6)
2047 # Set to y for ptrace access to watch registers.
2049 config HARDWARE_WATCHPOINTS
2051 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
2056 prompt "Kernel code model"
2058 You should only select this option if you have a workload that
2059 actually benefits from 64-bit processing or if your machine has
2060 large memory. You will only be presented a single option in this
2061 menu if your system does not support both 32-bit and 64-bit kernels.
2064 bool "32-bit kernel"
2065 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
2068 Select this option if you want to build a 32-bit kernel.
2071 bool "64-bit kernel"
2072 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
2074 Select this option if you want to build a 64-bit kernel.
2078 config MIPS_VA_BITS_48
2079 bool "48 bits virtual memory"
2082 Support a maximum at least 48 bits of application virtual
2083 memory. Default is 40 bits or less, depending on the CPU.
2084 For page sizes 16k and above, this option results in a small
2085 memory overhead for page tables. For 4k page size, a fourth
2086 level of page tables is added which imposes both a memory
2087 overhead as well as slower TLB fault handling.
2091 config ZBOOT_LOAD_ADDRESS
2092 hex "Compressed kernel load address"
2093 default 0xffffffff80400000 if BCM47XX
2095 depends on SYS_SUPPORTS_ZBOOT
2097 The address to load compressed kernel, aka vmlinuz.
2099 This is only used if non-zero.
2101 config ARCH_FORCE_MAX_ORDER
2102 int "Maximum zone order"
2103 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
2104 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
2105 default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
2108 The kernel memory allocator divides physically contiguous memory
2109 blocks into "zones", where each zone is a power of two number of
2110 pages. This option selects the largest power of two that the kernel
2111 keeps in the memory allocator. If you need to allocate very large
2112 blocks of physically contiguous memory, then you may need to
2113 increase this value.
2115 The page size is not necessarily 4KB. Keep this in mind
2116 when choosing a value for this option.
2121 config IP22_CPU_SCACHE
2126 # Support for a MIPS32 / MIPS64 style S-caches
2128 config MIPS_CPU_SCACHE
2132 config R5000_CPU_SCACHE
2136 config RM7000_CPU_SCACHE
2140 config SIBYTE_DMA_PAGEOPS
2141 bool "Use DMA to clear/copy pages"
2144 Instead of using the CPU to zero and copy pages, use a Data Mover
2145 channel. These DMA channels are otherwise unused by the standard
2146 SiByte Linux port. Seems to give a small performance benefit.
2148 config CPU_HAS_PREFETCH
2151 config CPU_GENERIC_DUMP_TLB
2153 default y if !CPU_R3000
2155 config MIPS_FP_SUPPORT
2156 bool "Floating Point support" if EXPERT
2159 Select y to include support for floating point in the kernel
2160 including initialization of FPU hardware, FP context save & restore
2161 and emulation of an FPU where necessary. Without this support any
2162 userland program attempting to use floating point instructions will
2165 If you know that your userland will not attempt to use floating point
2166 instructions then you can say n here to shrink the kernel a little.
2170 config CPU_R2300_FPU
2172 depends on MIPS_FP_SUPPORT
2173 default y if CPU_R3000
2180 depends on MIPS_FP_SUPPORT
2181 default y if !CPU_R2300_FPU
2183 config CPU_R4K_CACHE_TLB
2185 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
2188 bool "MIPS MT SMP support (1 TC on each available VPE)"
2190 depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
2191 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
2192 select CPU_MIPSR2_IRQ_VI
2193 select CPU_MIPSR2_IRQ_EI
2198 select SYS_SUPPORTS_SMP
2199 select SYS_SUPPORTS_SCHED_SMT
2200 select MIPS_PERF_SHARED_TC_COUNTERS
2202 This is a kernel model which is known as SMVP. This is supported
2203 on cores with the MT ASE and uses the available VPEs to implement
2204 virtual processors which supports SMP. This is equivalent to the
2205 Intel Hyperthreading feature. For further information go to
2206 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2212 bool "SMT (multithreading) scheduler support"
2213 depends on SYS_SUPPORTS_SCHED_SMT
2216 SMT scheduler support improves the CPU scheduler's decision making
2217 when dealing with MIPS MT enabled cores at a cost of slightly
2218 increased overhead in some places. If unsure say N here.
2220 config SYS_SUPPORTS_SCHED_SMT
2223 config SYS_SUPPORTS_MULTITHREADING
2226 config MIPS_MT_FPAFF
2227 bool "Dynamic FPU affinity for FP-intensive threads"
2229 depends on MIPS_MT_SMP
2231 config MIPSR2_TO_R6_EMULATOR
2232 bool "MIPS R2-to-R6 emulator"
2233 depends on CPU_MIPSR6
2234 depends on MIPS_FP_SUPPORT
2237 Choose this option if you want to run non-R6 MIPS userland code.
2238 Even if you say 'Y' here, the emulator will still be disabled by
2239 default. You can enable it using the 'mipsr2emu' kernel option.
2240 The only reason this is a build-time option is to save ~14K from the
2243 config SYS_SUPPORTS_VPE_LOADER
2245 depends on SYS_SUPPORTS_MULTITHREADING
2247 Indicates that the platform supports the VPE loader, and provides
2250 config MIPS_VPE_LOADER
2251 bool "VPE loader support."
2252 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
2253 select CPU_MIPSR2_IRQ_VI
2254 select CPU_MIPSR2_IRQ_EI
2257 Includes a loader for loading an elf relocatable object
2258 onto another VPE and running it.
2260 config MIPS_VPE_LOADER_MT
2263 depends on MIPS_VPE_LOADER
2265 config MIPS_VPE_LOADER_TOM
2266 bool "Load VPE program into memory hidden from linux"
2267 depends on MIPS_VPE_LOADER
2270 The loader can use memory that is present but has been hidden from
2271 Linux using the kernel command line option "mem=xxMB". It's up to
2272 you to ensure the amount you put in the option and the space your
2273 program requires is less or equal to the amount physically present.
2275 config MIPS_VPE_APSP_API
2276 bool "Enable support for AP/SP API (RTLX)"
2277 depends on MIPS_VPE_LOADER
2279 config MIPS_VPE_APSP_API_MT
2282 depends on MIPS_VPE_APSP_API
2285 bool "MIPS Coherent Processing System support"
2286 depends on SYS_SUPPORTS_MIPS_CPS
2288 select MIPS_CPS_PM if HOTPLUG_CPU
2290 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
2291 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
2292 select SYS_SUPPORTS_HOTPLUG_CPU
2293 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
2294 select SYS_SUPPORTS_SMP
2295 select WEAK_ORDERING
2296 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
2298 Select this if you wish to run an SMP kernel across multiple cores
2299 within a MIPS Coherent Processing System. When this option is
2300 enabled the kernel will probe for other cores and boot them with
2301 no external assistance. It is safe to enable this when hardware
2302 support is unavailable.
2315 config SB1_PASS_2_WORKAROUNDS
2317 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
2320 config SB1_PASS_2_1_WORKAROUNDS
2322 depends on CPU_SB1 && CPU_SB1_PASS_2
2326 prompt "SmartMIPS or microMIPS ASE support"
2328 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
2331 Select this if you want neither microMIPS nor SmartMIPS support
2333 config CPU_HAS_SMARTMIPS
2334 depends on SYS_SUPPORTS_SMARTMIPS
2337 SmartMIPS is a extension of the MIPS32 architecture aimed at
2338 increased security at both hardware and software level for
2339 smartcards. Enabling this option will allow proper use of the
2340 SmartMIPS instructions by Linux applications. However a kernel with
2341 this option will not work on a MIPS core without SmartMIPS core. If
2342 you don't know you probably don't have SmartMIPS and should say N
2345 config CPU_MICROMIPS
2346 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
2349 When this option is enabled the kernel will be built using the
2355 bool "Support for the MIPS SIMD Architecture"
2356 depends on CPU_SUPPORTS_MSA
2357 depends on MIPS_FP_SUPPORT
2358 depends on 64BIT || MIPS_O32_FP64_SUPPORT
2360 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
2361 and a set of SIMD instructions to operate on them. When this option
2362 is enabled the kernel will support allocating & switching MSA
2363 vector register contexts. If you know that your kernel will only be
2364 running on CPUs which do not support MSA or that your userland will
2365 not be making use of it then you may wish to say N here to reduce
2366 the size & complexity of your kernel.
2377 depends on !CPU_DIEI_BROKEN
2380 config CPU_DIEI_BROKEN
2386 config CPU_NO_LOAD_STORE_LR
2389 CPU lacks support for unaligned load and store instructions:
2390 LWL, LWR, SWL, SWR (Load/store word left/right).
2391 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
2395 # Vectored interrupt mode is an R2 feature
2397 config CPU_MIPSR2_IRQ_VI
2401 # Extended interrupt mode is an R2 feature
2403 config CPU_MIPSR2_IRQ_EI
2408 depends on !CPU_R3000
2415 # Work around the "daddi" and "daddiu" CPU errata:
2417 # - The `daddi' instruction fails to trap on overflow.
2418 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2421 # - The `daddiu' instruction can produce an incorrect result.
2422 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2424 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2426 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
2427 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
2428 config CPU_DADDI_WORKAROUNDS
2431 # Work around certain R4000 CPU errata (as implemented by GCC):
2433 # - A double-word or a variable shift may give an incorrect result
2434 # if executed immediately after starting an integer division:
2435 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2437 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2440 # - A double-word or a variable shift may give an incorrect result
2441 # if executed while an integer multiplication is in progress:
2442 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2445 # - An integer division may give an incorrect result if started in
2446 # a delay slot of a taken branch or a jump:
2447 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2449 config CPU_R4000_WORKAROUNDS
2451 select CPU_R4400_WORKAROUNDS
2453 # Work around certain R4400 CPU errata (as implemented by GCC):
2455 # - A double-word or a variable shift may give an incorrect result
2456 # if executed immediately after starting an integer division:
2457 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
2458 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
2459 config CPU_R4400_WORKAROUNDS
2462 config CPU_R4X00_BUGS64
2464 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
2466 config MIPS_ASID_SHIFT
2468 default 6 if CPU_R3000
2471 config MIPS_ASID_BITS
2473 default 0 if MIPS_ASID_BITS_VARIABLE
2474 default 6 if CPU_R3000
2477 config MIPS_ASID_BITS_VARIABLE
2480 config MIPS_CRC_SUPPORT
2483 # R4600 erratum. Due to the lack of errata information the exact
2484 # technical details aren't known. I've experimentally found that disabling
2485 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2487 config WAR_R4600_V1_INDEX_ICACHEOP
2490 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
2492 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
2493 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
2494 # executed if there is no other dcache activity. If the dcache is
2495 # accessed for another instruction immediately preceding when these
2496 # cache instructions are executing, it is possible that the dcache
2497 # tag match outputs used by these cache instructions will be
2498 # incorrect. These cache instructions should be preceded by at least
2499 # four instructions that are not any kind of load or store
2502 # This is not allowed: lw
2506 # cache Hit_Writeback_Invalidate_D
2508 # This is allowed: lw
2513 # cache Hit_Writeback_Invalidate_D
2514 config WAR_R4600_V1_HIT_CACHEOP
2517 # Writeback and invalidate the primary cache dcache before DMA.
2519 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
2520 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
2521 # operate correctly if the internal data cache refill buffer is empty. These
2522 # CACHE instructions should be separated from any potential data cache miss
2523 # by a load instruction to an uncached address to empty the response buffer."
2524 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
2526 config WAR_R4600_V2_HIT_CACHEOP
2529 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
2530 # the line which this instruction itself exists, the following
2531 # operation is not guaranteed."
2533 # Workaround: do two phase flushing for Index_Invalidate_I
2534 config WAR_TX49XX_ICACHE_INDEX_INV
2537 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2538 # opposes it being called that) where invalid instructions in the same
2539 # I-cache line worth of instructions being fetched may case spurious
2541 config WAR_ICACHE_REFILLS
2544 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
2545 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2546 config WAR_R10000_LLSC
2549 # 34K core erratum: "Problems Executing the TLBR Instruction"
2550 config WAR_MIPS34K_MISSED_ITLB
2554 # - Highmem only makes sense for the 32-bit kernel.
2555 # - The current highmem code will only work properly on physically indexed
2556 # caches such as R3000, SB1, R7000 or those that look like they're virtually
2557 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
2558 # moment we protect the user and offer the highmem option only on machines
2559 # where it's known to be safe. This will not offer highmem on a few systems
2560 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
2561 # indexed CPUs but we're playing safe.
2562 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2563 # know they might have memory configurations that could make use of highmem
2567 bool "High Memory Support"
2568 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
2571 config CPU_SUPPORTS_HIGHMEM
2574 config SYS_SUPPORTS_HIGHMEM
2577 config SYS_SUPPORTS_SMARTMIPS
2580 config SYS_SUPPORTS_MICROMIPS
2583 config SYS_SUPPORTS_MIPS16
2586 This option must be set if a kernel might be executed on a MIPS16-
2587 enabled CPU even if MIPS16 is not actually being used. In other
2588 words, it makes the kernel MIPS16-tolerant.
2590 config CPU_SUPPORTS_MSA
2593 config ARCH_FLATMEM_ENABLE
2595 depends on !NUMA && !CPU_LOONGSON2EF
2597 config ARCH_SPARSEMEM_ENABLE
2602 depends on SYS_SUPPORTS_NUMA
2604 select HAVE_SETUP_PER_CPU_AREA
2605 select NEED_PER_CPU_EMBED_FIRST_CHUNK
2607 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2608 Access). This option improves performance on systems with more
2609 than two nodes; on two node systems it is generally better to
2610 leave it disabled; on single node systems leave this option
2613 config SYS_SUPPORTS_NUMA
2616 config HAVE_ARCH_NODEDATA_EXTENSION
2620 bool "Relocatable kernel"
2621 depends on SYS_SUPPORTS_RELOCATABLE
2622 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
2623 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
2624 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
2625 CPU_P5600 || CAVIUM_OCTEON_SOC || \
2628 This builds a kernel image that retains relocation information
2629 so it can be loaded someplace besides the default 1MB.
2630 The relocations make the kernel binary about 15% larger,
2631 but are discarded at runtime
2633 config RELOCATION_TABLE_SIZE
2634 hex "Relocation table size"
2635 depends on RELOCATABLE
2636 range 0x0 0x01000000
2637 default "0x00200000" if CPU_LOONGSON64
2638 default "0x00100000"
2640 A table of relocation data will be appended to the kernel binary
2641 and parsed at boot to fix up the relocated kernel.
2643 This option allows the amount of space reserved for the table to be
2644 adjusted, although the default of 1Mb should be ok in most cases.
2646 The build will fail and a valid size suggested if this is too small.
2648 If unsure, leave at the default value.
2650 config RANDOMIZE_BASE
2651 bool "Randomize the address of the kernel image"
2652 depends on RELOCATABLE
2654 Randomizes the physical and virtual address at which the
2655 kernel image is loaded, as a security feature that
2656 deters exploit attempts relying on knowledge of the location
2657 of kernel internals.
2659 Entropy is generated using any coprocessor 0 registers available.
2661 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
2665 config RANDOMIZE_BASE_MAX_OFFSET
2666 hex "Maximum kASLR offset" if EXPERT
2667 depends on RANDOMIZE_BASE
2668 range 0x0 0x40000000 if EVA || 64BIT
2669 range 0x0 0x08000000
2670 default "0x01000000"
2672 When kASLR is active, this provides the maximum offset that will
2673 be applied to the kernel image. It should be set according to the
2674 amount of physical RAM available in the target system minus
2675 PHYSICAL_START and must be a power of 2.
2677 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2678 EVA or 64-bit. The default is 16Mb.
2685 config HW_PERF_EVENTS
2686 bool "Enable hardware performance counter support for perf events"
2687 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
2690 Enable hardware performance counter support for perf events. If
2691 disabled, perf events will use software events only.
2694 bool "Enable DMI scanning"
2695 depends on MACH_LOONGSON64
2696 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
2699 Enabled scanning of DMI to identify machine quirks. Say Y
2700 here unless you have verified that your setup is not
2701 affected by entries in the DMI blacklist. Required by PNP
2705 bool "Multi-Processing support"
2706 depends on SYS_SUPPORTS_SMP
2708 This enables support for systems with more than one CPU. If you have
2709 a system with only one CPU, say N. If you have a system with more
2710 than one CPU, say Y.
2712 If you say N here, the kernel will run on uni- and multiprocessor
2713 machines, but will use only one CPU of a multiprocessor machine. If
2714 you say Y here, the kernel will run on many, but not all,
2715 uniprocessor machines. On a uniprocessor machine, the kernel
2716 will run faster if you say N here.
2718 People using multiprocessor machines who say Y here should also say
2719 Y to "Enhanced Real Time Clock Support", below.
2721 See also the SMP-HOWTO available at
2722 <https://www.tldp.org/docs.html#howto>.
2724 If you don't know what to do here, say N.
2727 bool "Support for hot-pluggable CPUs"
2728 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
2730 Say Y here to allow turning CPUs off and on. CPUs can be
2731 controlled through /sys/devices/system/cpu.
2732 (Note: power management support will enable this option
2733 automatically on SMP systems. )
2734 Say N if you want to disable CPU hotplug.
2739 config SYS_SUPPORTS_MIPS_CPS
2742 config SYS_SUPPORTS_SMP
2745 config NR_CPUS_DEFAULT_4
2748 config NR_CPUS_DEFAULT_8
2751 config NR_CPUS_DEFAULT_16
2754 config NR_CPUS_DEFAULT_32
2757 config NR_CPUS_DEFAULT_64
2761 int "Maximum number of CPUs (2-256)"
2764 default "4" if NR_CPUS_DEFAULT_4
2765 default "8" if NR_CPUS_DEFAULT_8
2766 default "16" if NR_CPUS_DEFAULT_16
2767 default "32" if NR_CPUS_DEFAULT_32
2768 default "64" if NR_CPUS_DEFAULT_64
2770 This allows you to specify the maximum number of CPUs which this
2771 kernel will support. The maximum supported value is 32 for 32-bit
2772 kernel and 64 for 64-bit kernels; the minimum value which makes
2773 sense is 1 for Qemu (useful only for kernel debugging purposes)
2774 and 2 for all others.
2776 This is purely to save memory - each supported CPU adds
2777 approximately eight kilobytes to the kernel image. For best
2778 performance should round up your number of processors to the next
2781 config MIPS_PERF_SHARED_TC_COUNTERS
2784 config MIPS_NR_CPU_NR_MAP_1024
2787 config MIPS_NR_CPU_NR_MAP
2790 default 1024 if MIPS_NR_CPU_NR_MAP_1024
2791 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
2794 # Timer Interrupt Frequency Configuration
2798 prompt "Timer frequency"
2801 Allows the configuration of the timer frequency.
2804 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2807 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2810 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2813 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2816 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2819 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2822 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2825 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2829 config SYS_SUPPORTS_24HZ
2832 config SYS_SUPPORTS_48HZ
2835 config SYS_SUPPORTS_100HZ
2838 config SYS_SUPPORTS_128HZ
2841 config SYS_SUPPORTS_250HZ
2844 config SYS_SUPPORTS_256HZ
2847 config SYS_SUPPORTS_1000HZ
2850 config SYS_SUPPORTS_1024HZ
2853 config SYS_SUPPORTS_ARBIT_HZ
2855 default y if !SYS_SUPPORTS_24HZ && \
2856 !SYS_SUPPORTS_48HZ && \
2857 !SYS_SUPPORTS_100HZ && \
2858 !SYS_SUPPORTS_128HZ && \
2859 !SYS_SUPPORTS_250HZ && \
2860 !SYS_SUPPORTS_256HZ && \
2861 !SYS_SUPPORTS_1000HZ && \
2862 !SYS_SUPPORTS_1024HZ
2868 default 100 if HZ_100
2869 default 128 if HZ_128
2870 default 250 if HZ_250
2871 default 256 if HZ_256
2872 default 1000 if HZ_1000
2873 default 1024 if HZ_1024
2876 def_bool HIGH_RES_TIMERS
2878 config ARCH_SUPPORTS_KEXEC
2881 config ARCH_SUPPORTS_CRASH_DUMP
2884 config PHYSICAL_START
2885 hex "Physical address where the kernel is loaded"
2886 default "0xffffffff84000000"
2887 depends on CRASH_DUMP
2889 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
2890 If you plan to use kernel for capturing the crash dump change
2891 this value to start of the reserved region (the "X" value as
2892 specified in the "crashkernel=YM@XM" command line boot parameter
2893 passed to the panic-ed kernel).
2895 config MIPS_O32_FP64_SUPPORT
2896 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
2897 depends on 32BIT || MIPS32_O32
2899 When this is enabled, the kernel will support use of 64-bit floating
2900 point registers with binaries using the O32 ABI along with the
2901 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
2902 32-bit MIPS systems this support is at the cost of increasing the
2903 size and complexity of the compiled FPU emulator. Thus if you are
2904 running a MIPS32 system and know that none of your userland binaries
2905 will require 64-bit floating point, you may wish to reduce the size
2906 of your kernel & potentially improve FP emulation performance by
2909 Although binutils currently supports use of this flag the details
2910 concerning its effect upon the O32 ABI in userland are still being
2911 worked on. In order to avoid userland becoming dependent upon current
2912 behaviour before the details have been finalised, this option should
2913 be considered experimental and only enabled by those working upon
2921 select OF_EARLY_FLATTREE
2931 prompt "Kernel appended dtb support"
2933 default MIPS_NO_APPENDED_DTB
2935 config MIPS_NO_APPENDED_DTB
2938 Do not enable appended dtb support.
2940 config MIPS_ELF_APPENDED_DTB
2943 With this option, the boot code will look for a device tree binary
2944 DTB) included in the vmlinux ELF section .appended_dtb. By default
2945 it is empty and the DTB can be appended using binutils command
2948 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
2950 This is meant as a backward compatibility convenience for those
2951 systems with a bootloader that can't be upgraded to accommodate
2952 the documented boot protocol using a device tree.
2954 config MIPS_RAW_APPENDED_DTB
2955 bool "vmlinux.bin or vmlinuz.bin"
2957 With this option, the boot code will look for a device tree binary
2958 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
2959 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
2961 This is meant as a backward compatibility convenience for those
2962 systems with a bootloader that can't be upgraded to accommodate
2963 the documented boot protocol using a device tree.
2965 Beware that there is very little in terms of protection against
2966 this option being confused by leftover garbage in memory that might
2967 look like a DTB header after a reboot if no actual DTB is appended
2968 to vmlinux.bin. Do not leave this option active in a production kernel
2969 if you don't intend to always append a DTB.
2973 prompt "Kernel command line type"
2974 depends on !CMDLINE_OVERRIDE
2975 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2976 !MACH_LOONGSON64 && !MIPS_MALTA && \
2978 default MIPS_CMDLINE_FROM_BOOTLOADER
2980 config MIPS_CMDLINE_FROM_DTB
2982 bool "Dtb kernel arguments if available"
2984 config MIPS_CMDLINE_DTB_EXTEND
2986 bool "Extend dtb kernel arguments with bootloader arguments"
2988 config MIPS_CMDLINE_FROM_BOOTLOADER
2989 bool "Bootloader kernel arguments if available"
2991 config MIPS_CMDLINE_BUILTIN_EXTEND
2992 depends on CMDLINE_BOOL
2993 bool "Extend builtin kernel arguments with bootloader arguments"
2998 config LOCKDEP_SUPPORT
3002 config STACKTRACE_SUPPORT
3006 config PGTABLE_LEVELS
3008 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
3009 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
3012 config MIPS_AUTO_PFN_OFFSET
3015 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
3017 config PCI_DRIVERS_GENERIC
3018 select PCI_DOMAINS_GENERIC if PCI
3021 config PCI_DRIVERS_LEGACY
3022 def_bool !PCI_DRIVERS_GENERIC
3023 select NO_GENERIC_PCI_IOPORT_MAP
3024 select PCI_DOMAINS if PCI
3027 # ISA support is now enabled via select. Too many systems still have the one
3028 # or other ISA chip on the board that users don't know about so don't expect
3029 # users to choose the right thing ...
3035 bool "TURBOchannel support"
3036 depends on MACH_DECSTATION
3038 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
3039 processors. TURBOchannel programming specifications are available
3041 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
3043 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
3044 Linux driver support status is documented at:
3045 <http://www.linux-mips.org/wiki/DECstation>
3051 config ARCH_MMAP_RND_BITS_MIN
3055 config ARCH_MMAP_RND_BITS_MAX
3059 config ARCH_MMAP_RND_COMPAT_BITS_MIN
3062 config ARCH_MMAP_RND_COMPAT_BITS_MAX
3069 select MIPS_EXTERNAL_TIMER
3075 config MIPS32_COMPAT
3082 bool "Kernel support for o32 binaries"
3084 select ARCH_WANT_OLD_COMPAT_IPC
3086 select MIPS32_COMPAT
3088 Select this option if you want to run o32 binaries. These are pure
3089 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3090 existing binaries are in this format.
3095 bool "Kernel support for n32 binaries"
3097 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
3099 select MIPS32_COMPAT
3101 Select this option if you want to run n32 binaries. These are
3102 64-bit binaries using 32-bit quantities for addressing and certain
3103 data that would normally be 64-bit. They are used in special
3108 config CC_HAS_MNO_BRANCH_LIKELY
3110 depends on $(cc-option,-mno-branch-likely)
3112 # https://github.com/llvm/llvm-project/issues/61045
3113 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
3114 def_bool y if CC_IS_CLANG
3116 menu "Power management options"
3118 config ARCH_HIBERNATION_POSSIBLE
3120 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3122 config ARCH_SUSPEND_POSSIBLE
3124 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3126 source "kernel/power/Kconfig"
3130 config MIPS_EXTERNAL_TIMER
3133 menu "CPU Power Management"
3135 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3136 source "drivers/cpufreq/Kconfig"
3137 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3139 source "drivers/cpuidle/Kconfig"
3143 source "arch/mips/kvm/Kconfig"
3145 source "arch/mips/vdso/Kconfig"