2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
31 #include <linux/of_address.h>
32 #include <linux/of_pci.h>
33 #include <linux/export.h>
35 #include <asm/processor.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/byteorder.h>
40 static DEFINE_SPINLOCK(hose_spinlock);
43 /* XXX kill that some day ... */
44 static int global_phb_number; /* Global phb counter */
46 /* ISA Memory physical address */
47 resource_size_t isa_mem_base;
49 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
51 unsigned long isa_io_base;
52 unsigned long pci_dram_offset;
53 static int pci_bus_count;
56 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
58 pci_dma_ops = dma_ops;
61 struct dma_map_ops *get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops);
67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
69 struct pci_controller *phb;
71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
74 spin_lock(&hose_spinlock);
75 phb->global_number = global_phb_number++;
76 list_add_tail(&phb->list_node, &hose_list);
77 spin_unlock(&hose_spinlock);
79 phb->is_dynamic = mem_init_done;
83 void pcibios_free_controller(struct pci_controller *phb)
85 spin_lock(&hose_spinlock);
86 list_del(&phb->list_node);
87 spin_unlock(&hose_spinlock);
93 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
95 return resource_size(&hose->io_resource);
98 int pcibios_vaddr_is_ioport(void __iomem *address)
101 struct pci_controller *hose;
102 resource_size_t size;
104 spin_lock(&hose_spinlock);
105 list_for_each_entry(hose, &hose_list, list_node) {
106 size = pcibios_io_size(hose);
107 if (address >= hose->io_base_virt &&
108 address < (hose->io_base_virt + size)) {
113 spin_unlock(&hose_spinlock);
117 unsigned long pci_address_to_pio(phys_addr_t address)
119 struct pci_controller *hose;
120 resource_size_t size;
121 unsigned long ret = ~0;
123 spin_lock(&hose_spinlock);
124 list_for_each_entry(hose, &hose_list, list_node) {
125 size = pcibios_io_size(hose);
126 if (address >= hose->io_base_phys &&
127 address < (hose->io_base_phys + size)) {
129 (unsigned long)hose->io_base_virt - _IO_BASE;
130 ret = base + (address - hose->io_base_phys);
134 spin_unlock(&hose_spinlock);
138 EXPORT_SYMBOL_GPL(pci_address_to_pio);
141 * Return the domain number for this bus.
143 int pci_domain_nr(struct pci_bus *bus)
145 struct pci_controller *hose = pci_bus_to_host(bus);
147 return hose->global_number;
149 EXPORT_SYMBOL(pci_domain_nr);
151 /* This routine is meant to be used early during boot, when the
152 * PCI bus numbers have not yet been assigned, and you need to
153 * issue PCI config cycles to an OF device.
154 * It could also be used to "fix" RTAS config cycles if you want
155 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
158 struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
161 struct pci_controller *hose, *tmp;
162 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
163 if (hose->dn == node)
170 static ssize_t pci_show_devspec(struct device *dev,
171 struct device_attribute *attr, char *buf)
173 struct pci_dev *pdev;
174 struct device_node *np;
176 pdev = to_pci_dev(dev);
177 np = pci_device_to_OF_node(pdev);
178 if (np == NULL || np->full_name == NULL)
180 return sprintf(buf, "%s", np->full_name);
182 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
184 /* Add sysfs properties */
185 int pcibios_add_platform_entries(struct pci_dev *pdev)
187 return device_create_file(&pdev->dev, &dev_attr_devspec);
190 void pcibios_set_master(struct pci_dev *dev)
192 /* No special bus mastering setup handling */
195 char __devinit *pcibios_setup(char *str)
201 * Reads the interrupt pin to determine if interrupt is use by card.
202 * If the interrupt is used, then gets the interrupt line from the
203 * openfirmware and sets it in the pci_dev and pci_config line.
205 int pci_read_irq_line(struct pci_dev *pci_dev)
210 /* The current device-tree that iSeries generates from the HV
211 * PCI informations doesn't contain proper interrupt routing,
212 * and all the fallback would do is print out crap, so we
213 * don't attempt to resolve the interrupts here at all, some
214 * iSeries specific fixup does it.
216 * In the long run, we will hopefully fix the generated device-tree
219 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
222 memset(&oirq, 0xff, sizeof(oirq));
224 /* Try to get a mapping from the device-tree */
225 if (of_irq_map_pci(pci_dev, &oirq)) {
228 /* If that fails, lets fallback to what is in the config
229 * space and map that through the default controller. We
230 * also set the type to level low since that's what PCI
231 * interrupts are. If your platform does differently, then
232 * either provide a proper interrupt tree or don't use this
235 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
239 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
240 line == 0xff || line == 0) {
243 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
246 virq = irq_create_mapping(NULL, line);
248 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
250 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
251 oirq.size, oirq.specifier[0], oirq.specifier[1],
252 of_node_full_name(oirq.controller));
254 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
258 pr_debug(" Failed to map !\n");
262 pr_debug(" Mapped to linux irq %d\n", virq);
268 EXPORT_SYMBOL(pci_read_irq_line);
271 * Platform support for /proc/bus/pci/X/Y mmap()s,
272 * modelled on the sparc64 implementation by Dave Miller.
277 * Adjust vm_pgoff of VMA such that it is the physical page offset
278 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
280 * Basically, the user finds the base address for his device which he wishes
281 * to mmap. They read the 32-bit value from the config space base register,
282 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
283 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
285 * Returns negative error code on failure, zero on success.
287 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
288 resource_size_t *offset,
289 enum pci_mmap_state mmap_state)
291 struct pci_controller *hose = pci_bus_to_host(dev->bus);
292 unsigned long io_offset = 0;
296 return NULL; /* should never happen */
298 /* If memory, add on the PCI bridge address offset */
299 if (mmap_state == pci_mmap_mem) {
300 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
301 *offset += hose->pci_mem_offset;
303 res_bit = IORESOURCE_MEM;
305 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
306 *offset += io_offset;
307 res_bit = IORESOURCE_IO;
311 * Check that the offset requested corresponds to one of the
312 * resources of the device.
314 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
315 struct resource *rp = &dev->resource[i];
316 int flags = rp->flags;
318 /* treat ROM as memory (should be already) */
319 if (i == PCI_ROM_RESOURCE)
320 flags |= IORESOURCE_MEM;
322 /* Active and same type? */
323 if ((flags & res_bit) == 0)
326 /* In the range of this resource? */
327 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
330 /* found it! construct the final physical address */
331 if (mmap_state == pci_mmap_io)
332 *offset += hose->io_base_phys - io_offset;
340 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
343 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
345 enum pci_mmap_state mmap_state,
348 pgprot_t prot = protection;
350 /* Write combine is always 0 on non-memory space mappings. On
351 * memory space, if the user didn't pass 1, we check for a
352 * "prefetchable" resource. This is a bit hackish, but we use
353 * this to workaround the inability of /sysfs to provide a write
356 if (mmap_state != pci_mmap_mem)
358 else if (write_combine == 0) {
359 if (rp->flags & IORESOURCE_PREFETCH)
363 return pgprot_noncached(prot);
367 * This one is used by /dev/mem and fbdev who have no clue about the
368 * PCI device, it tries to find the PCI device first and calls the
371 pgprot_t pci_phys_mem_access_prot(struct file *file,
376 struct pci_dev *pdev = NULL;
377 struct resource *found = NULL;
378 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
381 if (page_is_ram(pfn))
384 prot = pgprot_noncached(prot);
385 for_each_pci_dev(pdev) {
386 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
387 struct resource *rp = &pdev->resource[i];
388 int flags = rp->flags;
390 /* Active and same type? */
391 if ((flags & IORESOURCE_MEM) == 0)
393 /* In the range of this resource? */
394 if (offset < (rp->start & PAGE_MASK) ||
404 if (found->flags & IORESOURCE_PREFETCH)
405 prot = pgprot_noncached_wc(prot);
409 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
410 (unsigned long long)offset, pgprot_val(prot));
416 * Perform the actual remap of the pages for a PCI device mapping, as
417 * appropriate for this architecture. The region in the process to map
418 * is described by vm_start and vm_end members of VMA, the base physical
419 * address is found in vm_pgoff.
420 * The pci device structure is provided so that architectures may make mapping
421 * decisions on a per-device or per-bus basis.
423 * Returns a negative error code on failure, zero on success.
425 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
426 enum pci_mmap_state mmap_state, int write_combine)
428 resource_size_t offset =
429 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
433 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
437 vma->vm_pgoff = offset >> PAGE_SHIFT;
438 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
440 mmap_state, write_combine);
442 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
443 vma->vm_end - vma->vm_start, vma->vm_page_prot);
448 /* This provides legacy IO read access on a bus */
449 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
451 unsigned long offset;
452 struct pci_controller *hose = pci_bus_to_host(bus);
453 struct resource *rp = &hose->io_resource;
456 /* Check if port can be supported by that bus. We only check
457 * the ranges of the PHB though, not the bus itself as the rules
458 * for forwarding legacy cycles down bridges are not our problem
459 * here. So if the host bridge supports it, we do it.
461 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
464 if (!(rp->flags & IORESOURCE_IO))
466 if (offset < rp->start || (offset + size) > rp->end)
468 addr = hose->io_base_virt + port;
472 *((u8 *)val) = in_8(addr);
477 *((u16 *)val) = in_le16(addr);
482 *((u32 *)val) = in_le32(addr);
488 /* This provides legacy IO write access on a bus */
489 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
491 unsigned long offset;
492 struct pci_controller *hose = pci_bus_to_host(bus);
493 struct resource *rp = &hose->io_resource;
496 /* Check if port can be supported by that bus. We only check
497 * the ranges of the PHB though, not the bus itself as the rules
498 * for forwarding legacy cycles down bridges are not our problem
499 * here. So if the host bridge supports it, we do it.
501 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
504 if (!(rp->flags & IORESOURCE_IO))
506 if (offset < rp->start || (offset + size) > rp->end)
508 addr = hose->io_base_virt + port;
510 /* WARNING: The generic code is idiotic. It gets passed a pointer
511 * to what can be a 1, 2 or 4 byte quantity and always reads that
512 * as a u32, which means that we have to correct the location of
513 * the data read within those 32 bits for size 1 and 2
517 out_8(addr, val >> 24);
522 out_le16(addr, val >> 16);
533 /* This provides legacy IO or memory mmap access on a bus */
534 int pci_mmap_legacy_page_range(struct pci_bus *bus,
535 struct vm_area_struct *vma,
536 enum pci_mmap_state mmap_state)
538 struct pci_controller *hose = pci_bus_to_host(bus);
539 resource_size_t offset =
540 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
541 resource_size_t size = vma->vm_end - vma->vm_start;
544 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
545 pci_domain_nr(bus), bus->number,
546 mmap_state == pci_mmap_mem ? "MEM" : "IO",
547 (unsigned long long)offset,
548 (unsigned long long)(offset + size - 1));
550 if (mmap_state == pci_mmap_mem) {
553 * Because X is lame and can fail starting if it gets an error
554 * trying to mmap legacy_mem (instead of just moving on without
555 * legacy memory access) we fake it here by giving it anonymous
556 * memory, effectively behaving just like /dev/zero
558 if ((offset + size) > hose->isa_mem_size) {
561 "Process %s (pid:%d) mapped non-existing PCI"
562 "legacy memory for 0%04x:%02x\n",
563 current->comm, current->pid, pci_domain_nr(bus),
566 if (vma->vm_flags & VM_SHARED)
567 return shmem_zero_setup(vma);
570 offset += hose->isa_mem_phys;
572 unsigned long io_offset = (unsigned long)hose->io_base_virt - \
574 unsigned long roffset = offset + io_offset;
575 rp = &hose->io_resource;
576 if (!(rp->flags & IORESOURCE_IO))
578 if (roffset < rp->start || (roffset + size) > rp->end)
580 offset += hose->io_base_phys;
582 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
584 vma->vm_pgoff = offset >> PAGE_SHIFT;
585 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
586 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
587 vma->vm_end - vma->vm_start,
591 void pci_resource_to_user(const struct pci_dev *dev, int bar,
592 const struct resource *rsrc,
593 resource_size_t *start, resource_size_t *end)
595 struct pci_controller *hose = pci_bus_to_host(dev->bus);
596 resource_size_t offset = 0;
601 if (rsrc->flags & IORESOURCE_IO)
602 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
604 /* We pass a fully fixed up address to userland for MMIO instead of
605 * a BAR value because X is lame and expects to be able to use that
606 * to pass to /dev/mem !
608 * That means that we'll have potentially 64 bits values where some
609 * userland apps only expect 32 (like X itself since it thinks only
610 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
613 * Hopefully, the sysfs insterface is immune to that gunk. Once X
614 * has been fixed (and the fix spread enough), we can re-enable the
615 * 2 lines below and pass down a BAR value to userland. In that case
616 * we'll also have to re-enable the matching code in
617 * __pci_mmap_make_offset().
622 else if (rsrc->flags & IORESOURCE_MEM)
623 offset = hose->pci_mem_offset;
626 *start = rsrc->start - offset;
627 *end = rsrc->end - offset;
631 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
632 * @hose: newly allocated pci_controller to be setup
633 * @dev: device node of the host bridge
634 * @primary: set if primary bus (32 bits only, soon to be deprecated)
636 * This function will parse the "ranges" property of a PCI host bridge device
637 * node and setup the resource mapping of a pci controller based on its
640 * Life would be boring if it wasn't for a few issues that we have to deal
643 * - We can only cope with one IO space range and up to 3 Memory space
644 * ranges. However, some machines (thanks Apple !) tend to split their
645 * space into lots of small contiguous ranges. So we have to coalesce.
647 * - We can only cope with all memory ranges having the same offset
648 * between CPU addresses and PCI addresses. Unfortunately, some bridges
649 * are setup for a large 1:1 mapping along with a small "window" which
650 * maps PCI address 0 to some arbitrary high address of the CPU space in
651 * order to give access to the ISA memory hole.
652 * The way out of here that I've chosen for now is to always set the
653 * offset based on the first resource found, then override it if we
654 * have a different offset and the previous was set by an ISA hole.
656 * - Some busses have IO space not starting at 0, which causes trouble with
657 * the way we do our IO resource renumbering. The code somewhat deals with
658 * it for 64 bits but I would expect problems on 32 bits.
660 * - Some 32 bits platforms such as 4xx can have physical space larger than
661 * 32 bits so we need to use 64 bits values for the parsing
663 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
664 struct device_node *dev,
669 int pna = of_n_addr_cells(dev);
671 int memno = 0, isa_hole = -1;
673 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
674 unsigned long long isa_mb = 0;
675 struct resource *res;
677 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
678 dev->full_name, primary ? "(primary)" : "");
680 /* Get ranges property */
681 ranges = of_get_property(dev, "ranges", &rlen);
686 pr_debug("Parsing ranges property...\n");
687 while ((rlen -= np * 4) >= 0) {
688 /* Read next ranges element */
689 pci_space = ranges[0];
690 pci_addr = of_read_number(ranges + 1, 2);
691 cpu_addr = of_translate_address(dev, ranges + 3);
692 size = of_read_number(ranges + pna + 3, 2);
694 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx "
695 "cpu_addr:0x%016llx size:0x%016llx\n",
696 pci_space, pci_addr, cpu_addr, size);
700 /* If we failed translation or got a zero-sized region
701 * (some FW try to feed us with non sensical zero sized regions
702 * such as power3 which look like some kind of attempt
703 * at exposing the VGA memory hole)
705 if (cpu_addr == OF_BAD_ADDR || size == 0)
708 /* Now consume following elements while they are contiguous */
709 for (; rlen >= np * sizeof(u32);
710 ranges += np, rlen -= np * 4) {
711 if (ranges[0] != pci_space)
713 pci_next = of_read_number(ranges + 1, 2);
714 cpu_next = of_translate_address(dev, ranges + 3);
715 if (pci_next != pci_addr + size ||
716 cpu_next != cpu_addr + size)
718 size += of_read_number(ranges + pna + 3, 2);
721 /* Act based on address space type */
723 switch ((pci_space >> 24) & 0x3) {
724 case 1: /* PCI IO space */
726 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
727 cpu_addr, cpu_addr + size - 1, pci_addr);
729 /* We support only one IO range */
730 if (hose->pci_io_size) {
732 " \\--> Skipped (too many) !\n");
735 /* On 32 bits, limit I/O space to 16MB */
736 if (size > 0x01000000)
739 /* 32 bits needs to map IOs here */
740 hose->io_base_virt = ioremap(cpu_addr, size);
742 /* Expect trouble if pci_addr is not 0 */
745 (unsigned long)hose->io_base_virt;
746 /* pci_io_size and io_base_phys always represent IO
747 * space starting at 0 so we factor in pci_addr
749 hose->pci_io_size = pci_addr + size;
750 hose->io_base_phys = cpu_addr - pci_addr;
753 res = &hose->io_resource;
754 res->flags = IORESOURCE_IO;
755 res->start = pci_addr;
757 case 2: /* PCI Memory space */
758 case 3: /* PCI 64 bits Memory space */
760 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
761 cpu_addr, cpu_addr + size - 1, pci_addr,
762 (pci_space & 0x40000000) ? "Prefetch" : "");
764 /* We support only 3 memory ranges */
767 " \\--> Skipped (too many) !\n");
770 /* Handles ISA memory hole space here */
774 if (primary || isa_mem_base == 0)
775 isa_mem_base = cpu_addr;
776 hose->isa_mem_phys = cpu_addr;
777 hose->isa_mem_size = size;
780 /* We get the PCI/Mem offset from the first range or
781 * the, current one if the offset came from an ISA
782 * hole. If they don't match, bugger.
785 (isa_hole >= 0 && pci_addr != 0 &&
786 hose->pci_mem_offset == isa_mb))
787 hose->pci_mem_offset = cpu_addr - pci_addr;
788 else if (pci_addr != 0 &&
789 hose->pci_mem_offset != cpu_addr - pci_addr) {
791 " \\--> Skipped (offset mismatch) !\n");
796 res = &hose->mem_resources[memno++];
797 res->flags = IORESOURCE_MEM;
798 if (pci_space & 0x40000000)
799 res->flags |= IORESOURCE_PREFETCH;
800 res->start = cpu_addr;
804 res->name = dev->full_name;
805 res->end = res->start + size - 1;
812 /* If there's an ISA hole and the pci_mem_offset is -not- matching
813 * the ISA hole offset, then we need to remove the ISA hole from
814 * the resource list for that brige
816 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
817 unsigned int next = isa_hole + 1;
818 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
820 memmove(&hose->mem_resources[isa_hole],
821 &hose->mem_resources[next],
822 sizeof(struct resource) * (memno - next));
823 hose->mem_resources[--memno].flags = 0;
827 /* Decide whether to display the domain number in /proc */
828 int pci_proc_domain(struct pci_bus *bus)
830 struct pci_controller *hose = pci_bus_to_host(bus);
835 /* This header fixup will do the resource fixup for all devices as they are
836 * probed, but not for bridge ranges
838 static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
840 struct pci_controller *hose = pci_bus_to_host(dev->bus);
844 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
848 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
849 struct resource *res = dev->resource + i;
852 if (res->start == 0) {
853 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]" \
856 (unsigned long long)res->start,
857 (unsigned long long)res->end,
858 (unsigned int)res->flags);
859 res->end -= res->start;
861 res->flags |= IORESOURCE_UNSET;
865 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
867 (unsigned long long)res->start,\
868 (unsigned long long)res->end,
869 (unsigned int)res->flags);
872 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
874 /* This function tries to figure out if a bridge resource has been initialized
875 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
876 * things go more smoothly when it gets it right. It should covers cases such
877 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
879 static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
880 struct resource *res)
882 struct pci_controller *hose = pci_bus_to_host(bus);
883 struct pci_dev *dev = bus->self;
884 resource_size_t offset;
888 /* Job is a bit different between memory and IO */
889 if (res->flags & IORESOURCE_MEM) {
890 /* If the BAR is non-0 (res != pci_mem_offset) then it's
891 * probably been initialized by somebody
893 if (res->start != hose->pci_mem_offset)
896 /* The BAR is 0, let's check if memory decoding is enabled on
897 * the bridge. If not, we consider it unassigned
899 pci_read_config_word(dev, PCI_COMMAND, &command);
900 if ((command & PCI_COMMAND_MEMORY) == 0)
903 /* Memory decoding is enabled and the BAR is 0. If any of
904 * the bridge resources covers that starting address (0 then
905 * it's good enough for us for memory
907 for (i = 0; i < 3; i++) {
908 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
909 hose->mem_resources[i].start == hose->pci_mem_offset)
913 /* Well, it starts at 0 and we know it will collide so we may as
914 * well consider it as unassigned. That covers the Apple case.
918 /* If the BAR is non-0, then we consider it assigned */
919 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
920 if (((res->start - offset) & 0xfffffffful) != 0)
923 /* Here, we are a bit different than memory as typically IO
924 * space starting at low addresses -is- valid. What we do
925 * instead if that we consider as unassigned anything that
926 * doesn't have IO enabled in the PCI command register,
929 pci_read_config_word(dev, PCI_COMMAND, &command);
930 if (command & PCI_COMMAND_IO)
933 /* It's starting at 0 and IO is disabled in the bridge, consider
940 /* Fixup resources of a PCI<->PCI bridge */
941 static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
943 struct resource *res;
946 struct pci_dev *dev = bus->self;
948 pci_bus_for_each_resource(bus, res, i) {
953 if (i >= 3 && bus->self->transparent)
956 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
958 (unsigned long long)res->start,\
959 (unsigned long long)res->end,
960 (unsigned int)res->flags);
962 /* Try to detect uninitialized P2P bridge resources,
963 * and clear them out so they get re-assigned later
965 if (pcibios_uninitialized_bridge_resource(bus, res)) {
967 pr_debug("PCI:%s (unassigned)\n",
970 pr_debug("PCI:%s %016llx-%016llx\n",
972 (unsigned long long)res->start,
973 (unsigned long long)res->end);
978 void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
980 /* Fix up the bus resources for P2P bridges */
981 if (bus->self != NULL)
982 pcibios_fixup_bridge(bus);
985 void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
989 pr_debug("PCI: Fixup bus devices %d (%s)\n",
990 bus->number, bus->self ? pci_name(bus->self) : "PHB");
992 list_for_each_entry(dev, &bus->devices, bus_list) {
993 /* Setup OF node pointer in archdata */
994 dev->dev.of_node = pci_device_to_OF_node(dev);
996 /* Fixup NUMA node as it may not be setup yet by the generic
997 * code and is needed by the DMA init
999 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1001 /* Hook up default DMA ops */
1002 set_dma_ops(&dev->dev, pci_dma_ops);
1003 dev->dev.archdata.dma_data = (void *)PCI_DRAM_OFFSET;
1005 /* Read default IRQs and fixup if necessary */
1006 pci_read_irq_line(dev);
1010 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1012 /* When called from the generic PCI probe, read PCI<->PCI bridge
1013 * bases. This is -not- called when generating the PCI tree from
1014 * the OF device-tree.
1016 if (bus->self != NULL)
1017 pci_read_bridge_bases(bus);
1019 /* Now fixup the bus bus */
1020 pcibios_setup_bus_self(bus);
1022 /* Now fixup devices on that bus */
1023 pcibios_setup_bus_devices(bus);
1025 EXPORT_SYMBOL(pcibios_fixup_bus);
1027 static int skip_isa_ioresource_align(struct pci_dev *dev)
1033 * We need to avoid collisions with `mirrored' VGA ports
1034 * and other strange ISA hardware, so we always want the
1035 * addresses to be allocated in the 0x000-0x0ff region
1038 * Why? Because some silly external IO cards only decode
1039 * the low 10 bits of the IO address. The 0x00-0xff region
1040 * is reserved for motherboard devices that decode all 16
1041 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1042 * but we want to try to avoid allocating at 0x2900-0x2bff
1043 * which might have be mirrored at 0x0100-0x03ff..
1045 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1046 resource_size_t size, resource_size_t align)
1048 struct pci_dev *dev = data;
1049 resource_size_t start = res->start;
1051 if (res->flags & IORESOURCE_IO) {
1052 if (skip_isa_ioresource_align(dev))
1055 start = (start + 0x3ff) & ~0x3ff;
1060 EXPORT_SYMBOL(pcibios_align_resource);
1063 * Reparent resource children of pr that conflict with res
1064 * under res, and make res replace those children.
1066 static int __init reparent_resources(struct resource *parent,
1067 struct resource *res)
1069 struct resource *p, **pp;
1070 struct resource **firstpp = NULL;
1072 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1073 if (p->end < res->start)
1075 if (res->end < p->start)
1077 if (p->start < res->start || p->end > res->end)
1078 return -1; /* not completely contained */
1079 if (firstpp == NULL)
1082 if (firstpp == NULL)
1083 return -1; /* didn't find any conflicting entries? */
1084 res->parent = parent;
1085 res->child = *firstpp;
1089 for (p = res->child; p != NULL; p = p->sibling) {
1091 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1093 (unsigned long long)p->start,
1094 (unsigned long long)p->end, res->name);
1100 * Handle resources of PCI devices. If the world were perfect, we could
1101 * just allocate all the resource regions and do nothing more. It isn't.
1102 * On the other hand, we cannot just re-allocate all devices, as it would
1103 * require us to know lots of host bridge internals. So we attempt to
1104 * keep as much of the original configuration as possible, but tweak it
1105 * when it's found to be wrong.
1107 * Known BIOS problems we have to work around:
1108 * - I/O or memory regions not configured
1109 * - regions configured, but not enabled in the command register
1110 * - bogus I/O addresses above 64K used
1111 * - expansion ROMs left enabled (this may sound harmless, but given
1112 * the fact the PCI specs explicitly allow address decoders to be
1113 * shared between expansion ROMs and other resource regions, it's
1114 * at least dangerous)
1117 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1118 * This gives us fixed barriers on where we can allocate.
1119 * (2) Allocate resources for all enabled devices. If there is
1120 * a collision, just mark the resource as unallocated. Also
1121 * disable expansion ROMs during this step.
1122 * (3) Try to allocate resources for disabled devices. If the
1123 * resources were assigned correctly, everything goes well,
1124 * if they weren't, they won't disturb allocation of other
1126 * (4) Assign new addresses to resources which were either
1127 * not configured at all or misconfigured. If explicitly
1128 * requested by the user, configure expansion ROM address
1132 void pcibios_allocate_bus_resources(struct pci_bus *bus)
1136 struct resource *res, *pr;
1138 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1139 pci_domain_nr(bus), bus->number);
1141 pci_bus_for_each_resource(bus, res, i) {
1142 if (!res || !res->flags
1143 || res->start > res->end || res->parent)
1145 if (bus->parent == NULL)
1146 pr = (res->flags & IORESOURCE_IO) ?
1147 &ioport_resource : &iomem_resource;
1149 /* Don't bother with non-root busses when
1150 * re-assigning all resources. We clear the
1151 * resource flags as if they were colliding
1152 * and as such ensure proper re-allocation
1155 pr = pci_find_parent_resource(bus->self, res);
1157 /* this happens when the generic PCI
1158 * code (wrongly) decides that this
1159 * bridge is transparent -- paulus
1165 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1166 "[0x%x], parent %p (%s)\n",
1167 bus->self ? pci_name(bus->self) : "PHB",
1169 (unsigned long long)res->start,
1170 (unsigned long long)res->end,
1171 (unsigned int)res->flags,
1172 pr, (pr && pr->name) ? pr->name : "nil");
1174 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1175 if (request_resource(pr, res) == 0)
1178 * Must be a conflict with an existing entry.
1179 * Move that entry (or entries) under the
1180 * bridge resource and try again.
1182 if (reparent_resources(pr, res) == 0)
1185 printk(KERN_WARNING "PCI: Cannot allocate resource region "
1186 "%d of PCI bridge %d, will remap\n", i, bus->number);
1188 res->start = res->end = 0;
1192 list_for_each_entry(b, &bus->children, node)
1193 pcibios_allocate_bus_resources(b);
1196 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
1198 struct resource *pr, *r = &dev->resource[idx];
1200 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1202 (unsigned long long)r->start,
1203 (unsigned long long)r->end,
1204 (unsigned int)r->flags);
1206 pr = pci_find_parent_resource(dev, r);
1207 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1208 request_resource(pr, r) < 0) {
1209 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1210 " of device %s, will remap\n", idx, pci_name(dev));
1212 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1214 (unsigned long long)pr->start,
1215 (unsigned long long)pr->end,
1216 (unsigned int)pr->flags);
1217 /* We'll assign a new address later */
1218 r->flags |= IORESOURCE_UNSET;
1224 static void __init pcibios_allocate_resources(int pass)
1226 struct pci_dev *dev = NULL;
1231 for_each_pci_dev(dev) {
1232 pci_read_config_word(dev, PCI_COMMAND, &command);
1233 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1234 r = &dev->resource[idx];
1235 if (r->parent) /* Already allocated */
1237 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1238 continue; /* Not assigned at all */
1239 /* We only allocate ROMs on pass 1 just in case they
1240 * have been screwed up by firmware
1242 if (idx == PCI_ROM_RESOURCE)
1244 if (r->flags & IORESOURCE_IO)
1245 disabled = !(command & PCI_COMMAND_IO);
1247 disabled = !(command & PCI_COMMAND_MEMORY);
1248 if (pass == disabled)
1249 alloc_resource(dev, idx);
1253 r = &dev->resource[PCI_ROM_RESOURCE];
1255 /* Turn the ROM off, leave the resource region,
1256 * but keep it unregistered.
1259 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1260 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1261 pr_debug("PCI: Switching off ROM of %s\n",
1263 r->flags &= ~IORESOURCE_ROM_ENABLE;
1264 pci_write_config_dword(dev, dev->rom_base_reg,
1265 reg & ~PCI_ROM_ADDRESS_ENABLE);
1271 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1273 struct pci_controller *hose = pci_bus_to_host(bus);
1274 resource_size_t offset;
1275 struct resource *res, *pres;
1278 pr_debug("Reserving legacy ranges for domain %04x\n",
1279 pci_domain_nr(bus));
1282 if (!(hose->io_resource.flags & IORESOURCE_IO))
1284 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1285 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1286 BUG_ON(res == NULL);
1287 res->name = "Legacy IO";
1288 res->flags = IORESOURCE_IO;
1289 res->start = offset;
1290 res->end = (offset + 0xfff) & 0xfffffffful;
1291 pr_debug("Candidate legacy IO: %pR\n", res);
1292 if (request_resource(&hose->io_resource, res)) {
1294 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1295 pci_domain_nr(bus), bus->number, res);
1300 /* Check for memory */
1301 offset = hose->pci_mem_offset;
1302 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1303 for (i = 0; i < 3; i++) {
1304 pres = &hose->mem_resources[i];
1305 if (!(pres->flags & IORESOURCE_MEM))
1307 pr_debug("hose mem res: %pR\n", pres);
1308 if ((pres->start - offset) <= 0xa0000 &&
1309 (pres->end - offset) >= 0xbffff)
1314 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1315 BUG_ON(res == NULL);
1316 res->name = "Legacy VGA memory";
1317 res->flags = IORESOURCE_MEM;
1318 res->start = 0xa0000 + offset;
1319 res->end = 0xbffff + offset;
1320 pr_debug("Candidate VGA memory: %pR\n", res);
1321 if (request_resource(pres, res)) {
1323 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1324 pci_domain_nr(bus), bus->number, res);
1329 void __init pcibios_resource_survey(void)
1333 /* Allocate and assign resources. If we re-assign everything, then
1334 * we skip the allocate phase
1336 list_for_each_entry(b, &pci_root_buses, node)
1337 pcibios_allocate_bus_resources(b);
1339 pcibios_allocate_resources(0);
1340 pcibios_allocate_resources(1);
1342 /* Before we start assigning unassigned resource, we try to reserve
1343 * the low IO area and the VGA memory area if they intersect the
1344 * bus available resources to avoid allocating things on top of them
1346 list_for_each_entry(b, &pci_root_buses, node)
1347 pcibios_reserve_legacy_regions(b);
1349 /* Now proceed to assigning things that were left unassigned */
1350 pr_debug("PCI: Assigning unassigned resources...\n");
1351 pci_assign_unassigned_resources();
1354 #ifdef CONFIG_HOTPLUG
1356 /* This is used by the PCI hotplug driver to allocate resource
1357 * of newly plugged busses. We can try to consolidate with the
1358 * rest of the code later, for now, keep it as-is as our main
1359 * resource allocation function doesn't deal with sub-trees yet.
1361 void __devinit pcibios_claim_one_bus(struct pci_bus *bus)
1363 struct pci_dev *dev;
1364 struct pci_bus *child_bus;
1366 list_for_each_entry(dev, &bus->devices, bus_list) {
1369 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1370 struct resource *r = &dev->resource[i];
1372 if (r->parent || !r->start || !r->flags)
1375 pr_debug("PCI: Claiming %s: "
1376 "Resource %d: %016llx..%016llx [%x]\n",
1378 (unsigned long long)r->start,
1379 (unsigned long long)r->end,
1380 (unsigned int)r->flags);
1382 pci_claim_resource(dev, i);
1386 list_for_each_entry(child_bus, &bus->children, node)
1387 pcibios_claim_one_bus(child_bus);
1389 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1392 /* pcibios_finish_adding_to_bus
1394 * This is to be called by the hotplug code after devices have been
1395 * added to a bus, this include calling it for a PHB that is just
1398 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1400 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1401 pci_domain_nr(bus), bus->number);
1403 /* Allocate bus and devices resources */
1404 pcibios_allocate_bus_resources(bus);
1405 pcibios_claim_one_bus(bus);
1407 /* Add new devices to global lists. Register in proc, sysfs. */
1408 pci_bus_add_devices(bus);
1411 /* eeh_add_device_tree_late(bus); */
1413 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1415 #endif /* CONFIG_HOTPLUG */
1417 int pcibios_enable_device(struct pci_dev *dev, int mask)
1419 return pci_enable_resources(dev, mask);
1422 static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, struct list_head *resources)
1424 unsigned long io_offset;
1425 struct resource *res;
1428 /* Hookup PHB IO resource */
1429 res = &hose->io_resource;
1431 /* Fixup IO space offset */
1432 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1433 res->start = (res->start + io_offset) & 0xffffffffu;
1434 res->end = (res->end + io_offset) & 0xffffffffu;
1437 printk(KERN_WARNING "PCI: I/O resource not set for host"
1438 " bridge %s (domain %d)\n",
1439 hose->dn->full_name, hose->global_number);
1440 /* Workaround for lack of IO resource only on 32-bit */
1441 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1442 res->end = res->start + IO_SPACE_LIMIT;
1443 res->flags = IORESOURCE_IO;
1445 pci_add_resource_offset(resources, res, hose->io_base_virt - _IO_BASE);
1447 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1448 (unsigned long long)res->start,
1449 (unsigned long long)res->end,
1450 (unsigned long)res->flags);
1452 /* Hookup PHB Memory resources */
1453 for (i = 0; i < 3; ++i) {
1454 res = &hose->mem_resources[i];
1458 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1459 "host bridge %s (domain %d)\n",
1460 hose->dn->full_name, hose->global_number);
1462 /* Workaround for lack of MEM resource only on 32-bit */
1463 res->start = hose->pci_mem_offset;
1464 res->end = (resource_size_t)-1LL;
1465 res->flags = IORESOURCE_MEM;
1468 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1470 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1471 i, (unsigned long long)res->start,
1472 (unsigned long long)res->end,
1473 (unsigned long)res->flags);
1476 pr_debug("PCI: PHB MEM offset = %016llx\n",
1477 (unsigned long long)hose->pci_mem_offset);
1478 pr_debug("PCI: PHB IO offset = %08lx\n",
1479 (unsigned long)hose->io_base_virt - _IO_BASE);
1482 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1484 struct pci_controller *hose = bus->sysdata;
1486 return of_node_get(hose->dn);
1489 static void __devinit pcibios_scan_phb(struct pci_controller *hose)
1491 LIST_HEAD(resources);
1492 struct pci_bus *bus;
1493 struct device_node *node = hose->dn;
1495 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1497 pcibios_setup_phb_resources(hose, &resources);
1499 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1500 hose->ops, hose, &resources);
1502 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
1503 hose->global_number);
1504 pci_free_resource_list(&resources);
1507 bus->secondary = hose->first_busno;
1510 hose->last_busno = bus->subordinate;
1513 static int __init pcibios_init(void)
1515 struct pci_controller *hose, *tmp;
1518 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1520 /* Scan all of the recorded PCI controllers. */
1521 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1522 hose->last_busno = 0xff;
1523 pcibios_scan_phb(hose);
1524 if (next_busno <= hose->last_busno)
1525 next_busno = hose->last_busno + 1;
1527 pci_bus_count = next_busno;
1529 /* Call common code to handle resource allocation */
1530 pcibios_resource_survey();
1535 subsys_initcall(pcibios_init);
1537 static struct pci_controller *pci_bus_to_hose(int bus)
1539 struct pci_controller *hose, *tmp;
1541 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1542 if (bus >= hose->first_busno && bus <= hose->last_busno)
1547 /* Provide information on locations of various I/O regions in physical
1548 * memory. Do this on a per-card basis so that we choose the right
1550 * Note that the returned IO or memory base is a physical address
1553 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1555 struct pci_controller *hose;
1556 long result = -EOPNOTSUPP;
1558 hose = pci_bus_to_hose(bus);
1563 case IOBASE_BRIDGE_NUMBER:
1564 return (long)hose->first_busno;
1566 return (long)hose->pci_mem_offset;
1568 return (long)hose->io_base_phys;
1570 return (long)isa_io_base;
1571 case IOBASE_ISA_MEM:
1572 return (long)isa_mem_base;
1579 * Null PCI config access functions, for the case when we can't
1582 #define NULL_PCI_OP(rw, size, type) \
1584 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1586 return PCIBIOS_DEVICE_NOT_FOUND; \
1590 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1593 return PCIBIOS_DEVICE_NOT_FOUND;
1597 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1600 return PCIBIOS_DEVICE_NOT_FOUND;
1603 static struct pci_ops null_pci_ops = {
1604 .read = null_read_config,
1605 .write = null_write_config,
1609 * These functions are used early on before PCI scanning is done
1610 * and all of the pci_dev and pci_bus structures have been created.
1612 static struct pci_bus *
1613 fake_pci_bus(struct pci_controller *hose, int busnr)
1615 static struct pci_bus bus;
1618 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1622 bus.ops = hose ? hose->ops : &null_pci_ops;
1626 #define EARLY_PCI_OP(rw, size, type) \
1627 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1628 int devfn, int offset, type value) \
1630 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1631 devfn, offset, value); \
1634 EARLY_PCI_OP(read, byte, u8 *)
1635 EARLY_PCI_OP(read, word, u16 *)
1636 EARLY_PCI_OP(read, dword, u32 *)
1637 EARLY_PCI_OP(write, byte, u8)
1638 EARLY_PCI_OP(write, word, u16)
1639 EARLY_PCI_OP(write, dword, u32)
1641 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1644 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);