2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
31 #include <linux/of_address.h>
32 #include <linux/of_pci.h>
33 #include <linux/export.h>
35 #include <asm/processor.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/byteorder.h>
40 static DEFINE_SPINLOCK(hose_spinlock);
43 /* XXX kill that some day ... */
44 static int global_phb_number; /* Global phb counter */
46 /* ISA Memory physical address */
47 resource_size_t isa_mem_base;
49 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
51 unsigned long isa_io_base;
52 unsigned long pci_dram_offset;
53 static int pci_bus_count;
56 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
58 pci_dma_ops = dma_ops;
61 struct dma_map_ops *get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops);
67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
69 struct pci_controller *phb;
71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
74 spin_lock(&hose_spinlock);
75 phb->global_number = global_phb_number++;
76 list_add_tail(&phb->list_node, &hose_list);
77 spin_unlock(&hose_spinlock);
79 phb->is_dynamic = mem_init_done;
83 void pcibios_free_controller(struct pci_controller *phb)
85 spin_lock(&hose_spinlock);
86 list_del(&phb->list_node);
87 spin_unlock(&hose_spinlock);
93 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
95 return resource_size(&hose->io_resource);
98 int pcibios_vaddr_is_ioport(void __iomem *address)
101 struct pci_controller *hose;
102 resource_size_t size;
104 spin_lock(&hose_spinlock);
105 list_for_each_entry(hose, &hose_list, list_node) {
106 size = pcibios_io_size(hose);
107 if (address >= hose->io_base_virt &&
108 address < (hose->io_base_virt + size)) {
113 spin_unlock(&hose_spinlock);
117 unsigned long pci_address_to_pio(phys_addr_t address)
119 struct pci_controller *hose;
120 resource_size_t size;
121 unsigned long ret = ~0;
123 spin_lock(&hose_spinlock);
124 list_for_each_entry(hose, &hose_list, list_node) {
125 size = pcibios_io_size(hose);
126 if (address >= hose->io_base_phys &&
127 address < (hose->io_base_phys + size)) {
129 (unsigned long)hose->io_base_virt - _IO_BASE;
130 ret = base + (address - hose->io_base_phys);
134 spin_unlock(&hose_spinlock);
138 EXPORT_SYMBOL_GPL(pci_address_to_pio);
141 * Return the domain number for this bus.
143 int pci_domain_nr(struct pci_bus *bus)
145 struct pci_controller *hose = pci_bus_to_host(bus);
147 return hose->global_number;
149 EXPORT_SYMBOL(pci_domain_nr);
151 /* This routine is meant to be used early during boot, when the
152 * PCI bus numbers have not yet been assigned, and you need to
153 * issue PCI config cycles to an OF device.
154 * It could also be used to "fix" RTAS config cycles if you want
155 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
158 struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
161 struct pci_controller *hose, *tmp;
162 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
163 if (hose->dn == node)
170 static ssize_t pci_show_devspec(struct device *dev,
171 struct device_attribute *attr, char *buf)
173 struct pci_dev *pdev;
174 struct device_node *np;
176 pdev = to_pci_dev(dev);
177 np = pci_device_to_OF_node(pdev);
178 if (np == NULL || np->full_name == NULL)
180 return sprintf(buf, "%s", np->full_name);
182 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
184 /* Add sysfs properties */
185 int pcibios_add_platform_entries(struct pci_dev *pdev)
187 return device_create_file(&pdev->dev, &dev_attr_devspec);
190 void pcibios_set_master(struct pci_dev *dev)
192 /* No special bus mastering setup handling */
196 * Reads the interrupt pin to determine if interrupt is use by card.
197 * If the interrupt is used, then gets the interrupt line from the
198 * openfirmware and sets it in the pci_dev and pci_config line.
200 int pci_read_irq_line(struct pci_dev *pci_dev)
202 struct of_phandle_args oirq;
205 /* The current device-tree that iSeries generates from the HV
206 * PCI informations doesn't contain proper interrupt routing,
207 * and all the fallback would do is print out crap, so we
208 * don't attempt to resolve the interrupts here at all, some
209 * iSeries specific fixup does it.
211 * In the long run, we will hopefully fix the generated device-tree
214 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
217 memset(&oirq, 0xff, sizeof(oirq));
219 /* Try to get a mapping from the device-tree */
220 if (of_irq_parse_pci(pci_dev, &oirq)) {
223 /* If that fails, lets fallback to what is in the config
224 * space and map that through the default controller. We
225 * also set the type to level low since that's what PCI
226 * interrupts are. If your platform does differently, then
227 * either provide a proper interrupt tree or don't use this
230 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
234 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
235 line == 0xff || line == 0) {
238 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
241 virq = irq_create_mapping(NULL, line);
243 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
245 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
246 oirq.args_count, oirq.args[0], oirq.args[1],
247 of_node_full_name(oirq.np));
249 virq = irq_create_of_mapping(&oirq);
252 pr_debug(" Failed to map !\n");
256 pr_debug(" Mapped to linux irq %d\n", virq);
262 EXPORT_SYMBOL(pci_read_irq_line);
265 * Platform support for /proc/bus/pci/X/Y mmap()s,
266 * modelled on the sparc64 implementation by Dave Miller.
271 * Adjust vm_pgoff of VMA such that it is the physical page offset
272 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
274 * Basically, the user finds the base address for his device which he wishes
275 * to mmap. They read the 32-bit value from the config space base register,
276 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
277 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
279 * Returns negative error code on failure, zero on success.
281 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
282 resource_size_t *offset,
283 enum pci_mmap_state mmap_state)
285 struct pci_controller *hose = pci_bus_to_host(dev->bus);
286 unsigned long io_offset = 0;
290 return NULL; /* should never happen */
292 /* If memory, add on the PCI bridge address offset */
293 if (mmap_state == pci_mmap_mem) {
294 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
295 *offset += hose->pci_mem_offset;
297 res_bit = IORESOURCE_MEM;
299 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
300 *offset += io_offset;
301 res_bit = IORESOURCE_IO;
305 * Check that the offset requested corresponds to one of the
306 * resources of the device.
308 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
309 struct resource *rp = &dev->resource[i];
310 int flags = rp->flags;
312 /* treat ROM as memory (should be already) */
313 if (i == PCI_ROM_RESOURCE)
314 flags |= IORESOURCE_MEM;
316 /* Active and same type? */
317 if ((flags & res_bit) == 0)
320 /* In the range of this resource? */
321 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
324 /* found it! construct the final physical address */
325 if (mmap_state == pci_mmap_io)
326 *offset += hose->io_base_phys - io_offset;
334 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
337 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
339 enum pci_mmap_state mmap_state,
342 pgprot_t prot = protection;
344 /* Write combine is always 0 on non-memory space mappings. On
345 * memory space, if the user didn't pass 1, we check for a
346 * "prefetchable" resource. This is a bit hackish, but we use
347 * this to workaround the inability of /sysfs to provide a write
350 if (mmap_state != pci_mmap_mem)
352 else if (write_combine == 0) {
353 if (rp->flags & IORESOURCE_PREFETCH)
357 return pgprot_noncached(prot);
361 * This one is used by /dev/mem and fbdev who have no clue about the
362 * PCI device, it tries to find the PCI device first and calls the
365 pgprot_t pci_phys_mem_access_prot(struct file *file,
370 struct pci_dev *pdev = NULL;
371 struct resource *found = NULL;
372 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
375 if (page_is_ram(pfn))
378 prot = pgprot_noncached(prot);
379 for_each_pci_dev(pdev) {
380 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
381 struct resource *rp = &pdev->resource[i];
382 int flags = rp->flags;
384 /* Active and same type? */
385 if ((flags & IORESOURCE_MEM) == 0)
387 /* In the range of this resource? */
388 if (offset < (rp->start & PAGE_MASK) ||
398 if (found->flags & IORESOURCE_PREFETCH)
399 prot = pgprot_noncached_wc(prot);
403 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
404 (unsigned long long)offset, pgprot_val(prot));
410 * Perform the actual remap of the pages for a PCI device mapping, as
411 * appropriate for this architecture. The region in the process to map
412 * is described by vm_start and vm_end members of VMA, the base physical
413 * address is found in vm_pgoff.
414 * The pci device structure is provided so that architectures may make mapping
415 * decisions on a per-device or per-bus basis.
417 * Returns a negative error code on failure, zero on success.
419 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
420 enum pci_mmap_state mmap_state, int write_combine)
422 resource_size_t offset =
423 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
427 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
431 vma->vm_pgoff = offset >> PAGE_SHIFT;
432 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
434 mmap_state, write_combine);
436 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
437 vma->vm_end - vma->vm_start, vma->vm_page_prot);
442 /* This provides legacy IO read access on a bus */
443 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
445 unsigned long offset;
446 struct pci_controller *hose = pci_bus_to_host(bus);
447 struct resource *rp = &hose->io_resource;
450 /* Check if port can be supported by that bus. We only check
451 * the ranges of the PHB though, not the bus itself as the rules
452 * for forwarding legacy cycles down bridges are not our problem
453 * here. So if the host bridge supports it, we do it.
455 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
458 if (!(rp->flags & IORESOURCE_IO))
460 if (offset < rp->start || (offset + size) > rp->end)
462 addr = hose->io_base_virt + port;
466 *((u8 *)val) = in_8(addr);
471 *((u16 *)val) = in_le16(addr);
476 *((u32 *)val) = in_le32(addr);
482 /* This provides legacy IO write access on a bus */
483 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
485 unsigned long offset;
486 struct pci_controller *hose = pci_bus_to_host(bus);
487 struct resource *rp = &hose->io_resource;
490 /* Check if port can be supported by that bus. We only check
491 * the ranges of the PHB though, not the bus itself as the rules
492 * for forwarding legacy cycles down bridges are not our problem
493 * here. So if the host bridge supports it, we do it.
495 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
498 if (!(rp->flags & IORESOURCE_IO))
500 if (offset < rp->start || (offset + size) > rp->end)
502 addr = hose->io_base_virt + port;
504 /* WARNING: The generic code is idiotic. It gets passed a pointer
505 * to what can be a 1, 2 or 4 byte quantity and always reads that
506 * as a u32, which means that we have to correct the location of
507 * the data read within those 32 bits for size 1 and 2
511 out_8(addr, val >> 24);
516 out_le16(addr, val >> 16);
527 /* This provides legacy IO or memory mmap access on a bus */
528 int pci_mmap_legacy_page_range(struct pci_bus *bus,
529 struct vm_area_struct *vma,
530 enum pci_mmap_state mmap_state)
532 struct pci_controller *hose = pci_bus_to_host(bus);
533 resource_size_t offset =
534 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
535 resource_size_t size = vma->vm_end - vma->vm_start;
538 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
539 pci_domain_nr(bus), bus->number,
540 mmap_state == pci_mmap_mem ? "MEM" : "IO",
541 (unsigned long long)offset,
542 (unsigned long long)(offset + size - 1));
544 if (mmap_state == pci_mmap_mem) {
547 * Because X is lame and can fail starting if it gets an error
548 * trying to mmap legacy_mem (instead of just moving on without
549 * legacy memory access) we fake it here by giving it anonymous
550 * memory, effectively behaving just like /dev/zero
552 if ((offset + size) > hose->isa_mem_size) {
554 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
555 current->comm, current->pid);
556 pr_debug("legacy memory for 0%04x:%02x\n",
557 pci_domain_nr(bus), bus->number);
559 if (vma->vm_flags & VM_SHARED)
560 return shmem_zero_setup(vma);
563 offset += hose->isa_mem_phys;
565 unsigned long io_offset = (unsigned long)hose->io_base_virt -
567 unsigned long roffset = offset + io_offset;
568 rp = &hose->io_resource;
569 if (!(rp->flags & IORESOURCE_IO))
571 if (roffset < rp->start || (roffset + size) > rp->end)
573 offset += hose->io_base_phys;
575 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
577 vma->vm_pgoff = offset >> PAGE_SHIFT;
578 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
579 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
580 vma->vm_end - vma->vm_start,
584 void pci_resource_to_user(const struct pci_dev *dev, int bar,
585 const struct resource *rsrc,
586 resource_size_t *start, resource_size_t *end)
588 struct pci_controller *hose = pci_bus_to_host(dev->bus);
589 resource_size_t offset = 0;
594 if (rsrc->flags & IORESOURCE_IO)
595 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
597 /* We pass a fully fixed up address to userland for MMIO instead of
598 * a BAR value because X is lame and expects to be able to use that
599 * to pass to /dev/mem !
601 * That means that we'll have potentially 64 bits values where some
602 * userland apps only expect 32 (like X itself since it thinks only
603 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
606 * Hopefully, the sysfs insterface is immune to that gunk. Once X
607 * has been fixed (and the fix spread enough), we can re-enable the
608 * 2 lines below and pass down a BAR value to userland. In that case
609 * we'll also have to re-enable the matching code in
610 * __pci_mmap_make_offset().
615 else if (rsrc->flags & IORESOURCE_MEM)
616 offset = hose->pci_mem_offset;
619 *start = rsrc->start - offset;
620 *end = rsrc->end - offset;
624 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
625 * @hose: newly allocated pci_controller to be setup
626 * @dev: device node of the host bridge
627 * @primary: set if primary bus (32 bits only, soon to be deprecated)
629 * This function will parse the "ranges" property of a PCI host bridge device
630 * node and setup the resource mapping of a pci controller based on its
633 * Life would be boring if it wasn't for a few issues that we have to deal
636 * - We can only cope with one IO space range and up to 3 Memory space
637 * ranges. However, some machines (thanks Apple !) tend to split their
638 * space into lots of small contiguous ranges. So we have to coalesce.
640 * - We can only cope with all memory ranges having the same offset
641 * between CPU addresses and PCI addresses. Unfortunately, some bridges
642 * are setup for a large 1:1 mapping along with a small "window" which
643 * maps PCI address 0 to some arbitrary high address of the CPU space in
644 * order to give access to the ISA memory hole.
645 * The way out of here that I've chosen for now is to always set the
646 * offset based on the first resource found, then override it if we
647 * have a different offset and the previous was set by an ISA hole.
649 * - Some busses have IO space not starting at 0, which causes trouble with
650 * the way we do our IO resource renumbering. The code somewhat deals with
651 * it for 64 bits but I would expect problems on 32 bits.
653 * - Some 32 bits platforms such as 4xx can have physical space larger than
654 * 32 bits so we need to use 64 bits values for the parsing
656 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
657 struct device_node *dev, int primary)
659 int memno = 0, isa_hole = -1;
660 unsigned long long isa_mb = 0;
661 struct resource *res;
662 struct of_pci_range range;
663 struct of_pci_range_parser parser;
665 pr_info("PCI host bridge %s %s ranges:\n",
666 dev->full_name, primary ? "(primary)" : "");
668 /* Check for ranges property */
669 if (of_pci_range_parser_init(&parser, dev))
672 pr_debug("Parsing ranges property...\n");
673 for_each_of_pci_range(&parser, &range) {
674 /* Read next ranges element */
675 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
676 range.pci_space, range.pci_addr);
677 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
678 range.cpu_addr, range.size);
680 /* If we failed translation or got a zero-sized region
681 * (some FW try to feed us with non sensical zero sized regions
682 * such as power3 which look like some kind of attempt
683 * at exposing the VGA memory hole)
685 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
688 /* Act based on address space type */
690 switch (range.flags & IORESOURCE_TYPE_BITS) {
692 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
693 range.cpu_addr, range.cpu_addr + range.size - 1,
696 /* We support only one IO range */
697 if (hose->pci_io_size) {
698 pr_info(" \\--> Skipped (too many) !\n");
701 /* On 32 bits, limit I/O space to 16MB */
702 if (range.size > 0x01000000)
703 range.size = 0x01000000;
705 /* 32 bits needs to map IOs here */
706 hose->io_base_virt = ioremap(range.cpu_addr,
709 /* Expect trouble if pci_addr is not 0 */
712 (unsigned long)hose->io_base_virt;
713 /* pci_io_size and io_base_phys always represent IO
714 * space starting at 0 so we factor in pci_addr
716 hose->pci_io_size = range.pci_addr + range.size;
717 hose->io_base_phys = range.cpu_addr - range.pci_addr;
720 res = &hose->io_resource;
721 range.cpu_addr = range.pci_addr;
725 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
726 range.cpu_addr, range.cpu_addr + range.size - 1,
728 (range.pci_space & 0x40000000) ?
731 /* We support only 3 memory ranges */
733 pr_info(" \\--> Skipped (too many) !\n");
736 /* Handles ISA memory hole space here */
737 if (range.pci_addr == 0) {
738 isa_mb = range.cpu_addr;
740 if (primary || isa_mem_base == 0)
741 isa_mem_base = range.cpu_addr;
742 hose->isa_mem_phys = range.cpu_addr;
743 hose->isa_mem_size = range.size;
746 /* We get the PCI/Mem offset from the first range or
747 * the, current one if the offset came from an ISA
748 * hole. If they don't match, bugger.
751 (isa_hole >= 0 && range.pci_addr != 0 &&
752 hose->pci_mem_offset == isa_mb))
753 hose->pci_mem_offset = range.cpu_addr -
755 else if (range.pci_addr != 0 &&
756 hose->pci_mem_offset != range.cpu_addr -
758 pr_info(" \\--> Skipped (offset mismatch) !\n");
763 res = &hose->mem_resources[memno++];
767 of_pci_range_to_resource(&range, dev, res);
770 /* If there's an ISA hole and the pci_mem_offset is -not- matching
771 * the ISA hole offset, then we need to remove the ISA hole from
772 * the resource list for that brige
774 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
775 unsigned int next = isa_hole + 1;
776 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
778 memmove(&hose->mem_resources[isa_hole],
779 &hose->mem_resources[next],
780 sizeof(struct resource) * (memno - next));
781 hose->mem_resources[--memno].flags = 0;
785 /* Decide whether to display the domain number in /proc */
786 int pci_proc_domain(struct pci_bus *bus)
791 /* This header fixup will do the resource fixup for all devices as they are
792 * probed, but not for bridge ranges
794 static void pcibios_fixup_resources(struct pci_dev *dev)
796 struct pci_controller *hose = pci_bus_to_host(dev->bus);
800 pr_err("No host bridge for PCI dev %s !\n",
804 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
805 struct resource *res = dev->resource + i;
808 if (res->start == 0) {
809 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
811 (unsigned long long)res->start,
812 (unsigned long long)res->end,
813 (unsigned int)res->flags);
814 pr_debug("is unassigned\n");
815 res->end -= res->start;
817 res->flags |= IORESOURCE_UNSET;
821 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
823 (unsigned long long)res->start,
824 (unsigned long long)res->end,
825 (unsigned int)res->flags);
828 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
830 /* This function tries to figure out if a bridge resource has been initialized
831 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
832 * things go more smoothly when it gets it right. It should covers cases such
833 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
835 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
836 struct resource *res)
838 struct pci_controller *hose = pci_bus_to_host(bus);
839 struct pci_dev *dev = bus->self;
840 resource_size_t offset;
844 /* Job is a bit different between memory and IO */
845 if (res->flags & IORESOURCE_MEM) {
846 /* If the BAR is non-0 (res != pci_mem_offset) then it's
847 * probably been initialized by somebody
849 if (res->start != hose->pci_mem_offset)
852 /* The BAR is 0, let's check if memory decoding is enabled on
853 * the bridge. If not, we consider it unassigned
855 pci_read_config_word(dev, PCI_COMMAND, &command);
856 if ((command & PCI_COMMAND_MEMORY) == 0)
859 /* Memory decoding is enabled and the BAR is 0. If any of
860 * the bridge resources covers that starting address (0 then
861 * it's good enough for us for memory
863 for (i = 0; i < 3; i++) {
864 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
865 hose->mem_resources[i].start == hose->pci_mem_offset)
869 /* Well, it starts at 0 and we know it will collide so we may as
870 * well consider it as unassigned. That covers the Apple case.
874 /* If the BAR is non-0, then we consider it assigned */
875 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
876 if (((res->start - offset) & 0xfffffffful) != 0)
879 /* Here, we are a bit different than memory as typically IO
880 * space starting at low addresses -is- valid. What we do
881 * instead if that we consider as unassigned anything that
882 * doesn't have IO enabled in the PCI command register,
885 pci_read_config_word(dev, PCI_COMMAND, &command);
886 if (command & PCI_COMMAND_IO)
889 /* It's starting at 0 and IO is disabled in the bridge, consider
896 /* Fixup resources of a PCI<->PCI bridge */
897 static void pcibios_fixup_bridge(struct pci_bus *bus)
899 struct resource *res;
902 struct pci_dev *dev = bus->self;
904 pci_bus_for_each_resource(bus, res, i) {
909 if (i >= 3 && bus->self->transparent)
912 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
914 (unsigned long long)res->start,
915 (unsigned long long)res->end,
916 (unsigned int)res->flags);
918 /* Try to detect uninitialized P2P bridge resources,
919 * and clear them out so they get re-assigned later
921 if (pcibios_uninitialized_bridge_resource(bus, res)) {
923 pr_debug("PCI:%s (unassigned)\n",
926 pr_debug("PCI:%s %016llx-%016llx\n",
928 (unsigned long long)res->start,
929 (unsigned long long)res->end);
934 void pcibios_setup_bus_self(struct pci_bus *bus)
936 /* Fix up the bus resources for P2P bridges */
937 if (bus->self != NULL)
938 pcibios_fixup_bridge(bus);
941 void pcibios_setup_bus_devices(struct pci_bus *bus)
945 pr_debug("PCI: Fixup bus devices %d (%s)\n",
946 bus->number, bus->self ? pci_name(bus->self) : "PHB");
948 list_for_each_entry(dev, &bus->devices, bus_list) {
949 /* Setup OF node pointer in archdata */
950 dev->dev.of_node = pci_device_to_OF_node(dev);
952 /* Fixup NUMA node as it may not be setup yet by the generic
953 * code and is needed by the DMA init
955 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
957 /* Hook up default DMA ops */
958 set_dma_ops(&dev->dev, pci_dma_ops);
959 dev->dev.archdata.dma_data = (void *)PCI_DRAM_OFFSET;
961 /* Read default IRQs and fixup if necessary */
962 pci_read_irq_line(dev);
966 void pcibios_fixup_bus(struct pci_bus *bus)
968 /* When called from the generic PCI probe, read PCI<->PCI bridge
969 * bases. This is -not- called when generating the PCI tree from
970 * the OF device-tree.
972 if (bus->self != NULL)
973 pci_read_bridge_bases(bus);
975 /* Now fixup the bus bus */
976 pcibios_setup_bus_self(bus);
978 /* Now fixup devices on that bus */
979 pcibios_setup_bus_devices(bus);
981 EXPORT_SYMBOL(pcibios_fixup_bus);
983 static int skip_isa_ioresource_align(struct pci_dev *dev)
989 * We need to avoid collisions with `mirrored' VGA ports
990 * and other strange ISA hardware, so we always want the
991 * addresses to be allocated in the 0x000-0x0ff region
994 * Why? Because some silly external IO cards only decode
995 * the low 10 bits of the IO address. The 0x00-0xff region
996 * is reserved for motherboard devices that decode all 16
997 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
998 * but we want to try to avoid allocating at 0x2900-0x2bff
999 * which might have be mirrored at 0x0100-0x03ff..
1001 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1002 resource_size_t size, resource_size_t align)
1004 struct pci_dev *dev = data;
1005 resource_size_t start = res->start;
1007 if (res->flags & IORESOURCE_IO) {
1008 if (skip_isa_ioresource_align(dev))
1011 start = (start + 0x3ff) & ~0x3ff;
1016 EXPORT_SYMBOL(pcibios_align_resource);
1019 * Reparent resource children of pr that conflict with res
1020 * under res, and make res replace those children.
1022 static int __init reparent_resources(struct resource *parent,
1023 struct resource *res)
1025 struct resource *p, **pp;
1026 struct resource **firstpp = NULL;
1028 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1029 if (p->end < res->start)
1031 if (res->end < p->start)
1033 if (p->start < res->start || p->end > res->end)
1034 return -1; /* not completely contained */
1035 if (firstpp == NULL)
1038 if (firstpp == NULL)
1039 return -1; /* didn't find any conflicting entries? */
1040 res->parent = parent;
1041 res->child = *firstpp;
1045 for (p = res->child; p != NULL; p = p->sibling) {
1047 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1049 (unsigned long long)p->start,
1050 (unsigned long long)p->end, res->name);
1056 * Handle resources of PCI devices. If the world were perfect, we could
1057 * just allocate all the resource regions and do nothing more. It isn't.
1058 * On the other hand, we cannot just re-allocate all devices, as it would
1059 * require us to know lots of host bridge internals. So we attempt to
1060 * keep as much of the original configuration as possible, but tweak it
1061 * when it's found to be wrong.
1063 * Known BIOS problems we have to work around:
1064 * - I/O or memory regions not configured
1065 * - regions configured, but not enabled in the command register
1066 * - bogus I/O addresses above 64K used
1067 * - expansion ROMs left enabled (this may sound harmless, but given
1068 * the fact the PCI specs explicitly allow address decoders to be
1069 * shared between expansion ROMs and other resource regions, it's
1070 * at least dangerous)
1073 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1074 * This gives us fixed barriers on where we can allocate.
1075 * (2) Allocate resources for all enabled devices. If there is
1076 * a collision, just mark the resource as unallocated. Also
1077 * disable expansion ROMs during this step.
1078 * (3) Try to allocate resources for disabled devices. If the
1079 * resources were assigned correctly, everything goes well,
1080 * if they weren't, they won't disturb allocation of other
1082 * (4) Assign new addresses to resources which were either
1083 * not configured at all or misconfigured. If explicitly
1084 * requested by the user, configure expansion ROM address
1088 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1092 struct resource *res, *pr;
1094 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1095 pci_domain_nr(bus), bus->number);
1097 pci_bus_for_each_resource(bus, res, i) {
1098 if (!res || !res->flags
1099 || res->start > res->end || res->parent)
1101 if (bus->parent == NULL)
1102 pr = (res->flags & IORESOURCE_IO) ?
1103 &ioport_resource : &iomem_resource;
1105 /* Don't bother with non-root busses when
1106 * re-assigning all resources. We clear the
1107 * resource flags as if they were colliding
1108 * and as such ensure proper re-allocation
1111 pr = pci_find_parent_resource(bus->self, res);
1113 /* this happens when the generic PCI
1114 * code (wrongly) decides that this
1115 * bridge is transparent -- paulus
1121 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
1122 bus->self ? pci_name(bus->self) : "PHB",
1124 (unsigned long long)res->start,
1125 (unsigned long long)res->end);
1126 pr_debug("[0x%x], parent %p (%s)\n",
1127 (unsigned int)res->flags,
1128 pr, (pr && pr->name) ? pr->name : "nil");
1130 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1131 if (request_resource(pr, res) == 0)
1134 * Must be a conflict with an existing entry.
1135 * Move that entry (or entries) under the
1136 * bridge resource and try again.
1138 if (reparent_resources(pr, res) == 0)
1141 pr_warn("PCI: Cannot allocate resource region ");
1142 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
1143 res->start = res->end = 0;
1147 list_for_each_entry(b, &bus->children, node)
1148 pcibios_allocate_bus_resources(b);
1151 static inline void alloc_resource(struct pci_dev *dev, int idx)
1153 struct resource *pr, *r = &dev->resource[idx];
1155 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1157 (unsigned long long)r->start,
1158 (unsigned long long)r->end,
1159 (unsigned int)r->flags);
1161 pr = pci_find_parent_resource(dev, r);
1162 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1163 request_resource(pr, r) < 0) {
1164 pr_warn("PCI: Cannot allocate resource region %d ", idx);
1165 pr_cont("of device %s, will remap\n", pci_name(dev));
1167 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1169 (unsigned long long)pr->start,
1170 (unsigned long long)pr->end,
1171 (unsigned int)pr->flags);
1172 /* We'll assign a new address later */
1173 r->flags |= IORESOURCE_UNSET;
1179 static void __init pcibios_allocate_resources(int pass)
1181 struct pci_dev *dev = NULL;
1186 for_each_pci_dev(dev) {
1187 pci_read_config_word(dev, PCI_COMMAND, &command);
1188 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1189 r = &dev->resource[idx];
1190 if (r->parent) /* Already allocated */
1192 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1193 continue; /* Not assigned at all */
1194 /* We only allocate ROMs on pass 1 just in case they
1195 * have been screwed up by firmware
1197 if (idx == PCI_ROM_RESOURCE)
1199 if (r->flags & IORESOURCE_IO)
1200 disabled = !(command & PCI_COMMAND_IO);
1202 disabled = !(command & PCI_COMMAND_MEMORY);
1203 if (pass == disabled)
1204 alloc_resource(dev, idx);
1208 r = &dev->resource[PCI_ROM_RESOURCE];
1210 /* Turn the ROM off, leave the resource region,
1211 * but keep it unregistered.
1214 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1215 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1216 pr_debug("PCI: Switching off ROM of %s\n",
1218 r->flags &= ~IORESOURCE_ROM_ENABLE;
1219 pci_write_config_dword(dev, dev->rom_base_reg,
1220 reg & ~PCI_ROM_ADDRESS_ENABLE);
1226 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1228 struct pci_controller *hose = pci_bus_to_host(bus);
1229 resource_size_t offset;
1230 struct resource *res, *pres;
1233 pr_debug("Reserving legacy ranges for domain %04x\n",
1234 pci_domain_nr(bus));
1237 if (!(hose->io_resource.flags & IORESOURCE_IO))
1239 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1240 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1241 BUG_ON(res == NULL);
1242 res->name = "Legacy IO";
1243 res->flags = IORESOURCE_IO;
1244 res->start = offset;
1245 res->end = (offset + 0xfff) & 0xfffffffful;
1246 pr_debug("Candidate legacy IO: %pR\n", res);
1247 if (request_resource(&hose->io_resource, res)) {
1248 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1249 pci_domain_nr(bus), bus->number, res);
1254 /* Check for memory */
1255 offset = hose->pci_mem_offset;
1256 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1257 for (i = 0; i < 3; i++) {
1258 pres = &hose->mem_resources[i];
1259 if (!(pres->flags & IORESOURCE_MEM))
1261 pr_debug("hose mem res: %pR\n", pres);
1262 if ((pres->start - offset) <= 0xa0000 &&
1263 (pres->end - offset) >= 0xbffff)
1268 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1269 BUG_ON(res == NULL);
1270 res->name = "Legacy VGA memory";
1271 res->flags = IORESOURCE_MEM;
1272 res->start = 0xa0000 + offset;
1273 res->end = 0xbffff + offset;
1274 pr_debug("Candidate VGA memory: %pR\n", res);
1275 if (request_resource(pres, res)) {
1276 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1277 pci_domain_nr(bus), bus->number, res);
1282 void __init pcibios_resource_survey(void)
1286 /* Allocate and assign resources. If we re-assign everything, then
1287 * we skip the allocate phase
1289 list_for_each_entry(b, &pci_root_buses, node)
1290 pcibios_allocate_bus_resources(b);
1292 pcibios_allocate_resources(0);
1293 pcibios_allocate_resources(1);
1295 /* Before we start assigning unassigned resource, we try to reserve
1296 * the low IO area and the VGA memory area if they intersect the
1297 * bus available resources to avoid allocating things on top of them
1299 list_for_each_entry(b, &pci_root_buses, node)
1300 pcibios_reserve_legacy_regions(b);
1302 /* Now proceed to assigning things that were left unassigned */
1303 pr_debug("PCI: Assigning unassigned resources...\n");
1304 pci_assign_unassigned_resources();
1307 /* This is used by the PCI hotplug driver to allocate resource
1308 * of newly plugged busses. We can try to consolidate with the
1309 * rest of the code later, for now, keep it as-is as our main
1310 * resource allocation function doesn't deal with sub-trees yet.
1312 void pcibios_claim_one_bus(struct pci_bus *bus)
1314 struct pci_dev *dev;
1315 struct pci_bus *child_bus;
1317 list_for_each_entry(dev, &bus->devices, bus_list) {
1320 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1321 struct resource *r = &dev->resource[i];
1323 if (r->parent || !r->start || !r->flags)
1326 pr_debug("PCI: Claiming %s: ", pci_name(dev));
1327 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
1328 i, (unsigned long long)r->start,
1329 (unsigned long long)r->end,
1330 (unsigned int)r->flags);
1332 pci_claim_resource(dev, i);
1336 list_for_each_entry(child_bus, &bus->children, node)
1337 pcibios_claim_one_bus(child_bus);
1339 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1342 /* pcibios_finish_adding_to_bus
1344 * This is to be called by the hotplug code after devices have been
1345 * added to a bus, this include calling it for a PHB that is just
1348 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1350 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1351 pci_domain_nr(bus), bus->number);
1353 /* Allocate bus and devices resources */
1354 pcibios_allocate_bus_resources(bus);
1355 pcibios_claim_one_bus(bus);
1357 /* Add new devices to global lists. Register in proc, sysfs. */
1358 pci_bus_add_devices(bus);
1361 /* eeh_add_device_tree_late(bus); */
1363 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1365 int pcibios_enable_device(struct pci_dev *dev, int mask)
1367 return pci_enable_resources(dev, mask);
1370 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1371 struct list_head *resources)
1373 unsigned long io_offset;
1374 struct resource *res;
1377 /* Hookup PHB IO resource */
1378 res = &hose->io_resource;
1380 /* Fixup IO space offset */
1381 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1382 res->start = (res->start + io_offset) & 0xffffffffu;
1383 res->end = (res->end + io_offset) & 0xffffffffu;
1386 pr_warn("PCI: I/O resource not set for host ");
1387 pr_cont("bridge %s (domain %d)\n",
1388 hose->dn->full_name, hose->global_number);
1389 /* Workaround for lack of IO resource only on 32-bit */
1390 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1391 res->end = res->start + IO_SPACE_LIMIT;
1392 res->flags = IORESOURCE_IO;
1394 pci_add_resource_offset(resources, res,
1395 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1397 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1398 (unsigned long long)res->start,
1399 (unsigned long long)res->end,
1400 (unsigned long)res->flags);
1402 /* Hookup PHB Memory resources */
1403 for (i = 0; i < 3; ++i) {
1404 res = &hose->mem_resources[i];
1408 pr_err("PCI: Memory resource 0 not set for ");
1409 pr_cont("host bridge %s (domain %d)\n",
1410 hose->dn->full_name, hose->global_number);
1412 /* Workaround for lack of MEM resource only on 32-bit */
1413 res->start = hose->pci_mem_offset;
1414 res->end = (resource_size_t)-1LL;
1415 res->flags = IORESOURCE_MEM;
1418 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1420 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1421 i, (unsigned long long)res->start,
1422 (unsigned long long)res->end,
1423 (unsigned long)res->flags);
1426 pr_debug("PCI: PHB MEM offset = %016llx\n",
1427 (unsigned long long)hose->pci_mem_offset);
1428 pr_debug("PCI: PHB IO offset = %08lx\n",
1429 (unsigned long)hose->io_base_virt - _IO_BASE);
1432 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1434 struct pci_controller *hose = bus->sysdata;
1436 return of_node_get(hose->dn);
1439 static void pcibios_scan_phb(struct pci_controller *hose)
1441 LIST_HEAD(resources);
1442 struct pci_bus *bus;
1443 struct device_node *node = hose->dn;
1445 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1447 pcibios_setup_phb_resources(hose, &resources);
1449 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1450 hose->ops, hose, &resources);
1452 pr_err("Failed to create bus for PCI domain %04x\n",
1453 hose->global_number);
1454 pci_free_resource_list(&resources);
1457 bus->busn_res.start = hose->first_busno;
1460 hose->last_busno = bus->busn_res.end;
1463 static int __init pcibios_init(void)
1465 struct pci_controller *hose, *tmp;
1468 pr_info("PCI: Probing PCI hardware\n");
1470 /* Scan all of the recorded PCI controllers. */
1471 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1472 hose->last_busno = 0xff;
1473 pcibios_scan_phb(hose);
1474 if (next_busno <= hose->last_busno)
1475 next_busno = hose->last_busno + 1;
1477 pci_bus_count = next_busno;
1479 /* Call common code to handle resource allocation */
1480 pcibios_resource_survey();
1485 subsys_initcall(pcibios_init);
1487 static struct pci_controller *pci_bus_to_hose(int bus)
1489 struct pci_controller *hose, *tmp;
1491 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1492 if (bus >= hose->first_busno && bus <= hose->last_busno)
1497 /* Provide information on locations of various I/O regions in physical
1498 * memory. Do this on a per-card basis so that we choose the right
1500 * Note that the returned IO or memory base is a physical address
1503 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1505 struct pci_controller *hose;
1506 long result = -EOPNOTSUPP;
1508 hose = pci_bus_to_hose(bus);
1513 case IOBASE_BRIDGE_NUMBER:
1514 return (long)hose->first_busno;
1516 return (long)hose->pci_mem_offset;
1518 return (long)hose->io_base_phys;
1520 return (long)isa_io_base;
1521 case IOBASE_ISA_MEM:
1522 return (long)isa_mem_base;
1529 * Null PCI config access functions, for the case when we can't
1532 #define NULL_PCI_OP(rw, size, type) \
1534 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1536 return PCIBIOS_DEVICE_NOT_FOUND; \
1540 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1543 return PCIBIOS_DEVICE_NOT_FOUND;
1547 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1550 return PCIBIOS_DEVICE_NOT_FOUND;
1553 static struct pci_ops null_pci_ops = {
1554 .read = null_read_config,
1555 .write = null_write_config,
1559 * These functions are used early on before PCI scanning is done
1560 * and all of the pci_dev and pci_bus structures have been created.
1562 static struct pci_bus *
1563 fake_pci_bus(struct pci_controller *hose, int busnr)
1565 static struct pci_bus bus;
1568 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1572 bus.ops = hose ? hose->ops : &null_pci_ops;
1576 #define EARLY_PCI_OP(rw, size, type) \
1577 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1578 int devfn, int offset, type value) \
1580 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1581 devfn, offset, value); \
1584 EARLY_PCI_OP(read, byte, u8 *)
1585 EARLY_PCI_OP(read, word, u16 *)
1586 EARLY_PCI_OP(read, dword, u32 *)
1587 EARLY_PCI_OP(write, byte, u8)
1588 EARLY_PCI_OP(write, word, u16)
1589 EARLY_PCI_OP(write, dword, u32)
1591 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1594 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);