2 * Microblaze support for cache consistent memory.
3 * Copyright (C) 2010 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2010 PetaLogix
5 * Copyright (C) 2005 John Williams <jwilliams@itee.uq.edu.au>
7 * Based on PowerPC version derived from arch/arm/mm/consistent.c
8 * Copyright (C) 2001 Dan Malek (dmalek@jlc.net)
9 * Copyright (C) 2000 Russell King
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/export.h>
17 #include <linux/signal.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/string.h>
22 #include <linux/types.h>
23 #include <linux/ptrace.h>
24 #include <linux/mman.h>
26 #include <linux/swap.h>
27 #include <linux/stddef.h>
28 #include <linux/vmalloc.h>
29 #include <linux/init.h>
30 #include <linux/delay.h>
31 #include <linux/bootmem.h>
32 #include <linux/highmem.h>
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
35 #include <linux/gfp.h>
36 #include <linux/dma-noncoherent.h>
38 #include <asm/pgalloc.h>
40 #include <linux/hardirq.h>
41 #include <linux/mmu_context.h>
43 #include <linux/uaccess.h>
44 #include <asm/pgtable.h>
45 #include <asm/cpuinfo.h>
46 #include <asm/tlbflush.h>
49 /* I have to use dcache values because I can't relate on ram size */
50 # define UNCACHED_SHADOW_MASK (cpuinfo.dcache_high - cpuinfo.dcache_base + 1)
54 * Consistent memory allocators. Used for DMA devices that want to
55 * share uncached memory with the processor core.
56 * My crufty no-MMU approach is simple. In the HW platform we can optionally
57 * mirror the DDR up above the processor cacheable region. So, memory accessed
58 * in this mirror region will not be cached. It's alloced from the same
59 * pool as normal memory, but the handle we return is shifted up into the
60 * uncached region. This will no doubt cause big problems if memory allocated
61 * here is not also freed properly. -- JW
63 void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
64 gfp_t gfp, unsigned long attrs)
66 unsigned long order, vaddr;
68 unsigned int i, err = 0;
69 struct page *page, *end;
73 struct vm_struct *area;
80 /* Only allocate page size areas. */
81 size = PAGE_ALIGN(size);
82 order = get_order(size);
84 vaddr = __get_free_pages(gfp, order);
89 * we need to ensure that there are no cachelines in use,
90 * or worse dirty in this area.
92 flush_dcache_range(virt_to_phys((void *)vaddr),
93 virt_to_phys((void *)vaddr) + size);
98 * Here's the magic! Note if the uncached shadow is not implemented,
99 * it's up to the calling code to also test that condition and make
100 * other arranegments, such as manually flushing the cache and so on.
102 # ifdef CONFIG_XILINX_UNCACHED_SHADOW
103 ret = (void *)((unsigned) ret | UNCACHED_SHADOW_MASK);
105 if ((unsigned int)ret > cpuinfo.dcache_base &&
106 (unsigned int)ret < cpuinfo.dcache_high)
107 pr_warn("ERROR: Your cache coherent area is CACHED!!!\n");
109 /* dma_handle is same as physical (shadowed) address */
110 *dma_handle = (dma_addr_t)ret;
112 /* Allocate some common virtual space to map the new pages. */
113 area = get_vm_area(size, VM_ALLOC);
115 free_pages(vaddr, order);
118 va = (unsigned long) area->addr;
121 /* This gives us the real physical address of the first page. */
122 *dma_handle = pa = __virt_to_phys(vaddr);
126 * free wasted pages. We skip the first page since we know
127 * that it will have count = 1 and won't require freeing.
128 * We also mark the pages in use as reserved so that
129 * remap_page_range works.
131 page = virt_to_page(vaddr);
132 end = page + (1 << order);
134 split_page(page, order);
136 for (i = 0; i < size && err == 0; i += PAGE_SIZE) {
138 /* MS: This is the whole magic - use cache inhibit pages */
139 err = map_page(va + i, pa + i, _PAGE_KERNEL | _PAGE_NO_CACHE);
142 SetPageReserved(page);
146 /* Free the otherwise unused pages. */
153 free_pages(vaddr, order);
161 static pte_t *consistent_virt_to_pte(void *vaddr)
163 unsigned long addr = (unsigned long)vaddr;
165 return pte_offset_kernel(pmd_offset(pgd_offset_k(addr), addr), addr);
168 long arch_dma_coherent_to_pfn(struct device *dev, void *vaddr,
171 pte_t *ptep = consistent_virt_to_pte(vaddr);
173 if (pte_none(*ptep) || !pte_present(*ptep))
176 return pte_pfn(*ptep);
181 * free page(s) as defined by the above mapping.
183 void arch_dma_free(struct device *dev, size_t size, void *vaddr,
184 dma_addr_t dma_addr, unsigned long attrs)
191 size = PAGE_ALIGN(size);
194 /* Clear SHADOW_MASK bit in address, and free as per usual */
195 # ifdef CONFIG_XILINX_UNCACHED_SHADOW
196 vaddr = (void *)((unsigned)vaddr & ~UNCACHED_SHADOW_MASK);
198 page = virt_to_page(vaddr);
201 __free_reserved_page(page);
203 } while (size -= PAGE_SIZE);
206 pte_t *ptep = consistent_virt_to_pte(vaddr);
209 if (!pte_none(*ptep) && pte_present(*ptep)) {
210 pfn = pte_pfn(*ptep);
211 pte_clear(&init_mm, (unsigned int)vaddr, ptep);
212 if (pfn_valid(pfn)) {
213 page = pfn_to_page(pfn);
214 __free_reserved_page(page);
218 } while (size -= PAGE_SIZE);