2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012-2013 Xilinx, Inc.
4 * Copyright (C) 2007-2009 PetaLogix
5 * Copyright (C) 2006 Atmark Techno, Inc.
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/sched.h>
15 #include <linux/clk.h>
16 #include <linux/clockchips.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <asm/cpuinfo.h>
20 #include <linux/cnt32_to_63.h>
22 static void __iomem *timer_baseaddr;
24 static unsigned int freq_div_hz;
25 static unsigned int timer_clock_freq;
34 #define TCSR_MDT (1<<0)
35 #define TCSR_UDT (1<<1)
36 #define TCSR_GENT (1<<2)
37 #define TCSR_CAPT (1<<3)
38 #define TCSR_ARHT (1<<4)
39 #define TCSR_LOAD (1<<5)
40 #define TCSR_ENIT (1<<6)
41 #define TCSR_ENT (1<<7)
42 #define TCSR_TINT (1<<8)
43 #define TCSR_PWMA (1<<9)
44 #define TCSR_ENALL (1<<10)
46 static inline void xilinx_timer0_stop(void)
48 out_be32(timer_baseaddr + TCSR0,
49 in_be32(timer_baseaddr + TCSR0) & ~TCSR_ENT);
52 static inline void xilinx_timer0_start_periodic(unsigned long load_val)
56 /* loading value to timer reg */
57 out_be32(timer_baseaddr + TLR0, load_val);
59 /* load the initial value */
60 out_be32(timer_baseaddr + TCSR0, TCSR_LOAD);
62 /* see timer data sheet for detail
63 * !ENALL - don't enable 'em all
65 * TINT - clear interrupt status
66 * ENT- enable timer itself
67 * ENIT - enable interrupt
68 * !LOAD - clear the bit to let go
70 * !CAPT - no external trigger
71 * !GENT - no external signal
72 * UDT - set the timer as down counter
73 * !MDT0 - generate mode
75 out_be32(timer_baseaddr + TCSR0,
76 TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
79 static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
83 /* loading value to timer reg */
84 out_be32(timer_baseaddr + TLR0, load_val);
86 /* load the initial value */
87 out_be32(timer_baseaddr + TCSR0, TCSR_LOAD);
89 out_be32(timer_baseaddr + TCSR0,
90 TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
93 static int xilinx_timer_set_next_event(unsigned long delta,
94 struct clock_event_device *dev)
96 pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
97 xilinx_timer0_start_oneshot(delta);
101 static void xilinx_timer_set_mode(enum clock_event_mode mode,
102 struct clock_event_device *evt)
105 case CLOCK_EVT_MODE_PERIODIC:
106 pr_info("%s: periodic\n", __func__);
107 xilinx_timer0_start_periodic(freq_div_hz);
109 case CLOCK_EVT_MODE_ONESHOT:
110 pr_info("%s: oneshot\n", __func__);
112 case CLOCK_EVT_MODE_UNUSED:
113 pr_info("%s: unused\n", __func__);
115 case CLOCK_EVT_MODE_SHUTDOWN:
116 pr_info("%s: shutdown\n", __func__);
117 xilinx_timer0_stop();
119 case CLOCK_EVT_MODE_RESUME:
120 pr_info("%s: resume\n", __func__);
125 static struct clock_event_device clockevent_xilinx_timer = {
126 .name = "xilinx_clockevent",
127 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
130 .set_next_event = xilinx_timer_set_next_event,
131 .set_mode = xilinx_timer_set_mode,
134 static inline void timer_ack(void)
136 out_be32(timer_baseaddr + TCSR0, in_be32(timer_baseaddr + TCSR0));
139 static irqreturn_t timer_interrupt(int irq, void *dev_id)
141 struct clock_event_device *evt = &clockevent_xilinx_timer;
142 #ifdef CONFIG_HEART_BEAT
146 evt->event_handler(evt);
150 static struct irqaction timer_irqaction = {
151 .handler = timer_interrupt,
152 .flags = IRQF_DISABLED | IRQF_TIMER,
154 .dev_id = &clockevent_xilinx_timer,
157 static __init void xilinx_clockevent_init(void)
159 clockevent_xilinx_timer.mult =
160 div_sc(timer_clock_freq, NSEC_PER_SEC,
161 clockevent_xilinx_timer.shift);
162 clockevent_xilinx_timer.max_delta_ns =
163 clockevent_delta2ns((u32)~0, &clockevent_xilinx_timer);
164 clockevent_xilinx_timer.min_delta_ns =
165 clockevent_delta2ns(1, &clockevent_xilinx_timer);
166 clockevent_xilinx_timer.cpumask = cpumask_of(0);
167 clockevents_register_device(&clockevent_xilinx_timer);
170 static cycle_t xilinx_read(struct clocksource *cs)
172 /* reading actual value of timer 1 */
173 return (cycle_t) (in_be32(timer_baseaddr + TCR1));
176 static struct timecounter xilinx_tc = {
180 static cycle_t xilinx_cc_read(const struct cyclecounter *cc)
182 return xilinx_read(NULL);
185 static struct cyclecounter xilinx_cc = {
186 .read = xilinx_cc_read,
187 .mask = CLOCKSOURCE_MASK(32),
191 static int __init init_xilinx_timecounter(void)
193 xilinx_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC,
196 timecounter_init(&xilinx_tc, &xilinx_cc, sched_clock());
201 static struct clocksource clocksource_microblaze = {
202 .name = "xilinx_clocksource",
205 .mask = CLOCKSOURCE_MASK(32),
206 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
209 static int __init xilinx_clocksource_init(void)
211 if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq))
212 panic("failed to register clocksource");
215 out_be32(timer_baseaddr + TCSR1,
216 in_be32(timer_baseaddr + TCSR1) & ~TCSR_ENT);
217 /* start timer1 - up counting without interrupt */
218 out_be32(timer_baseaddr + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);
220 /* register timecounter - for ftrace support */
221 init_xilinx_timecounter();
226 * We have to protect accesses before timer initialization
227 * and return 0 for sched_clock function below.
229 static int timer_initialized;
231 static void __init xilinx_timer_init(struct device_node *timer)
237 timer_baseaddr = of_iomap(timer, 0);
238 if (!timer_baseaddr) {
239 pr_err("ERROR: invalid timer base address\n");
243 irq = irq_of_parse_and_map(timer, 0);
245 of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num);
247 pr_emerg("Please enable two timers in HW\n");
251 pr_info("%s: irq=%d\n", timer->full_name, irq);
253 /* If there is clock-frequency property than use it */
254 ret = of_property_read_u32(timer, "clock-frequency", &timer_clock_freq);
256 timer_clock_freq = cpuinfo.cpu_clock_freq;
258 freq_div_hz = timer_clock_freq / HZ;
260 setup_irq(irq, &timer_irqaction);
261 #ifdef CONFIG_HEART_BEAT
264 xilinx_clocksource_init();
265 xilinx_clockevent_init();
266 timer_initialized = 1;
269 unsigned long long notrace sched_clock(void)
271 if (timer_initialized) {
272 struct clocksource *cs = &clocksource_microblaze;
274 cycle_t cyc = cnt32_to_63(cs->read(NULL)) & LLONG_MAX;
275 return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
280 CLOCKSOURCE_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a",