1 #ifndef _M68KNOMMU_SYSTEM_H
2 #define _M68KNOMMU_SYSTEM_H
4 #include <linux/linkage.h>
5 #include <linux/irqflags.h>
6 #include <asm/segment.h>
10 * switch_to(n) should switch tasks to task ptr, first checking that
11 * ptr isn't the current task, in which case it does nothing. This
12 * also clears the TS-flag if the task we switched to has used the
13 * math co-processor latest.
16 * switch_to() saves the extra registers, that are not saved
17 * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
18 * a0-a1. Some of these are used by schedule() and its predecessors
19 * and so we might get see unexpected behaviors when a task returns
20 * with unexpected register values.
22 * syscall stores these registers itself and none of them are used
23 * by syscall after the function in the syscall has been called.
25 * Beware that resume now expects *next to be in d1 and the offset of
26 * tss to be in a1. This saves a few instructions as we no longer have
27 * to push them onto the stack and read them back right after.
29 * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
31 * Changed 96/09/19 by Andreas Schwab
32 * pass prev in a0, next in a1, offset of tss in d1, and whether
33 * the mm structures are shared in d2 (to avoid atc flushing).
35 asmlinkage void resume(void);
36 #define switch_to(prev,next,last) \
39 __asm__ __volatile__( \
40 "movel %1, %%a0\n\t" \
41 "movel %2, %%a1\n\t" \
43 "movel %%d1, %0\n\t" \
45 : "d" (prev), "d" (next) \
46 : "cc", "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1"); \
50 #define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc")
53 * Force strict CPU ordering.
54 * Not really required on m68k...
56 #define nop() asm volatile ("nop"::)
57 #define mb() asm volatile ("" : : :"memory")
58 #define rmb() asm volatile ("" : : :"memory")
59 #define wmb() asm volatile ("" : : :"memory")
60 #define set_mb(var, value) ({ (var) = (value); wmb(); })
64 #define smp_rmb() rmb()
65 #define smp_wmb() wmb()
66 #define smp_read_barrier_depends() read_barrier_depends()
68 #define smp_mb() barrier()
69 #define smp_rmb() barrier()
70 #define smp_wmb() barrier()
71 #define smp_read_barrier_depends() do { } while(0)
74 #define read_barrier_depends() ((void)0)
76 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
78 struct __xchg_dummy { unsigned long a[100]; };
79 #define __xg(x) ((volatile struct __xchg_dummy *)(x))
81 #ifndef CONFIG_RMW_INSNS
82 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
84 unsigned long tmp, flags;
86 local_irq_save(flags);
93 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
99 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
105 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
108 local_irq_restore(flags);
112 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
121 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
129 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
137 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
144 #include <asm-generic/cmpxchg-local.h>
147 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
150 #define cmpxchg_local(ptr, o, n) \
151 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
152 (unsigned long)(n), sizeof(*(ptr))))
153 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
156 #include <asm-generic/cmpxchg.h>
159 #define arch_align_stack(x) (x)
162 #endif /* _M68KNOMMU_SYSTEM_H */