1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
5 #include <linux/init.h>
6 #include <linux/threads.h>
8 #include <asm/addrspace.h>
10 #include <asm/asmmacro.h>
11 #include <asm/regdef.h>
12 #include <asm/loongarch.h>
13 #include <asm/stackframe.h>
15 #ifdef CONFIG_EFI_STUB
17 #include "efi-header.S"
22 .word MZ_MAGIC /* "MZ", MS-DOS header */
23 .org 0x3c /* 0x04 ~ 0x3b reserved */
24 .long pe_header - _head /* Offset to the PE header */
29 SYM_DATA(kernel_asize, .long _end - _text);
30 SYM_DATA(kernel_fsize, .long _edata - _text);
31 SYM_DATA(kernel_offset, .long kernel_offset - _text);
37 SYM_CODE_START(kernel_entry) # kernel entry point
39 /* Config direct window and set PG */
40 li.d t0, CSR_DMW0_INIT # UC, PLV0, 0x8000 xxxx xxxx xxxx
41 csrwr t0, LOONGARCH_CSR_DMWIN0
42 li.d t0, CSR_DMW1_INIT # CA, PLV0, 0x9000 xxxx xxxx xxxx
43 csrwr t0, LOONGARCH_CSR_DMWIN1
45 /* We might not get launched at the address the kernel is linked to,
51 li.w t0, 0xb0 # PLV=0, IE=0, PG=1
52 csrwr t0, LOONGARCH_CSR_CRMD
53 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0
54 csrwr t0, LOONGARCH_CSR_PRMD
55 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
56 csrwr t0, LOONGARCH_CSR_EUEN
58 la t0, __bss_start # clear .bss
60 la t1, __bss_stop - LONGSIZE
62 addi.d t0, t0, LONGSIZE
67 st.d a0, t0, 0 # firmware arguments
73 /* KSave3 used for percpu base, initialized as 0 */
74 csrwr zero, PERCPU_BASE_KS
75 /* GPR21 used for percpu base (runtime), initialized as 0 */
78 la tp, init_thread_union
79 /* Set the SP after an empty pt_regs. */
80 PTR_LI sp, (_THREAD_SIZE - 32 - PT_SIZE)
82 set_saved_sp sp, t0, t1
83 PTR_ADDI sp, sp, -4 * SZREG # init stack pointer
87 SYM_CODE_END(kernel_entry)
92 * SMP slave cpus entry point. Board specific code for bootstrap calls this
93 * function after setting up the stack and tp registers.
95 SYM_CODE_START(smpboot_entry)
96 li.d t0, CSR_DMW0_INIT # UC, PLV0
97 csrwr t0, LOONGARCH_CSR_DMWIN0
98 li.d t0, CSR_DMW1_INIT # CA, PLV0
99 csrwr t0, LOONGARCH_CSR_DMWIN1
105 li.w t0, 0xb0 # PLV=0, IE=0, PG=1
106 csrwr t0, LOONGARCH_CSR_CRMD
107 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0
108 csrwr t0, LOONGARCH_CSR_PRMD
109 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
110 csrwr t0, LOONGARCH_CSR_EUEN
112 la.abs t0, cpuboot_data
113 ld.d sp, t0, CPU_BOOT_STACK
114 ld.d tp, t0, CPU_BOOT_TINFO
117 SYM_CODE_END(smpboot_entry)
119 #endif /* CONFIG_SMP */
121 SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE)