1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Cache operations for the cache instruction.
5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
7 #ifndef __ASM_CACHEOPS_H
8 #define __ASM_CACHEOPS_H
11 * Most cache ops are split into a 2 bit field identifying the cache, and a 3
12 * bit field identifying the cache operation.
14 #define CacheOp_Cache 0x03
15 #define CacheOp_Op 0x1c
22 #define Index_Invalidate 0x08
23 #define Index_Writeback_Inv 0x08
24 #define Hit_Invalidate 0x10
25 #define Hit_Writeback_Inv 0x10
26 #define CacheOp_User_Defined 0x18
28 #define Index_Invalidate_I (Cache_I | Index_Invalidate)
29 #define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv)
30 #define Index_Writeback_Inv_V (Cache_V | Index_Writeback_Inv)
31 #define Index_Writeback_Inv_S (Cache_S | Index_Writeback_Inv)
32 #define Hit_Invalidate_I (Cache_I | Hit_Invalidate)
33 #define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv)
34 #define Hit_Writeback_Inv_V (Cache_V | Hit_Writeback_Inv)
35 #define Hit_Writeback_Inv_S (Cache_S | Hit_Writeback_Inv)
37 #endif /* __ASM_CACHEOPS_H */