1 #ifndef _ASM_IA64_SPINLOCK_H
2 #define _ASM_IA64_SPINLOCK_H
5 * Copyright (C) 1998-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
9 * This file is used for SMP configurations only.
12 #include <linux/compiler.h>
13 #include <linux/kernel.h>
14 #include <linux/bitops.h>
16 #include <linux/atomic.h>
17 #include <asm/intrinsics.h>
18 #include <asm/barrier.h>
19 #include <asm/processor.h>
21 #define arch_spin_lock_init(x) ((x)->lock = 0)
24 * Ticket locks are conceptually two parts, one indicating the current head of
25 * the queue, and the other indicating the current tail. The lock is acquired
26 * by atomically noting the tail and incrementing it by one (thus adding
27 * ourself to the queue and noting our position), then waiting until the head
28 * becomes equal to the the initial value of the tail.
29 * The pad bits in the middle are used to prevent the next_ticket number
30 * overflowing into the now_serving number.
33 * +----------------------------------------------------+
34 * | now_serving | padding | next_ticket |
35 * +----------------------------------------------------+
38 #define TICKET_SHIFT 17
39 #define TICKET_BITS 15
40 #define TICKET_MASK ((1 << TICKET_BITS) - 1)
42 static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock)
44 int *p = (int *)&lock->lock, ticket, serve;
46 ticket = ia64_fetchadd(1, p, acq);
48 if (!(((ticket >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
54 asm volatile ("ld4.c.nc %0=[%1]" : "=r"(serve) : "r"(p) : "memory");
56 if (!(((serve >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
62 static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
64 int tmp = ACCESS_ONCE(lock->lock);
66 if (!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK))
67 return ia64_cmpxchg(acq, &lock->lock, tmp, tmp + 1, sizeof (tmp)) == tmp;
71 static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
73 unsigned short *p = (unsigned short *)&lock->lock + 1, tmp;
75 asm volatile ("ld2.bias %0=[%1]" : "=r"(tmp) : "r"(p));
76 ACCESS_ONCE(*p) = (tmp + 2) & ~1;
79 static __always_inline void __ticket_spin_unlock_wait(arch_spinlock_t *lock)
81 int *p = (int *)&lock->lock, ticket;
86 asm volatile ("ld4.c.nc %0=[%1]" : "=r"(ticket) : "r"(p) : "memory");
87 if (!(((ticket >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
92 smp_acquire__after_ctrl_dep();
95 static inline int __ticket_spin_is_locked(arch_spinlock_t *lock)
97 long tmp = ACCESS_ONCE(lock->lock);
99 return !!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK);
102 static inline int __ticket_spin_is_contended(arch_spinlock_t *lock)
104 long tmp = ACCESS_ONCE(lock->lock);
106 return ((tmp - (tmp >> TICKET_SHIFT)) & TICKET_MASK) > 1;
109 static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
111 return !(((lock.lock >> TICKET_SHIFT) ^ lock.lock) & TICKET_MASK);
114 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
116 return __ticket_spin_is_locked(lock);
119 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
121 return __ticket_spin_is_contended(lock);
123 #define arch_spin_is_contended arch_spin_is_contended
125 static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
127 __ticket_spin_lock(lock);
130 static __always_inline int arch_spin_trylock(arch_spinlock_t *lock)
132 return __ticket_spin_trylock(lock);
135 static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
137 __ticket_spin_unlock(lock);
140 static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock,
143 arch_spin_lock(lock);
146 static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
148 __ticket_spin_unlock_wait(lock);
151 #define arch_read_can_lock(rw) (*(volatile int *)(rw) >= 0)
152 #define arch_write_can_lock(rw) (*(volatile int *)(rw) == 0)
156 static __always_inline void
157 arch_read_lock_flags(arch_rwlock_t *lock, unsigned long flags)
159 __asm__ __volatile__ (
160 "tbit.nz p6, p0 = %1,%2\n"
163 "fetchadd4.rel r2 = [%0], -1;;\n"
168 "cmp4.lt p7,p0 = r2, r0\n"
169 "(p7) br.cond.spnt.few 2b\n"
173 "fetchadd4.acq r2 = [%0], 1;;\n"
174 "cmp4.lt p7,p0 = r2, r0\n"
175 "(p7) br.cond.spnt.few 1b\n"
176 : : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT)
177 : "p6", "p7", "r2", "memory");
180 #define arch_read_lock(lock) arch_read_lock_flags(lock, 0)
182 #else /* !ASM_SUPPORTED */
184 #define arch_read_lock_flags(rw, flags) arch_read_lock(rw)
186 #define arch_read_lock(rw) \
188 arch_rwlock_t *__read_lock_ptr = (rw); \
190 while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) { \
191 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
192 while (*(volatile int *)__read_lock_ptr < 0) \
197 #endif /* !ASM_SUPPORTED */
199 #define arch_read_unlock(rw) \
201 arch_rwlock_t *__read_lock_ptr = (rw); \
202 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
207 static __always_inline void
208 arch_write_lock_flags(arch_rwlock_t *lock, unsigned long flags)
210 __asm__ __volatile__ (
211 "tbit.nz p6, p0 = %1, %2\n"
213 "dep r29 = -1, r0, 31, 1\n"
220 "cmp4.eq p0,p7 = r0, r2\n"
221 "(p7) br.cond.spnt.few 2b\n"
225 "cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n"
226 "cmp4.eq p0,p7 = r0, r2\n"
227 "(p7) br.cond.spnt.few 1b;;\n"
228 : : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT)
229 : "ar.ccv", "p6", "p7", "r2", "r29", "memory");
232 #define arch_write_lock(rw) arch_write_lock_flags(rw, 0)
234 #define arch_write_trylock(rw) \
236 register long result; \
238 __asm__ __volatile__ ( \
239 "mov ar.ccv = r0\n" \
240 "dep r29 = -1, r0, 31, 1;;\n" \
241 "cmpxchg4.acq %0 = [%1], r29, ar.ccv\n" \
242 : "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory"); \
246 static inline void arch_write_unlock(arch_rwlock_t *x)
250 asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
253 #else /* !ASM_SUPPORTED */
255 #define arch_write_lock_flags(l, flags) arch_write_lock(l)
257 #define arch_write_lock(l) \
259 __u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1); \
260 __u32 *ia64_write_lock_ptr = (__u32 *) (l); \
262 while (*ia64_write_lock_ptr) \
264 ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0); \
265 } while (ia64_val); \
268 #define arch_write_trylock(rw) \
271 __u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1); \
272 ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0); \
276 static inline void arch_write_unlock(arch_rwlock_t *x)
282 #endif /* !ASM_SUPPORTED */
284 static inline int arch_read_trylock(arch_rwlock_t *x)
290 old.lock = new.lock = *x;
291 old.lock.write_lock = new.lock.write_lock = 0;
292 ++new.lock.read_counter;
293 return (u32)ia64_cmpxchg4_acq((__u32 *)(x), new.word, old.word) == old.word;
296 #define arch_spin_relax(lock) cpu_relax()
297 #define arch_read_relax(lock) cpu_relax()
298 #define arch_write_relax(lock) cpu_relax()
300 #endif /* _ASM_IA64_SPINLOCK_H */