1 #ifndef _ASM_IA64_PCI_H
2 #define _ASM_IA64_PCI_H
5 #include <linux/slab.h>
6 #include <linux/spinlock.h>
7 #include <linux/string.h>
8 #include <linux/types.h>
11 #include <asm/scatterlist.h>
12 #include <asm/hw_irq.h>
15 * Can be used to override the logic in pci_scan_bus for skipping already-configured bus
16 * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
19 #define pcibios_assign_all_busses() 0
21 #define PCIBIOS_MIN_IO 0x1000
22 #define PCIBIOS_MIN_MEM 0x10000000
24 void pcibios_config_init(void);
29 * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct
30 * correspondence between device bus addresses and CPU physical addresses.
31 * Platforms with a hardware I/O MMU _must_ turn this off to suppress the
32 * bounce buffer handling code in the block and network device layers.
33 * Platforms with separate bus address spaces _must_ turn this off and provide
34 * a device DMA mapping implementation that takes care of the necessary
35 * address translation.
37 * For now, the ia64 platforms which may have separate/multiple bus address
38 * spaces all have I/O MMUs which support the merging of physically
39 * discontiguous buffers, so we can use that as the sole factor to determine
40 * the setting of PCI_DMA_BUS_IS_PHYS.
42 extern unsigned long ia64_max_iommu_merge_mask;
43 #define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL)
46 pcibios_set_master (struct pci_dev *dev)
48 /* No special bus mastering setup handling */
52 pcibios_penalize_isa_irq (int irq, int active)
54 /* We don't do dynamic PCI IRQ allocation */
57 #include <asm-generic/pci-dma-compat.h>
59 #include <linux/pci-dma.h>
62 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
63 enum pci_dma_burst_strategy *strat,
64 unsigned long *strategy_parameter)
66 unsigned long cacheline_size;
69 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
71 cacheline_size = 1024;
73 cacheline_size = (int) byte * 4;
75 *strat = PCI_DMA_BURST_MULTIPLE;
76 *strategy_parameter = cacheline_size;
81 extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
82 enum pci_mmap_state mmap_state, int write_combine);
83 #define HAVE_PCI_LEGACY
84 extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
85 struct vm_area_struct *vma,
86 enum pci_mmap_state mmap_state);
88 #define pci_get_legacy_mem platform_pci_get_legacy_mem
89 #define pci_legacy_read platform_pci_legacy_read
90 #define pci_legacy_write platform_pci_legacy_write
93 struct resource resource;
97 struct pci_controller {
101 int node; /* nearest node with memory or -1 for global allocation */
103 unsigned int windows;
104 struct pci_window *window;
109 #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
110 #define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment)
112 extern struct pci_ops pci_root_ops;
114 static inline int pci_proc_domain(struct pci_bus *bus)
116 return (pci_domain_nr(bus) != 0);
119 extern void pcibios_resource_to_bus(struct pci_dev *dev,
120 struct pci_bus_region *region, struct resource *res);
122 extern void pcibios_bus_to_resource(struct pci_dev *dev,
123 struct resource *res, struct pci_bus_region *region);
125 static inline struct resource *
126 pcibios_select_root(struct pci_dev *pdev, struct resource *res)
128 struct resource *root = NULL;
130 if (res->flags & IORESOURCE_IO)
131 root = &ioport_resource;
132 if (res->flags & IORESOURCE_MEM)
133 root = &iomem_resource;
138 #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
139 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
141 return channel ? isa_irq_to_vector(15) : isa_irq_to_vector(14);
145 extern void pci_iommu_alloc(void);
147 #endif /* _ASM_IA64_PCI_H */