2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/config.h>
38 #include <linux/init.h>
39 #include <linux/kernel.h>
42 #include <linux/sched.h>
43 #include <linux/kernel_stat.h>
44 #include <linux/smp_lock.h>
45 #include <linux/bootmem.h>
46 #include <linux/notifier.h>
47 #include <linux/cpu.h>
48 #include <linux/percpu.h>
50 #include <linux/delay.h>
51 #include <linux/mc146818rtc.h>
52 #include <asm/tlbflush.h>
54 #include <asm/arch_hooks.h>
56 #include <mach_apic.h>
57 #include <mach_wakecpu.h>
58 #include <smpboot_hooks.h>
60 /* Set if we find a B stepping CPU */
61 static int __devinitdata smp_b_stepping;
63 /* Number of siblings per CPU package */
64 int smp_num_siblings = 1;
66 EXPORT_SYMBOL(smp_num_siblings);
69 /* Package ID of each logical CPU */
70 int phys_proc_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
71 EXPORT_SYMBOL(phys_proc_id);
73 /* Core ID of each logical CPU */
74 int cpu_core_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
75 EXPORT_SYMBOL(cpu_core_id);
77 /* representing HT siblings of each logical CPU */
78 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
79 EXPORT_SYMBOL(cpu_sibling_map);
81 /* representing HT and core siblings of each logical CPU */
82 cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
83 EXPORT_SYMBOL(cpu_core_map);
85 /* bitmap of online cpus */
86 cpumask_t cpu_online_map __read_mostly;
87 EXPORT_SYMBOL(cpu_online_map);
89 cpumask_t cpu_callin_map;
90 cpumask_t cpu_callout_map;
91 EXPORT_SYMBOL(cpu_callout_map);
92 #ifdef CONFIG_HOTPLUG_CPU
93 cpumask_t cpu_possible_map = CPU_MASK_ALL;
95 cpumask_t cpu_possible_map;
97 EXPORT_SYMBOL(cpu_possible_map);
98 static cpumask_t smp_commenced_mask;
100 /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
101 * is no way to resync one AP against BP. TBD: for prescott and above, we
102 * should use IA64's algorithm
104 static int __devinitdata tsc_sync_disabled;
106 /* Per CPU bogomips and other parameters */
107 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
108 EXPORT_SYMBOL(cpu_data);
110 u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
111 { [0 ... NR_CPUS-1] = 0xff };
112 EXPORT_SYMBOL(x86_cpu_to_apicid);
115 * Trampoline 80x86 program as an array.
118 extern unsigned char trampoline_data [];
119 extern unsigned char trampoline_end [];
120 static unsigned char *trampoline_base;
121 static int trampoline_exec;
123 static void map_cpu_to_logical_apicid(void);
125 /* State of each CPU. */
126 DEFINE_PER_CPU(int, cpu_state) = { 0 };
129 * Currently trivial. Write the real->protected mode
130 * bootstrap into the page concerned. The caller
131 * has made sure it's suitably aligned.
134 static unsigned long __devinit setup_trampoline(void)
136 memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
137 return virt_to_phys(trampoline_base);
141 * We are called very early to get the low memory for the
142 * SMP bootup trampoline page.
144 void __init smp_alloc_memory(void)
146 trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
148 * Has to be in very low memory so we can execute
151 if (__pa(trampoline_base) >= 0x9F000)
154 * Make the SMP trampoline executable:
156 trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1);
160 * The bootstrap kernel entry code has set these up. Save them for
164 static void __devinit smp_store_cpu_info(int id)
166 struct cpuinfo_x86 *c = cpu_data + id;
172 * Mask B, Pentium, but not Pentium MMX
174 if (c->x86_vendor == X86_VENDOR_INTEL &&
176 c->x86_mask >= 1 && c->x86_mask <= 4 &&
179 * Remember we have B step Pentia with bugs
184 * Certain Athlons might work (for various values of 'work') in SMP
185 * but they are not certified as MP capable.
187 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
189 /* Athlon 660/661 is valid. */
190 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
193 /* Duron 670 is valid */
194 if ((c->x86_model==7) && (c->x86_mask==0))
198 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
199 * It's worth noting that the A5 stepping (662) of some Athlon XP's
200 * have the MP bit set.
201 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
203 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
204 ((c->x86_model==7) && (c->x86_mask>=1)) ||
209 /* If we get here, it's not a certified SMP capable AMD system. */
210 add_taint(TAINT_UNSAFE_SMP);
218 * TSC synchronization.
220 * We first check whether all CPUs have their TSC's synchronized,
221 * then we print a warning if not, and always resync.
224 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
225 static atomic_t tsc_count_start = ATOMIC_INIT(0);
226 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
227 static unsigned long long tsc_values[NR_CPUS];
231 static void __init synchronize_tsc_bp (void)
234 unsigned long long t0;
235 unsigned long long sum, avg;
237 unsigned int one_usec;
240 printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus());
242 /* convert from kcyc/sec to cyc/usec */
243 one_usec = cpu_khz / 1000;
245 atomic_set(&tsc_start_flag, 1);
249 * We loop a few times to get a primed instruction cache,
250 * then the last pass is more or less synchronized and
251 * the BP and APs set their cycle counters to zero all at
252 * once. This reduces the chance of having random offsets
253 * between the processors, and guarantees that the maximum
254 * delay between the cycle counters is never bigger than
255 * the latency of information-passing (cachelines) between
258 for (i = 0; i < NR_LOOPS; i++) {
260 * all APs synchronize but they loop on '== num_cpus'
262 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1)
264 atomic_set(&tsc_count_stop, 0);
267 * this lets the APs save their current TSC:
269 atomic_inc(&tsc_count_start);
271 rdtscll(tsc_values[smp_processor_id()]);
273 * We clear the TSC in the last loop:
279 * Wait for all APs to leave the synchronization point:
281 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1)
283 atomic_set(&tsc_count_start, 0);
285 atomic_inc(&tsc_count_stop);
289 for (i = 0; i < NR_CPUS; i++) {
290 if (cpu_isset(i, cpu_callout_map)) {
296 do_div(avg, num_booting_cpus());
299 for (i = 0; i < NR_CPUS; i++) {
300 if (!cpu_isset(i, cpu_callout_map))
302 delta = tsc_values[i] - avg;
306 * We report bigger than 2 microseconds clock differences.
308 if (delta > 2*one_usec) {
315 do_div(realdelta, one_usec);
316 if (tsc_values[i] < avg)
317 realdelta = -realdelta;
319 printk(KERN_INFO "CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta);
328 static void __init synchronize_tsc_ap (void)
333 * Not every cpu is online at the time
334 * this gets called, so we first wait for the BP to
335 * finish SMP initialization:
337 while (!atomic_read(&tsc_start_flag)) mb();
339 for (i = 0; i < NR_LOOPS; i++) {
340 atomic_inc(&tsc_count_start);
341 while (atomic_read(&tsc_count_start) != num_booting_cpus())
344 rdtscll(tsc_values[smp_processor_id()]);
348 atomic_inc(&tsc_count_stop);
349 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
354 extern void calibrate_delay(void);
356 static atomic_t init_deasserted;
358 static void __devinit smp_callin(void)
361 unsigned long timeout;
364 * If waken up by an INIT in an 82489DX configuration
365 * we may get here before an INIT-deassert IPI reaches
366 * our local APIC. We have to wait for the IPI or we'll
367 * lock up on an APIC access.
369 wait_for_init_deassert(&init_deasserted);
372 * (This works even if the APIC is not enabled.)
374 phys_id = GET_APIC_ID(apic_read(APIC_ID));
375 cpuid = smp_processor_id();
376 if (cpu_isset(cpuid, cpu_callin_map)) {
377 printk("huh, phys CPU#%d, CPU#%d already present??\n",
381 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
384 * STARTUP IPIs are fragile beasts as they might sometimes
385 * trigger some glue motherboard logic. Complete APIC bus
386 * silence for 1 second, this overestimates the time the
387 * boot CPU is spending to send the up to 2 STARTUP IPIs
388 * by a factor of two. This should be enough.
392 * Waiting 2s total for startup (udelay is not yet working)
394 timeout = jiffies + 2*HZ;
395 while (time_before(jiffies, timeout)) {
397 * Has the boot CPU finished it's STARTUP sequence?
399 if (cpu_isset(cpuid, cpu_callout_map))
404 if (!time_before(jiffies, timeout)) {
405 printk("BUG: CPU%d started up but did not get a callout!\n",
411 * the boot CPU has finished the init stage and is spinning
412 * on callin_map until we finish. We are free to set up this
413 * CPU, first the APIC. (this is probably redundant on most
417 Dprintk("CALLIN, before setup_local_APIC().\n");
418 smp_callin_clear_local_apic();
420 map_cpu_to_logical_apicid();
426 Dprintk("Stack at about %p\n",&cpuid);
429 * Save our processor parameters
431 smp_store_cpu_info(cpuid);
433 disable_APIC_timer();
436 * Allow the master to continue.
438 cpu_set(cpuid, cpu_callin_map);
441 * Synchronize the TSC with the BP
443 if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled)
444 synchronize_tsc_ap();
449 /* representing cpus for which sibling maps can be computed */
450 static cpumask_t cpu_sibling_setup_map;
453 set_cpu_sibling_map(int cpu)
456 struct cpuinfo_x86 *c = cpu_data;
458 cpu_set(cpu, cpu_sibling_setup_map);
460 if (smp_num_siblings > 1) {
461 for_each_cpu_mask(i, cpu_sibling_setup_map) {
462 if (phys_proc_id[cpu] == phys_proc_id[i] &&
463 cpu_core_id[cpu] == cpu_core_id[i]) {
464 cpu_set(i, cpu_sibling_map[cpu]);
465 cpu_set(cpu, cpu_sibling_map[i]);
466 cpu_set(i, cpu_core_map[cpu]);
467 cpu_set(cpu, cpu_core_map[i]);
471 cpu_set(cpu, cpu_sibling_map[cpu]);
474 if (current_cpu_data.x86_max_cores == 1) {
475 cpu_core_map[cpu] = cpu_sibling_map[cpu];
476 c[cpu].booted_cores = 1;
480 for_each_cpu_mask(i, cpu_sibling_setup_map) {
481 if (phys_proc_id[cpu] == phys_proc_id[i]) {
482 cpu_set(i, cpu_core_map[cpu]);
483 cpu_set(cpu, cpu_core_map[i]);
485 * Does this new cpu bringup a new core?
487 if (cpus_weight(cpu_sibling_map[cpu]) == 1) {
489 * for each core in package, increment
490 * the booted_cores for this new cpu
492 if (first_cpu(cpu_sibling_map[i]) == i)
493 c[cpu].booted_cores++;
495 * increment the core count for all
496 * the other cpus in this package
500 } else if (i != cpu && !c[cpu].booted_cores)
501 c[cpu].booted_cores = c[i].booted_cores;
507 * Activate a secondary processor.
509 static void __devinit start_secondary(void *unused)
512 * Dont put anything before smp_callin(), SMP
513 * booting is too fragile that we want to limit the
514 * things done here to the most necessary things.
518 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
520 setup_secondary_APIC_clock();
521 if (nmi_watchdog == NMI_IO_APIC) {
522 disable_8259A_irq(0);
523 enable_NMI_through_LVT0(NULL);
528 * low-memory mappings have been cleared, flush them from
529 * the local TLBs too.
533 /* This must be done before setting cpu_online_map */
534 set_cpu_sibling_map(raw_smp_processor_id());
538 * We need to hold call_lock, so there is no inconsistency
539 * between the time smp_call_function() determines number of
540 * IPI receipients, and the time when the determination is made
541 * for which cpus receive the IPI. Holding this
542 * lock helps us to not include this cpu in a currently in progress
543 * smp_call_function().
545 lock_ipi_call_lock();
546 cpu_set(smp_processor_id(), cpu_online_map);
547 unlock_ipi_call_lock();
548 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
550 /* We can take interrupts now: we're officially "up". */
558 * Everything has been set up for the secondary
559 * CPUs - they just need to reload everything
560 * from the task structure
561 * This function must not return.
563 void __devinit initialize_secondary(void)
566 * We don't actually need to load the full TSS,
567 * basically just the stack pointer and the eip.
574 :"r" (current->thread.esp),"r" (current->thread.eip));
584 /* which logical CPUs are on which nodes */
585 cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly =
586 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
587 /* which node each logical CPU is on */
588 int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
589 EXPORT_SYMBOL(cpu_2_node);
591 /* set up a mapping between cpu and node. */
592 static inline void map_cpu_to_node(int cpu, int node)
594 printk("Mapping cpu %d to node %d\n", cpu, node);
595 cpu_set(cpu, node_2_cpu_mask[node]);
596 cpu_2_node[cpu] = node;
599 /* undo a mapping between cpu and node. */
600 static inline void unmap_cpu_to_node(int cpu)
604 printk("Unmapping cpu %d from all nodes\n", cpu);
605 for (node = 0; node < MAX_NUMNODES; node ++)
606 cpu_clear(cpu, node_2_cpu_mask[node]);
609 #else /* !CONFIG_NUMA */
611 #define map_cpu_to_node(cpu, node) ({})
612 #define unmap_cpu_to_node(cpu) ({})
614 #endif /* CONFIG_NUMA */
616 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
618 static void map_cpu_to_logical_apicid(void)
620 int cpu = smp_processor_id();
621 int apicid = logical_smp_processor_id();
623 cpu_2_logical_apicid[cpu] = apicid;
624 map_cpu_to_node(cpu, apicid_to_node(apicid));
627 static void unmap_cpu_to_logical_apicid(int cpu)
629 cpu_2_logical_apicid[cpu] = BAD_APICID;
630 unmap_cpu_to_node(cpu);
634 static inline void __inquire_remote_apic(int apicid)
636 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
637 char *names[] = { "ID", "VERSION", "SPIV" };
640 printk("Inquiring remote APIC #%d...\n", apicid);
642 for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
643 printk("... APIC #%d %s: ", apicid, names[i]);
648 apic_wait_icr_idle();
650 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
651 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
656 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
657 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
660 case APIC_ICR_RR_VALID:
661 status = apic_read(APIC_RRR);
662 printk("%08x\n", status);
671 #ifdef WAKE_SECONDARY_VIA_NMI
673 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
674 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
675 * won't ... remember to clear down the APIC, etc later.
678 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
680 unsigned long send_status = 0, accept_status = 0;
684 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
686 /* Boot on the stack */
687 /* Kick the second */
688 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
690 Dprintk("Waiting for send to finish...\n");
695 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
696 } while (send_status && (timeout++ < 1000));
699 * Give the other CPU some time to accept the IPI.
703 * Due to the Pentium erratum 3AP.
705 maxlvt = get_maxlvt();
707 apic_read_around(APIC_SPIV);
708 apic_write(APIC_ESR, 0);
710 accept_status = (apic_read(APIC_ESR) & 0xEF);
711 Dprintk("NMI sent.\n");
714 printk("APIC never delivered???\n");
716 printk("APIC delivery error (%lx).\n", accept_status);
718 return (send_status | accept_status);
720 #endif /* WAKE_SECONDARY_VIA_NMI */
722 #ifdef WAKE_SECONDARY_VIA_INIT
724 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
726 unsigned long send_status = 0, accept_status = 0;
727 int maxlvt, timeout, num_starts, j;
730 * Be paranoid about clearing APIC errors.
732 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
733 apic_read_around(APIC_SPIV);
734 apic_write(APIC_ESR, 0);
738 Dprintk("Asserting INIT.\n");
741 * Turn INIT on target chip
743 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
748 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
751 Dprintk("Waiting for send to finish...\n");
756 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
757 } while (send_status && (timeout++ < 1000));
761 Dprintk("Deasserting INIT.\n");
764 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
767 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
769 Dprintk("Waiting for send to finish...\n");
774 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
775 } while (send_status && (timeout++ < 1000));
777 atomic_set(&init_deasserted, 1);
780 * Should we send STARTUP IPIs ?
782 * Determine this based on the APIC version.
783 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
785 if (APIC_INTEGRATED(apic_version[phys_apicid]))
791 * Run STARTUP IPI loop.
793 Dprintk("#startup loops: %d.\n", num_starts);
795 maxlvt = get_maxlvt();
797 for (j = 1; j <= num_starts; j++) {
798 Dprintk("Sending STARTUP #%d.\n",j);
799 apic_read_around(APIC_SPIV);
800 apic_write(APIC_ESR, 0);
802 Dprintk("After apic_write.\n");
809 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
811 /* Boot on the stack */
812 /* Kick the second */
813 apic_write_around(APIC_ICR, APIC_DM_STARTUP
814 | (start_eip >> 12));
817 * Give the other CPU some time to accept the IPI.
821 Dprintk("Startup point 1.\n");
823 Dprintk("Waiting for send to finish...\n");
828 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
829 } while (send_status && (timeout++ < 1000));
832 * Give the other CPU some time to accept the IPI.
836 * Due to the Pentium erratum 3AP.
839 apic_read_around(APIC_SPIV);
840 apic_write(APIC_ESR, 0);
842 accept_status = (apic_read(APIC_ESR) & 0xEF);
843 if (send_status || accept_status)
846 Dprintk("After Startup.\n");
849 printk("APIC never delivered???\n");
851 printk("APIC delivery error (%lx).\n", accept_status);
853 return (send_status | accept_status);
855 #endif /* WAKE_SECONDARY_VIA_INIT */
857 extern cpumask_t cpu_initialized;
858 static inline int alloc_cpu_id(void)
862 cpus_complement(tmp_map, cpu_present_map);
863 cpu = first_cpu(tmp_map);
869 #ifdef CONFIG_HOTPLUG_CPU
870 static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS];
871 static inline struct task_struct * alloc_idle_task(int cpu)
873 struct task_struct *idle;
875 if ((idle = cpu_idle_tasks[cpu]) != NULL) {
876 /* initialize thread_struct. we really want to avoid destroy
879 idle->thread.esp = (unsigned long)(((struct pt_regs *)
880 (THREAD_SIZE + (unsigned long) idle->thread_info)) - 1);
881 init_idle(idle, cpu);
884 idle = fork_idle(cpu);
887 cpu_idle_tasks[cpu] = idle;
891 #define alloc_idle_task(cpu) fork_idle(cpu)
894 static int __devinit do_boot_cpu(int apicid, int cpu)
896 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
897 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
898 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
901 struct task_struct *idle;
902 unsigned long boot_error;
904 unsigned long start_eip;
905 unsigned short nmi_high = 0, nmi_low = 0;
910 * We can't use kernel_thread since we must avoid to
911 * reschedule the child.
913 idle = alloc_idle_task(cpu);
915 panic("failed fork for CPU %d", cpu);
916 idle->thread.eip = (unsigned long) start_secondary;
917 /* start_eip had better be page-aligned! */
918 start_eip = setup_trampoline();
920 /* So we see what's up */
921 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
922 /* Stack for startup_32 can be just as for start_secondary onwards */
923 stack_start.esp = (void *) idle->thread.esp;
928 * This grunge runs the startup process for
929 * the targeted processor.
932 atomic_set(&init_deasserted, 0);
934 Dprintk("Setting warm reset code and vector.\n");
936 store_NMI_vector(&nmi_high, &nmi_low);
938 smpboot_setup_warm_reset_vector(start_eip);
941 * Starting actual IPI sequence...
943 boot_error = wakeup_secondary_cpu(apicid, start_eip);
947 * allow APs to start initializing.
949 Dprintk("Before Callout %d.\n", cpu);
950 cpu_set(cpu, cpu_callout_map);
951 Dprintk("After Callout %d.\n", cpu);
954 * Wait 5s total for a response
956 for (timeout = 0; timeout < 50000; timeout++) {
957 if (cpu_isset(cpu, cpu_callin_map))
958 break; /* It has booted */
962 if (cpu_isset(cpu, cpu_callin_map)) {
963 /* number CPUs logically, starting from 1 (BSP is 0) */
965 printk("CPU%d: ", cpu);
966 print_cpu_info(&cpu_data[cpu]);
967 Dprintk("CPU has booted.\n");
970 if (*((volatile unsigned char *)trampoline_base)
972 /* trampoline started but...? */
973 printk("Stuck ??\n");
975 /* trampoline code not run */
976 printk("Not responding.\n");
977 inquire_remote_apic(apicid);
982 /* Try to put things back the way they were before ... */
983 unmap_cpu_to_logical_apicid(cpu);
984 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
985 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
988 x86_cpu_to_apicid[cpu] = apicid;
989 cpu_set(cpu, cpu_present_map);
992 /* mark "stuck" area as not stuck */
993 *((volatile unsigned long *)trampoline_base) = 0;
998 #ifdef CONFIG_HOTPLUG_CPU
999 void cpu_exit_clear(void)
1001 int cpu = raw_smp_processor_id();
1009 cpu_clear(cpu, cpu_callout_map);
1010 cpu_clear(cpu, cpu_callin_map);
1011 cpu_clear(cpu, cpu_present_map);
1013 cpu_clear(cpu, smp_commenced_mask);
1014 unmap_cpu_to_logical_apicid(cpu);
1017 struct warm_boot_cpu_info {
1018 struct completion *complete;
1023 static void __devinit do_warm_boot_cpu(void *p)
1025 struct warm_boot_cpu_info *info = p;
1026 do_boot_cpu(info->apicid, info->cpu);
1027 complete(info->complete);
1030 int __devinit smp_prepare_cpu(int cpu)
1032 DECLARE_COMPLETION(done);
1033 struct warm_boot_cpu_info info;
1034 struct work_struct task;
1038 apicid = x86_cpu_to_apicid[cpu];
1039 if (apicid == BAD_APICID) {
1044 info.complete = &done;
1045 info.apicid = apicid;
1047 INIT_WORK(&task, do_warm_boot_cpu, &info);
1049 tsc_sync_disabled = 1;
1051 /* init low mem mapping */
1052 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
1055 schedule_work(&task);
1056 wait_for_completion(&done);
1058 tsc_sync_disabled = 0;
1062 unlock_cpu_hotplug();
1067 static void smp_tune_scheduling (void)
1069 unsigned long cachesize; /* kB */
1070 unsigned long bandwidth = 350; /* MB/s */
1072 * Rough estimation for SMP scheduling, this is the number of
1073 * cycles it takes for a fully memory-limited process to flush
1074 * the SMP-local cache.
1076 * (For a P5 this pretty much means we will choose another idle
1077 * CPU almost always at wakeup time (this is due to the small
1078 * L1 cache), on PIIs it's around 50-100 usecs, depending on
1084 * this basically disables processor-affinity
1085 * scheduling on SMP without a TSC.
1089 cachesize = boot_cpu_data.x86_cache_size;
1090 if (cachesize == -1) {
1091 cachesize = 16; /* Pentiums, 2x8kB cache */
1098 * Cycle through the processors sending APIC IPIs to boot each.
1101 static int boot_cpu_logical_apicid;
1102 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1104 #ifdef CONFIG_X86_NUMAQ
1105 EXPORT_SYMBOL(xquad_portio);
1108 static void __init smp_boot_cpus(unsigned int max_cpus)
1110 int apicid, cpu, bit, kicked;
1111 unsigned long bogosum = 0;
1114 * Setup boot CPU information
1116 smp_store_cpu_info(0); /* Final full version of the data */
1117 printk("CPU%d: ", 0);
1118 print_cpu_info(&cpu_data[0]);
1120 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
1121 boot_cpu_logical_apicid = logical_smp_processor_id();
1122 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
1124 current_thread_info()->cpu = 0;
1125 smp_tune_scheduling();
1127 set_cpu_sibling_map(0);
1130 * If we couldn't find an SMP configuration at boot time,
1131 * get out of here now!
1133 if (!smp_found_config && !acpi_lapic) {
1134 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1135 smpboot_clear_io_apic_irqs();
1136 phys_cpu_present_map = physid_mask_of_physid(0);
1137 if (APIC_init_uniprocessor())
1138 printk(KERN_NOTICE "Local APIC not detected."
1139 " Using dummy APIC emulation.\n");
1140 map_cpu_to_logical_apicid();
1141 cpu_set(0, cpu_sibling_map[0]);
1142 cpu_set(0, cpu_core_map[0]);
1147 * Should not be necessary because the MP table should list the boot
1148 * CPU too, but we do it for the sake of robustness anyway.
1149 * Makes no sense to do this check in clustered apic mode, so skip it
1151 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1152 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1153 boot_cpu_physical_apicid);
1154 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1158 * If we couldn't find a local APIC, then get out of here now!
1160 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
1161 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1162 boot_cpu_physical_apicid);
1163 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1164 smpboot_clear_io_apic_irqs();
1165 phys_cpu_present_map = physid_mask_of_physid(0);
1166 cpu_set(0, cpu_sibling_map[0]);
1167 cpu_set(0, cpu_core_map[0]);
1171 verify_local_APIC();
1174 * If SMP should be disabled, then really disable it!
1177 smp_found_config = 0;
1178 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1179 smpboot_clear_io_apic_irqs();
1180 phys_cpu_present_map = physid_mask_of_physid(0);
1181 cpu_set(0, cpu_sibling_map[0]);
1182 cpu_set(0, cpu_core_map[0]);
1188 map_cpu_to_logical_apicid();
1191 setup_portio_remap();
1194 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1196 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1197 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1198 * clustered apic ID.
1200 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
1203 for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
1204 apicid = cpu_present_to_apicid(bit);
1206 * Don't even attempt to start the boot CPU!
1208 if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
1211 if (!check_apicid_present(bit))
1213 if (max_cpus <= cpucount+1)
1216 if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu))
1217 printk("CPU #%d not responding - cannot use it.\n",
1224 * Cleanup possible dangling ends...
1226 smpboot_restore_warm_reset_vector();
1229 * Allow the user to impress friends.
1231 Dprintk("Before bogomips.\n");
1232 for (cpu = 0; cpu < NR_CPUS; cpu++)
1233 if (cpu_isset(cpu, cpu_callout_map))
1234 bogosum += cpu_data[cpu].loops_per_jiffy;
1236 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1238 bogosum/(500000/HZ),
1239 (bogosum/(5000/HZ))%100);
1241 Dprintk("Before bogocount - setting activated=1.\n");
1244 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1247 * Don't taint if we are running SMP kernel on a single non-MP
1250 if (tainted & TAINT_UNSAFE_SMP) {
1252 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
1254 tainted &= ~TAINT_UNSAFE_SMP;
1257 Dprintk("Boot done.\n");
1260 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1263 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1264 cpus_clear(cpu_sibling_map[cpu]);
1265 cpus_clear(cpu_core_map[cpu]);
1268 cpu_set(0, cpu_sibling_map[0]);
1269 cpu_set(0, cpu_core_map[0]);
1271 smpboot_setup_io_apic();
1273 setup_boot_APIC_clock();
1276 * Synchronize the TSC with the AP
1278 if (cpu_has_tsc && cpucount && cpu_khz)
1279 synchronize_tsc_bp();
1282 /* These are wrappers to interface to the new boot process. Someone
1283 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1284 void __init smp_prepare_cpus(unsigned int max_cpus)
1286 smp_commenced_mask = cpumask_of_cpu(0);
1287 cpu_callin_map = cpumask_of_cpu(0);
1289 smp_boot_cpus(max_cpus);
1292 void __devinit smp_prepare_boot_cpu(void)
1294 cpu_set(smp_processor_id(), cpu_online_map);
1295 cpu_set(smp_processor_id(), cpu_callout_map);
1296 cpu_set(smp_processor_id(), cpu_present_map);
1297 cpu_set(smp_processor_id(), cpu_possible_map);
1298 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
1301 #ifdef CONFIG_HOTPLUG_CPU
1303 remove_siblinginfo(int cpu)
1306 struct cpuinfo_x86 *c = cpu_data;
1308 for_each_cpu_mask(sibling, cpu_core_map[cpu]) {
1309 cpu_clear(cpu, cpu_core_map[sibling]);
1311 * last thread sibling in this cpu core going down
1313 if (cpus_weight(cpu_sibling_map[cpu]) == 1)
1314 c[sibling].booted_cores--;
1317 for_each_cpu_mask(sibling, cpu_sibling_map[cpu])
1318 cpu_clear(cpu, cpu_sibling_map[sibling]);
1319 cpus_clear(cpu_sibling_map[cpu]);
1320 cpus_clear(cpu_core_map[cpu]);
1321 phys_proc_id[cpu] = BAD_APICID;
1322 cpu_core_id[cpu] = BAD_APICID;
1323 cpu_clear(cpu, cpu_sibling_setup_map);
1326 int __cpu_disable(void)
1328 cpumask_t map = cpu_online_map;
1329 int cpu = smp_processor_id();
1332 * Perhaps use cpufreq to drop frequency, but that could go
1333 * into generic code.
1335 * We won't take down the boot processor on i386 due to some
1336 * interrupts only being able to be serviced by the BSP.
1337 * Especially so if we're not using an IOAPIC -zwane
1342 /* We enable the timer again on the exit path of the death loop */
1343 disable_APIC_timer();
1344 /* Allow any queued timer interrupts to get serviced */
1347 local_irq_disable();
1349 remove_siblinginfo(cpu);
1351 cpu_clear(cpu, map);
1353 /* It's now safe to remove this processor from the online map */
1354 cpu_clear(cpu, cpu_online_map);
1358 void __cpu_die(unsigned int cpu)
1360 /* We don't do anything here: idle task is faking death itself. */
1363 for (i = 0; i < 10; i++) {
1364 /* They ack this in play_dead by setting CPU_DEAD */
1365 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1366 printk ("CPU %d is now offline\n", cpu);
1371 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1373 #else /* ... !CONFIG_HOTPLUG_CPU */
1374 int __cpu_disable(void)
1379 void __cpu_die(unsigned int cpu)
1381 /* We said "no" in __cpu_disable */
1384 #endif /* CONFIG_HOTPLUG_CPU */
1386 int __devinit __cpu_up(unsigned int cpu)
1388 /* In case one didn't come up */
1389 if (!cpu_isset(cpu, cpu_callin_map)) {
1390 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1396 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1397 /* Unleash the CPU! */
1398 cpu_set(cpu, smp_commenced_mask);
1399 while (!cpu_isset(cpu, cpu_online_map))
1404 void __init smp_cpus_done(unsigned int max_cpus)
1406 #ifdef CONFIG_X86_IO_APIC
1407 setup_ioapic_dest();
1410 #ifndef CONFIG_HOTPLUG_CPU
1412 * Disable executability of the SMP trampoline:
1414 set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
1418 void __init smp_intr_init(void)
1421 * IRQ0 must be given a fixed assignment and initialized,
1422 * because it's used before the IO-APIC is set up.
1424 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
1427 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1428 * IPI, driven by wakeup.
1430 set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
1432 /* IPI for invalidation */
1433 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1435 /* IPI for generic function call */
1436 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);