1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __clkgen_defs_h
3 #define __clkgen_defs_h
6 * This file is autogenerated from
9 * by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r
10 * Any changes here will be lost.
12 * -*- buffer-read-only: t -*-
14 /* Main access macros */
16 #define REG_RD( scope, inst, reg ) \
17 REG_READ( reg_##scope##_##reg, \
18 (inst) + REG_RD_ADDR_##scope##_##reg )
22 #define REG_WR( scope, inst, reg, val ) \
23 REG_WRITE( reg_##scope##_##reg, \
24 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28 #define REG_RD_VECT( scope, inst, reg, index ) \
29 REG_READ( reg_##scope##_##reg, \
30 (inst) + REG_RD_ADDR_##scope##_##reg + \
31 (index) * STRIDE_##scope##_##reg )
35 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 REG_WRITE( reg_##scope##_##reg, \
37 (inst) + REG_WR_ADDR_##scope##_##reg + \
38 (index) * STRIDE_##scope##_##reg, (val) )
42 #define REG_RD_INT( scope, inst, reg ) \
43 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
47 #define REG_WR_INT( scope, inst, reg, val ) \
48 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #ifndef REG_RD_INT_VECT
52 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
53 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
54 (index) * STRIDE_##scope##_##reg )
57 #ifndef REG_WR_INT_VECT
58 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
59 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
60 (index) * STRIDE_##scope##_##reg, (val) )
64 #define REG_TYPE_CONV( type, orgtype, val ) \
65 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
69 #define reg_page_size 8192
73 #define REG_ADDR( scope, inst, reg ) \
74 ( (inst) + REG_RD_ADDR_##scope##_##reg )
78 #define REG_ADDR_VECT( scope, inst, reg, index ) \
79 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
80 (index) * STRIDE_##scope##_##reg )
83 /* C-code for register scope clkgen */
85 /* Register r_bootsel, scope clkgen, type r */
87 unsigned int boot_mode : 5;
88 unsigned int intern_main_clk : 1;
89 unsigned int extern_usb2_clk : 1;
90 unsigned int dummy1 : 25;
91 } reg_clkgen_r_bootsel;
92 #define REG_RD_ADDR_clkgen_r_bootsel 0
94 /* Register rw_clk_ctrl, scope clkgen, type rw */
98 unsigned int iop_usb : 1;
100 unsigned int sclr : 1;
101 unsigned int h264 : 1;
102 unsigned int ddr2 : 1;
103 unsigned int vout_hist : 1;
104 unsigned int eth : 1;
105 unsigned int ccd_tg_200 : 1;
106 unsigned int dma0_1_eth : 1;
107 unsigned int ccd_tg_100 : 1;
108 unsigned int jpeg : 1;
109 unsigned int sser_ser_dma6_7 : 1;
110 unsigned int strdma0_2_video : 1;
111 unsigned int dma2_3_strcop : 1;
112 unsigned int dma4_5_iop : 1;
113 unsigned int dma9_11 : 1;
114 unsigned int memarb_bar_ddr : 1;
115 unsigned int sclr_h264 : 1;
116 unsigned int dummy1 : 12;
117 } reg_clkgen_rw_clk_ctrl;
118 #define REG_RD_ADDR_clkgen_rw_clk_ctrl 4
119 #define REG_WR_ADDR_clkgen_rw_clk_ctrl 4
124 regk_clkgen_eth1000_rx = 0x0000000c,
125 regk_clkgen_eth1000_tx = 0x0000000e,
126 regk_clkgen_eth100_rx = 0x0000001d,
127 regk_clkgen_eth100_rx_half = 0x0000001c,
128 regk_clkgen_eth100_tx = 0x0000001f,
129 regk_clkgen_eth100_tx_half = 0x0000001e,
130 regk_clkgen_nand_3_2 = 0x00000000,
131 regk_clkgen_nand_3_2_0x30 = 0x00000002,
132 regk_clkgen_nand_3_2_0x30_pll = 0x00000012,
133 regk_clkgen_nand_3_2_pll = 0x00000010,
134 regk_clkgen_nand_3_3 = 0x00000001,
135 regk_clkgen_nand_3_3_0x30 = 0x00000003,
136 regk_clkgen_nand_3_3_0x30_pll = 0x00000013,
137 regk_clkgen_nand_3_3_pll = 0x00000011,
138 regk_clkgen_nand_4_2 = 0x00000004,
139 regk_clkgen_nand_4_2_0x30 = 0x00000006,
140 regk_clkgen_nand_4_2_0x30_pll = 0x00000016,
141 regk_clkgen_nand_4_2_pll = 0x00000014,
142 regk_clkgen_nand_4_3 = 0x00000005,
143 regk_clkgen_nand_4_3_0x30 = 0x00000007,
144 regk_clkgen_nand_4_3_0x30_pll = 0x00000017,
145 regk_clkgen_nand_4_3_pll = 0x00000015,
146 regk_clkgen_nand_5_2 = 0x00000008,
147 regk_clkgen_nand_5_2_0x30 = 0x0000000a,
148 regk_clkgen_nand_5_2_0x30_pll = 0x0000001a,
149 regk_clkgen_nand_5_2_pll = 0x00000018,
150 regk_clkgen_nand_5_3 = 0x00000009,
151 regk_clkgen_nand_5_3_0x30 = 0x0000000b,
152 regk_clkgen_nand_5_3_0x30_pll = 0x0000001b,
153 regk_clkgen_nand_5_3_pll = 0x00000019,
154 regk_clkgen_no = 0x00000000,
155 regk_clkgen_rw_clk_ctrl_default = 0x00000002,
156 regk_clkgen_ser = 0x0000000d,
157 regk_clkgen_ser_pll = 0x0000000f,
158 regk_clkgen_yes = 0x00000001
160 #endif /* __clkgen_defs_h */