1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* ************************************************************************* */
3 /* This file is autogenerated by IOPASM Version 1.2 */
4 /* DO NOT EDIT THIS FILE - All changes will be lost! */
5 /* ************************************************************************* */
9 #ifndef __IOP_MPU_MACROS_H__
10 #define __IOP_MPU_MACROS_H__
13 /* ************************************************************************* */
14 /* REGISTER DEFINITIONS */
15 /* ************************************************************************* */
33 #define MPU_WSTS (0x3)
34 #define MPU_JADDR (0x4)
51 #define MPU_I10 (0x1a)
52 #define MPU_I11 (0x1b)
53 #define MPU_I12 (0x1c)
54 #define MPU_I13 (0x1d)
55 #define MPU_I14 (0x1e)
56 #define MPU_I15 (0x1f)
65 #define MPU_P16 (0x10)
66 #define MPU_P17 (0x12)
67 #define MPU_P18 (0x12)
68 #define MPU_P19 (0x13)
69 #define MPU_P20 (0x14)
70 #define MPU_P21 (0x15)
71 #define MPU_P22 (0x16)
72 #define MPU_P23 (0x17)
73 #define MPU_P24 (0x18)
74 #define MPU_P25 (0x19)
75 #define MPU_P26 (0x1a)
76 #define MPU_P27 (0x1b)
77 #define MPU_P28 (0x1c)
78 #define MPU_P29 (0x1d)
79 #define MPU_P30 (0x1e)
80 #define MPU_P31 (0x1f)
82 #define MPU_REGA (0x1)
86 /* ************************************************************************* */
88 /* ************************************************************************* */
89 #define MK_DWORD_ADDR(ADDR) (ADDR >> 2)
90 #define MK_BYTE_ADDR(ADDR) (ADDR)
94 /* ************************************************************************* */
95 /* INSTRUCTION MACROS */
96 /* ************************************************************************* */
97 #define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\
98 | ((N & ((1 << 5) - 1)) << 11)\
99 | ((D & ((1 << 5) - 1)) << 21))
101 #define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\
102 | ((N & ((1 << 5) - 1)) << 11)\
103 | ((D & ((1 << 5) - 1)) << 21))
105 #define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\
106 | ((N & ((1 << 5) - 1)) << 11)\
107 | ((D & ((1 << 5) - 1)) << 21))
109 #define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\
110 | ((N & ((1 << 5) - 1)) << 11)\
111 | ((D & ((1 << 5) - 1)) << 21))
113 #define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\
114 | ((N & ((1 << 5) - 1)) << 11)\
115 | ((D & ((1 << 5) - 1)) << 21))
117 #define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\
118 | ((N & ((1 << 5) - 1)) << 11)\
119 | ((D & ((1 << 5) - 1)) << 21))
121 #define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\
122 | ((N & ((1 << 5) - 1)) << 11)\
123 | ((D & ((1 << 5) - 1)) << 21))
125 #define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\
126 | ((N & ((1 << 5) - 1)) << 11)\
127 | ((D & ((1 << 5) - 1)) << 21))
129 #define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\
130 | ((N & ((1 << 16) - 1)) << 0)\
131 | ((D & ((1 << 5) - 1)) << 21))
133 #define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\
134 | ((N & ((1 << 5) - 1)) << 16)\
135 | ((D & ((1 << 5) - 1)) << 21))
137 #define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\
138 | ((D & ((1 << 5) - 1)) << 21))
140 #define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
142 #define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\
143 | ((D & ((1 << 5) - 1)) << 21))
145 #define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
147 #define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\
148 | ((D & ((1 << 5) - 1)) << 21))
150 #define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
152 #define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\
153 | ((D & ((1 << 5) - 1)) << 21))
155 #define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
157 #define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\
158 | ((D & ((1 << 5) - 1)) << 21))
160 #define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
162 #define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\
163 | ((D & ((1 << 5) - 1)) << 21))
165 #define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
167 #define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\
168 | ((D & ((1 << 5) - 1)) << 21))
170 #define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
172 #define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\
173 | ((D & ((1 << 5) - 1)) << 21))
175 #define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
177 #define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\
178 | ((N & ((1 << 5) - 1)) << 11)\
179 | ((D & ((1 << 5) - 1)) << 21))
181 #define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\
182 | ((N & ((1 << 5) - 1)) << 11)\
183 | ((D & ((1 << 5) - 1)) << 21))
185 #define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\
186 | ((N & ((1 << 5) - 1)) << 11)\
187 | ((D & ((1 << 5) - 1)) << 21))
189 #define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\
190 | ((N & ((1 << 5) - 1)) << 11)\
191 | ((D & ((1 << 5) - 1)) << 21))
193 #define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\
194 | ((N & ((1 << 5) - 1)) << 11)\
195 | ((D & ((1 << 5) - 1)) << 21))
197 #define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\
198 | ((N & ((1 << 5) - 1)) << 11)\
199 | ((D & ((1 << 5) - 1)) << 21))
201 #define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\
202 | ((N & ((1 << 5) - 1)) << 11)\
203 | ((D & ((1 << 5) - 1)) << 21))
205 #define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\
206 | ((N & ((1 << 5) - 1)) << 11)\
207 | ((D & ((1 << 5) - 1)) << 21))
209 #define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\
210 | ((N & ((1 << 16) - 1)) << 0)\
211 | ((D & ((1 << 5) - 1)) << 21))
213 #define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\
214 | ((N & ((1 << 5) - 1)) << 16)\
215 | ((D & ((1 << 5) - 1)) << 21))
217 #define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\
218 | ((D & ((1 << 5) - 1)) << 21))
220 #define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
222 #define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\
223 | ((D & ((1 << 5) - 1)) << 21))
225 #define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
227 #define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\
228 | ((D & ((1 << 5) - 1)) << 21))
230 #define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
232 #define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\
233 | ((D & ((1 << 5) - 1)) << 21))
235 #define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
237 #define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\
238 | ((D & ((1 << 5) - 1)) << 21))
240 #define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
242 #define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\
243 | ((D & ((1 << 5) - 1)) << 21))
245 #define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
247 #define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\
248 | ((D & ((1 << 5) - 1)) << 21))
250 #define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
252 #define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\
253 | ((D & ((1 << 5) - 1)) << 21))
255 #define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
257 #define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0))
259 #define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11))
261 #define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11))
263 #define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\
264 | ((N & ((1 << 5) - 1)) << 21)\
265 | ((D & ((1 << 16) - 1)) << 0))
267 #define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\
268 | ((N & ((1 << 5) - 1)) << 21)\
269 | ((D & ((1 << 16) - 1)) << 0))
271 #define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\
272 | ((D & ((1 << 16) - 1)) << 0))
274 #define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\
275 | ((D & ((1 << 16) - 1)) << 0))
277 #define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\
278 | ((D & ((1 << 16) - 1)) << 0))
280 #define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\
281 | ((D & ((1 << 16) - 1)) << 0))
283 #define MPU_DI() (0x40000001)
285 #define MPU_EI() (0x40000003)
287 #define MPU_HALT() (0x40000002)
289 #define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0))
291 #define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11))
293 #define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11))
295 #define MPU_JNT() (0x61000000)
297 #define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0))
299 #define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11))
301 #define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11))
303 #define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\
304 | ((N & ((1 << 5) - 1)) << 11)\
305 | ((D & ((1 << 5) - 1)) << 21))
307 #define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\
308 | ((N & ((1 << 5) - 1)) << 11)\
309 | ((D & ((1 << 5) - 1)) << 21))
311 #define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\
312 | ((N & ((1 << 5) - 1)) << 11)\
313 | ((D & ((1 << 5) - 1)) << 21))
315 #define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\
316 | ((N & ((1 << 5) - 1)) << 11)\
317 | ((D & ((1 << 5) - 1)) << 21))
319 #define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\
320 | ((N & ((1 << 5) - 1)) << 11)\
321 | ((D & ((1 << 5) - 1)) << 21))
323 #define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\
324 | ((N & ((1 << 5) - 1)) << 11)\
325 | ((D & ((1 << 5) - 1)) << 21))
327 #define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\
328 | ((N & ((1 << 5) - 1)) << 11)\
329 | ((D & ((1 << 5) - 1)) << 21))
331 #define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\
332 | ((N & ((1 << 5) - 1)) << 11)\
333 | ((D & ((1 << 5) - 1)) << 21))
335 #define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\
336 | ((N & ((1 << 16) - 1)) << 0)\
337 | ((D & ((1 << 5) - 1)) << 21))
339 #define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\
340 | ((N & ((1 << 5) - 1)) << 11)\
341 | ((D & ((1 << 5) - 1)) << 21))
343 #define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\
344 | ((N & ((1 << 5) - 1)) << 11)\
345 | ((D & ((1 << 5) - 1)) << 21))
347 #define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\
348 | ((N & ((1 << 5) - 1)) << 11)\
349 | ((D & ((1 << 5) - 1)) << 21))
351 #define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\
352 | ((N & ((1 << 5) - 1)) << 11)\
353 | ((D & ((1 << 5) - 1)) << 21))
355 #define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\
356 | ((N & ((1 << 5) - 1)) << 11)\
357 | ((D & ((1 << 5) - 1)) << 21))
359 #define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\
360 | ((N & ((1 << 5) - 1)) << 11)\
361 | ((D & ((1 << 5) - 1)) << 21))
363 #define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\
364 | ((N & ((1 << 5) - 1)) << 11)\
365 | ((D & ((1 << 5) - 1)) << 21))
367 #define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\
368 | ((N & ((1 << 5) - 1)) << 11)\
369 | ((D & ((1 << 5) - 1)) << 21))
371 #define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\
372 | ((N & ((1 << 16) - 1)) << 0)\
373 | ((D & ((1 << 5) - 1)) << 21))
375 #define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\
376 | ((D & ((1 << 5) - 1)) << 16))
378 #define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\
379 | ((D & ((1 << 5) - 1)) << 16))
381 #define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
382 | ((D & ((1 << 5) - 1)) << 16))
384 #define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
385 | ((D & ((1 << 5) - 1)) << 16))
387 #define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
388 | ((D & ((1 << 5) - 1)) << 16))
390 #define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
391 | ((D & ((1 << 5) - 1)) << 16))
393 #define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
394 | ((N & ((1 << 8) - 1)) << 0)\
395 | ((D & ((1 << 5) - 1)) << 16))
397 #define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
398 | ((N & ((1 << 8) - 1)) << 0)\
399 | ((D & ((1 << 5) - 1)) << 16))
401 #define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
402 | ((N & ((1 << 8) - 1)) << 0)\
403 | ((D & ((1 << 5) - 1)) << 16))
405 #define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
406 | ((N & ((1 << 8) - 1)) << 0)\
407 | ((D & ((1 << 5) - 1)) << 16))
409 #define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\
410 | ((D & ((1 << 5) - 1)) << 21))
412 #define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\
413 | ((D & ((1 << 5) - 1)) << 21))
415 #define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\
416 | ((D & ((1 << 5) - 1)) << 21))
418 #define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\
419 | ((D & ((1 << 5) - 1)) << 21))
421 #define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\
422 | ((D & ((1 << 5) - 1)) << 21))
424 #define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\
425 | ((D & ((1 << 5) - 1)) << 21))
427 #define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21))
429 #define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF)
431 #define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21))
433 #define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF)
435 #define MPU_NOP() (0x40000000)
437 #define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\
438 | ((D & ((1 << 5) - 1)) << 21))
440 #define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\
441 | ((D & ((1 << 5) - 1)) << 21))
443 #define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\
444 | ((D & ((1 << 5) - 1)) << 21))
446 #define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\
447 | ((D & ((1 << 5) - 1)) << 21))
449 #define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\
450 | ((N & ((1 << 5) - 1)) << 11)\
451 | ((D & ((1 << 5) - 1)) << 21))
453 #define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\
454 | ((N & ((1 << 5) - 1)) << 11)\
455 | ((D & ((1 << 5) - 1)) << 21))
457 #define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\
458 | ((N & ((1 << 5) - 1)) << 11)\
459 | ((D & ((1 << 5) - 1)) << 21))
461 #define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\
462 | ((N & ((1 << 5) - 1)) << 11)\
463 | ((D & ((1 << 5) - 1)) << 21))
465 #define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\
466 | ((N & ((1 << 5) - 1)) << 11)\
467 | ((D & ((1 << 5) - 1)) << 21))
469 #define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\
470 | ((N & ((1 << 5) - 1)) << 11)\
471 | ((D & ((1 << 5) - 1)) << 21))
473 #define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\
474 | ((N & ((1 << 5) - 1)) << 11)\
475 | ((D & ((1 << 5) - 1)) << 21))
477 #define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\
478 | ((N & ((1 << 5) - 1)) << 11)\
479 | ((D & ((1 << 5) - 1)) << 21))
481 #define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\
482 | ((N & ((1 << 16) - 1)) << 0)\
483 | ((D & ((1 << 5) - 1)) << 21))
485 #define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\
486 | ((N & ((1 << 5) - 1)) << 16)\
487 | ((D & ((1 << 5) - 1)) << 21))
489 #define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\
490 | ((D & ((1 << 5) - 1)) << 21))
492 #define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
494 #define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\
495 | ((D & ((1 << 5) - 1)) << 21))
497 #define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
499 #define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\
500 | ((D & ((1 << 5) - 1)) << 21))
502 #define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
504 #define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\
505 | ((D & ((1 << 5) - 1)) << 21))
507 #define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
509 #define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\
510 | ((D & ((1 << 5) - 1)) << 21))
512 #define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
514 #define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\
515 | ((D & ((1 << 5) - 1)) << 21))
517 #define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
519 #define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\
520 | ((D & ((1 << 5) - 1)) << 21))
522 #define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
524 #define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\
525 | ((D & ((1 << 5) - 1)) << 21))
527 #define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
529 #define MPU_RET() (0x63003000)
531 #define MPU_RETI() (0x63602800)
533 #define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\
534 | ((D & ((1 << 5) - 1)) << 21))
536 #define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\
537 | ((D & ((1 << 5) - 1)) << 21))
539 #define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\
540 | ((D & ((1 << 11) - 1)) << 0))
542 #define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\
543 | ((D & ((1 << 5) - 1)) << 16))
545 #define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\
546 | ((D & ((1 << 11) - 1)) << 0))
548 #define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\
549 | ((D & ((1 << 5) - 1)) << 16))
551 #define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0))
553 #define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF)
555 #define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16))
557 #define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
559 #define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\
560 | ((N & ((1 << 5) - 1)) << 11)\
561 | ((D & ((1 << 5) - 1)) << 21))
563 #define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\
564 | ((N & ((1 << 5) - 1)) << 11)\
565 | ((D & ((1 << 5) - 1)) << 21))
567 #define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\
568 | ((N & ((1 << 5) - 1)) << 11)\
569 | ((D & ((1 << 5) - 1)) << 21))
571 #define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\
572 | ((N & ((1 << 5) - 1)) << 11)\
573 | ((D & ((1 << 5) - 1)) << 21))
575 #define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\
576 | ((N & ((1 << 5) - 1)) << 11)\
577 | ((D & ((1 << 5) - 1)) << 21))
579 #define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\
580 | ((N & ((1 << 5) - 1)) << 11)\
581 | ((D & ((1 << 5) - 1)) << 21))
583 #define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\
584 | ((N & ((1 << 5) - 1)) << 11)\
585 | ((D & ((1 << 5) - 1)) << 21))
587 #define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\
588 | ((N & ((1 << 5) - 1)) << 11)\
589 | ((D & ((1 << 5) - 1)) << 21))
591 #define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\
592 | ((N & ((1 << 16) - 1)) << 0)\
593 | ((D & ((1 << 5) - 1)) << 21))
595 #define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\
596 | ((D & ((1 << 5) - 1)) << 21))
598 #define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
600 #define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\
601 | ((D & ((1 << 5) - 1)) << 21))
603 #define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
605 #define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\
606 | ((D & ((1 << 5) - 1)) << 21))
608 #define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
610 #define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\
611 | ((D & ((1 << 5) - 1)) << 21))
613 #define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
615 #define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\
616 | ((D & ((1 << 16) - 1)) << 0))
618 #define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\
619 | ((D & ((1 << 16) - 1)) << 0))
621 #define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
622 | ((D & ((1 << 5) - 1)) << 11))
624 #define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
625 | ((D & ((1 << 5) - 1)) << 11))
627 #define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
628 | ((D & ((1 << 5) - 1)) << 11))
630 #define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
631 | ((D & ((1 << 5) - 1)) << 11))
633 #define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
634 | ((N & ((1 << 8) - 1)) << 0)\
635 | ((D & ((1 << 5) - 1)) << 11))
637 #define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
638 | ((N & ((1 << 8) - 1)) << 0)\
639 | ((D & ((1 << 5) - 1)) << 11))
641 #define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
642 | ((N & ((1 << 8) - 1)) << 0)\
643 | ((D & ((1 << 5) - 1)) << 11))
645 #define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
646 | ((N & ((1 << 8) - 1)) << 0)\
647 | ((D & ((1 << 5) - 1)) << 11))
649 #define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0))
651 #define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF)
653 #define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11))
655 #define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF)
657 #define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11))
659 #define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
661 #define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\
662 | ((D & ((1 << 5) - 1)) << 11))
664 #define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF)
666 #define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\
667 | ((D & ((1 << 5) - 1)) << 11))
669 #define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF)
671 #define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\
672 | ((N & ((1 << 5) - 1)) << 11)\
673 | ((D & ((1 << 5) - 1)) << 21))
675 #define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\
676 | ((N & ((1 << 5) - 1)) << 11)\
677 | ((D & ((1 << 5) - 1)) << 21))
679 #define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\
680 | ((N & ((1 << 5) - 1)) << 11)\
681 | ((D & ((1 << 5) - 1)) << 21))
683 #define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\
684 | ((N & ((1 << 5) - 1)) << 11)\
685 | ((D & ((1 << 5) - 1)) << 21))
687 #define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\
688 | ((N & ((1 << 5) - 1)) << 11)\
689 | ((D & ((1 << 5) - 1)) << 21))
691 #define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\
692 | ((N & ((1 << 5) - 1)) << 11)\
693 | ((D & ((1 << 5) - 1)) << 21))
695 #define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\
696 | ((N & ((1 << 5) - 1)) << 11)\
697 | ((D & ((1 << 5) - 1)) << 21))
699 #define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\
700 | ((N & ((1 << 5) - 1)) << 11)\
701 | ((D & ((1 << 5) - 1)) << 21))
703 #define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\
704 | ((D & ((1 << 5) - 1)) << 21))
706 #define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\
707 | ((D & ((1 << 5) - 1)) << 21))
709 #define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\
710 | ((D & ((1 << 5) - 1)) << 21))
712 #define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\
713 | ((D & ((1 << 5) - 1)) << 21))
715 #define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\
716 | ((N & ((1 << 16) - 1)) << 0)\
717 | ((D & ((1 << 5) - 1)) << 21))
719 #define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\
720 | ((N & ((1 << 5) - 1)) << 16)\
721 | ((D & ((1 << 5) - 1)) << 21))
723 #define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\
724 | ((D & ((1 << 5) - 1)) << 21))
726 #define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
728 #define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\
729 | ((D & ((1 << 5) - 1)) << 21))
731 #define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
733 #define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\
734 | ((D & ((1 << 5) - 1)) << 21))
736 #define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
738 #define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\
739 | ((D & ((1 << 5) - 1)) << 21))
741 #define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
743 #define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\
744 | ((D & ((1 << 5) - 1)) << 21))
746 #define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
748 #define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\
749 | ((D & ((1 << 5) - 1)) << 21))
751 #define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
753 #define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\
754 | ((D & ((1 << 5) - 1)) << 21))
756 #define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
758 #define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\
759 | ((D & ((1 << 5) - 1)) << 21))
761 #define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
764 #endif /* end of __IOP_MPU_MACROS_H__ */
765 /* End of iop_mpu_macros.h */