2 * Port on Texas Instruments TMS320C6x architecture
4 * Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/dma-mapping.h>
12 #include <linux/memblock.h>
13 #include <linux/seq_file.h>
14 #include <linux/clkdev.h>
15 #include <linux/initrd.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/of_fdt.h>
19 #include <linux/string.h>
20 #include <linux/errno.h>
21 #include <linux/cache.h>
22 #include <linux/delay.h>
23 #include <linux/sched.h>
24 #include <linux/clk.h>
25 #include <linux/cpu.h>
28 #include <linux/console.h>
29 #include <linux/screen_info.h>
31 #include <asm/sections.h>
32 #include <asm/div64.h>
33 #include <asm/setup.h>
35 #include <asm/clock.h>
37 #include <asm/special_insns.h>
39 static const char *c6x_soc_name;
41 struct screen_info screen_info;
44 EXPORT_SYMBOL_GPL(c6x_num_cores);
46 unsigned int c6x_silicon_rev;
47 EXPORT_SYMBOL_GPL(c6x_silicon_rev);
50 * Device status register. This holds information
51 * about device configuration needed by some drivers.
53 unsigned int c6x_devstat;
54 EXPORT_SYMBOL_GPL(c6x_devstat);
57 * Some SoCs have fuse registers holding a unique MAC
58 * address. This is parsed out of the device tree with
59 * the resulting MAC being held here.
61 unsigned char c6x_fuse_mac[6];
63 unsigned long memory_start;
64 unsigned long memory_end;
65 EXPORT_SYMBOL(memory_end);
67 unsigned long ram_start;
68 unsigned long ram_end;
70 /* Uncached memory for DMA consistent use (memdma=) */
71 static unsigned long dma_start __initdata;
72 static unsigned long dma_size __initdata;
76 const char *cpu_voltage;
84 static DEFINE_PER_CPU(struct cpuinfo_c6x, cpu_data);
86 unsigned int ticks_per_ns_scaled;
87 EXPORT_SYMBOL(ticks_per_ns_scaled);
89 unsigned int c6x_core_freq;
91 static void __init get_cpuinfo(void)
93 unsigned cpu_id, rev_id, csr;
94 struct clk *coreclk = clk_get_sys(NULL, "core");
95 unsigned long core_khz;
97 struct cpuinfo_c6x *p;
98 struct device_node *node;
100 p = &per_cpu(cpu_data, smp_processor_id());
102 if (!IS_ERR(coreclk))
103 c6x_core_freq = clk_get_rate(coreclk);
106 "Cannot find core clock frequency. Using 700MHz\n");
107 c6x_core_freq = 700000000;
110 core_khz = c6x_core_freq / 1000;
112 tmp = (uint64_t)core_khz << C6X_NDELAY_SCALE;
113 do_div(tmp, 1000000);
114 ticks_per_ns_scaled = tmp;
118 rev_id = (csr >> 16) & 0xff;
122 p->cpu_voltage = "unknown";
126 p->cpu_name = "C67x";
130 p->cpu_name = "C62x";
133 p->cpu_name = "C64x";
136 p->cpu_name = "C64x";
139 p->cpu_name = "C64x+";
140 p->cpu_voltage = "1.2";
143 p->cpu_name = "C66X";
144 p->cpu_voltage = "1.2";
147 p->cpu_name = "unknown";
155 p->cpu_rev = "DM640/DM641/DM642/DM643";
156 p->cpu_voltage = "1.2 - 1.4";
158 p->cpu_rev = "C6201";
159 p->cpu_voltage = "2.5";
163 p->cpu_rev = "C6201B/C6202/C6211";
164 p->cpu_voltage = "1.8";
167 p->cpu_rev = "C6202B/C6203/C6204/C6205";
168 p->cpu_voltage = "1.5";
171 p->cpu_rev = "C6701 revision 0 (early CPU)";
172 p->cpu_voltage = "1.8";
175 p->cpu_rev = "C6701/C6711/C6712";
176 p->cpu_voltage = "1.8";
180 p->cpu_voltage = "1.5";
183 p->cpu_rev = "unknown";
186 p->cpu_rev = p->__cpu_rev;
187 snprintf(p->__cpu_rev, sizeof(p->__cpu_rev), "0x%x", cpu_id);
190 p->core_id = get_coreid();
192 for_each_of_cpu_node(node)
195 node = of_find_node_by_name(NULL, "soc");
197 if (of_property_read_string(node, "model", &c6x_soc_name))
198 c6x_soc_name = "unknown";
201 c6x_soc_name = "unknown";
203 printk(KERN_INFO "CPU%d: %s rev %s, %s volts, %uMHz\n",
204 p->core_id, p->cpu_name, p->cpu_rev,
205 p->cpu_voltage, c6x_core_freq / 1000000);
209 * Early parsing of the command line
211 static u32 mem_size __initdata;
213 /* "mem=" parsing. */
214 static int __init early_mem(char *p)
219 mem_size = memparse(p, &p);
220 /* don't remove all of memory when handling "mem={invalid}" */
226 early_param("mem", early_mem);
228 /* "memdma=<size>[@<address>]" parsing. */
229 static int __init early_memdma(char *p)
234 dma_size = memparse(p, &p);
236 dma_start = memparse(p, &p);
240 early_param("memdma", early_memdma);
242 int __init c6x_add_memory(phys_addr_t start, unsigned long size)
244 static int ram_found __initdata;
246 /* We only handle one bank (the one with PAGE_OFFSET) for now */
250 if (start > PAGE_OFFSET || PAGE_OFFSET >= (start + size))
254 ram_end = start + size;
261 * Do early machine setup and device tree parsing. This is called very
262 * early on the boot process.
264 notrace void __init machine_init(unsigned long dt_ptr)
266 void *dtb = __va(dt_ptr);
267 void *fdt = __dtb_start;
269 /* interrupts must be masked */
273 * Set the Interrupt Service Table (IST) to the beginning of the
276 set_ist(_vectors_start);
279 * dtb is passed in from bootloader.
280 * fdt is linked in blob.
282 if (dtb && dtb != fdt)
285 /* Do some early initialization based on the flat device tree */
286 early_init_dt_scan(fdt);
291 void __init setup_arch(char **cmdline_p)
294 struct memblock_region *reg;
296 printk(KERN_INFO "Initializing kernel\n");
298 /* Initialize command line */
299 *cmdline_p = boot_command_line;
301 memory_end = ram_end;
302 memory_end &= ~(PAGE_SIZE - 1);
304 if (mem_size && (PAGE_OFFSET + PAGE_ALIGN(mem_size)) < memory_end)
305 memory_end = PAGE_OFFSET + PAGE_ALIGN(mem_size);
307 /* add block that this kernel can use */
308 memblock_add(PAGE_OFFSET, memory_end - PAGE_OFFSET);
310 /* reserve kernel text/data/bss */
311 memblock_reserve(PAGE_OFFSET,
312 PAGE_ALIGN((unsigned long)&_end - PAGE_OFFSET));
315 /* align to cacheability granularity */
316 dma_size = CACHE_REGION_END(dma_size);
319 dma_start = memory_end - dma_size;
321 /* align to cacheability granularity */
322 dma_start = CACHE_REGION_START(dma_start);
324 /* reserve DMA memory taken from kernel memory */
325 if (memblock_is_region_memory(dma_start, dma_size))
326 memblock_reserve(dma_start, dma_size);
329 memory_start = PAGE_ALIGN((unsigned int) &_end);
331 printk(KERN_INFO "Memory Start=%08lx, Memory End=%08lx\n",
332 memory_start, memory_end);
334 #ifdef CONFIG_BLK_DEV_INITRD
336 * Reserve initrd memory if in kernel memory.
338 if (initrd_start < initrd_end)
339 if (memblock_is_region_memory(initrd_start,
340 initrd_end - initrd_start))
341 memblock_reserve(initrd_start,
342 initrd_end - initrd_start);
345 init_mm.start_code = (unsigned long) &_stext;
346 init_mm.end_code = (unsigned long) &_etext;
347 init_mm.end_data = memory_start;
348 init_mm.brk = memory_start;
351 * Give all the memory to the bootmap allocator, tell it to put the
352 * boot mem_map at the start of memory
354 bootmap_size = init_bootmem_node(NODE_DATA(0),
355 memory_start >> PAGE_SHIFT,
356 PAGE_OFFSET >> PAGE_SHIFT,
357 memory_end >> PAGE_SHIFT);
358 memblock_reserve(memory_start, bootmap_size);
360 unflatten_and_copy_device_tree();
364 /* Set the whole external memory as non-cacheable */
365 disable_caching(ram_start, ram_end - 1);
367 /* Set caching of external RAM used by Linux */
368 for_each_memblock(memory, reg)
369 enable_caching(CACHE_REGION_START(reg->base),
370 CACHE_REGION_START(reg->base + reg->size - 1));
372 #ifdef CONFIG_BLK_DEV_INITRD
374 * Enable caching for initrd which falls outside kernel memory.
376 if (initrd_start < initrd_end) {
377 if (!memblock_is_region_memory(initrd_start,
378 initrd_end - initrd_start))
379 enable_caching(CACHE_REGION_START(initrd_start),
380 CACHE_REGION_START(initrd_end - 1));
385 * Disable caching for dma coherent memory taken from kernel memory.
387 if (dma_size && memblock_is_region_memory(dma_start, dma_size))
388 disable_caching(dma_start,
389 CACHE_REGION_START(dma_start + dma_size - 1));
391 /* Initialize the coherent memory allocator */
392 coherent_mem_init(dma_start, dma_size);
395 * Free all memory as a starting point.
397 free_bootmem(PAGE_OFFSET, memory_end - PAGE_OFFSET);
400 * Then reserve memory which is already being used.
402 for_each_memblock(reserved, reg) {
403 pr_debug("reserved - 0x%08x-0x%08x\n",
404 (u32) reg->base, (u32) reg->size);
405 reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
408 max_low_pfn = PFN_DOWN(memory_end);
409 min_low_pfn = PFN_UP(memory_start);
410 max_mapnr = max_low_pfn - min_low_pfn;
412 /* Get kmalloc into gear */
416 * Probe for Device State Configuration Registers.
417 * We have to do this early in case timer needs to be enabled
422 /* We do this early for timer and core clock frequency */
428 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
429 conswitchp = &dummy_con;
433 #define cpu_to_ptr(n) ((void *)((long)(n)+1))
434 #define ptr_to_cpu(p) ((long)(p) - 1)
436 static int show_cpuinfo(struct seq_file *m, void *v)
438 int n = ptr_to_cpu(v);
439 struct cpuinfo_c6x *p = &per_cpu(cpu_data, n);
444 "soc revision\t: 0x%x\n"
446 c6x_soc_name, c6x_silicon_rev, c6x_num_cores);
453 "core revision\t: %s\n"
454 "core voltage\t: %s\n"
459 "bogomips\t: %lu.%02lu\n\n",
461 p->cpu_name, p->cpu_rev, p->cpu_voltage,
462 p->core_id, p->mmu, p->fpu,
463 (c6x_core_freq + 500000) / 1000000,
464 (loops_per_jiffy/(500000/HZ)),
465 (loops_per_jiffy/(5000/HZ))%100);
470 static void *c_start(struct seq_file *m, loff_t *pos)
472 return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
474 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
479 static void c_stop(struct seq_file *m, void *v)
483 const struct seq_operations cpuinfo_op = {
490 static struct cpu cpu_devices[NR_CPUS];
492 static int __init topology_init(void)
496 for_each_present_cpu(i)
497 register_cpu(&cpu_devices[i], i);
502 subsys_initcall(topology_init);