2 * File: arch/blackfin/kernel/smp.c
3 * Author: Philippe Gerum <rpm@xenomai.org>
4 * IPI management based on arch/arm/kernel/smp.c.
6 * Copyright 2007 Analog Devices Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see the file COPYING, or write
20 * to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <linux/module.h>
25 #include <linux/delay.h>
26 #include <linux/init.h>
27 #include <linux/spinlock.h>
28 #include <linux/sched.h>
29 #include <linux/interrupt.h>
30 #include <linux/cache.h>
31 #include <linux/profile.h>
32 #include <linux/errno.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
36 #include <linux/seq_file.h>
37 #include <linux/irq.h>
38 #include <asm/atomic.h>
39 #include <asm/cacheflush.h>
40 #include <asm/mmu_context.h>
41 #include <asm/pgtable.h>
42 #include <asm/pgalloc.h>
43 #include <asm/processor.h>
44 #include <asm/ptrace.h>
47 #include <linux/err.h>
51 * 05000120 - we always define corelock as 32-bit integer in L2
53 struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
55 void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
56 *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
57 *init_saved_dcplb_fault_addr_coreb;
59 cpumask_t cpu_possible_map;
60 EXPORT_SYMBOL(cpu_possible_map);
62 cpumask_t cpu_online_map;
63 EXPORT_SYMBOL(cpu_online_map);
65 #define BFIN_IPI_RESCHEDULE 0
66 #define BFIN_IPI_CALL_FUNC 1
67 #define BFIN_IPI_CPU_STOP 2
69 struct blackfin_flush_data {
74 void *secondary_stack;
77 struct smp_call_struct {
78 void (*func)(void *info);
85 static struct blackfin_flush_data smp_flush_data;
87 static DEFINE_SPINLOCK(stop_lock);
90 struct list_head list;
92 struct smp_call_struct call_struct;
95 struct ipi_message_queue {
96 struct list_head head;
101 static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
103 static void ipi_cpu_stop(unsigned int cpu)
105 spin_lock(&stop_lock);
106 printk(KERN_CRIT "CPU%u: stopping\n", cpu);
108 spin_unlock(&stop_lock);
110 cpu_clear(cpu, cpu_online_map);
118 static void ipi_flush_icache(void *info)
120 struct blackfin_flush_data *fdata = info;
122 /* Invalidate the memory holding the bounds of the flushed region. */
123 blackfin_dcache_invalidate_range((unsigned long)fdata,
124 (unsigned long)fdata + sizeof(*fdata));
126 blackfin_icache_flush_range(fdata->start, fdata->end);
129 static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
132 void (*func)(void *info);
134 func = msg->call_struct.func;
135 info = msg->call_struct.info;
136 wait = msg->call_struct.wait;
137 cpu_clear(cpu, msg->call_struct.pending);
140 cpu_clear(cpu, msg->call_struct.waitmask);
145 static irqreturn_t ipi_handler(int irq, void *dev_instance)
147 struct ipi_message *msg, *mg;
148 struct ipi_message_queue *msg_queue;
149 unsigned int cpu = smp_processor_id();
151 platform_clear_ipi(cpu);
153 msg_queue = &__get_cpu_var(ipi_msg_queue);
156 spin_lock(&msg_queue->lock);
157 list_for_each_entry_safe(msg, mg, &msg_queue->head, list) {
158 list_del(&msg->list);
160 case BFIN_IPI_RESCHEDULE:
161 /* That's the easiest one; leave it to
162 * return_from_int. */
165 case BFIN_IPI_CALL_FUNC:
166 spin_unlock(&msg_queue->lock);
167 ipi_call_function(cpu, msg);
168 spin_lock(&msg_queue->lock);
170 case BFIN_IPI_CPU_STOP:
171 spin_unlock(&msg_queue->lock);
173 spin_lock(&msg_queue->lock);
177 printk(KERN_CRIT "CPU%u: Unknown IPI message \
178 0x%lx\n", cpu, msg->type);
183 spin_unlock(&msg_queue->lock);
187 static void ipi_queue_init(void)
190 struct ipi_message_queue *msg_queue;
191 for_each_possible_cpu(cpu) {
192 msg_queue = &per_cpu(ipi_msg_queue, cpu);
193 INIT_LIST_HEAD(&msg_queue->head);
194 spin_lock_init(&msg_queue->lock);
195 msg_queue->count = 0;
199 int smp_call_function(void (*func)(void *info), void *info, int wait)
204 struct ipi_message_queue *msg_queue;
205 struct ipi_message *msg;
207 callmap = cpu_online_map;
208 cpu_clear(smp_processor_id(), callmap);
209 if (cpus_empty(callmap))
212 msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
213 INIT_LIST_HEAD(&msg->list);
214 msg->call_struct.func = func;
215 msg->call_struct.info = info;
216 msg->call_struct.wait = wait;
217 msg->call_struct.pending = callmap;
218 msg->call_struct.waitmask = callmap;
219 msg->type = BFIN_IPI_CALL_FUNC;
221 for_each_cpu_mask(cpu, callmap) {
222 msg_queue = &per_cpu(ipi_msg_queue, cpu);
223 spin_lock_irqsave(&msg_queue->lock, flags);
224 list_add(&msg->list, &msg_queue->head);
225 spin_unlock_irqrestore(&msg_queue->lock, flags);
226 platform_send_ipi_cpu(cpu);
229 while (!cpus_empty(msg->call_struct.waitmask))
230 blackfin_dcache_invalidate_range(
231 (unsigned long)(&msg->call_struct.waitmask),
232 (unsigned long)(&msg->call_struct.waitmask));
237 EXPORT_SYMBOL_GPL(smp_call_function);
239 int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
242 unsigned int cpu = cpuid;
245 struct ipi_message_queue *msg_queue;
246 struct ipi_message *msg;
248 if (cpu_is_offline(cpu))
251 cpu_set(cpu, callmap);
253 msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
254 INIT_LIST_HEAD(&msg->list);
255 msg->call_struct.func = func;
256 msg->call_struct.info = info;
257 msg->call_struct.wait = wait;
258 msg->call_struct.pending = callmap;
259 msg->call_struct.waitmask = callmap;
260 msg->type = BFIN_IPI_CALL_FUNC;
262 msg_queue = &per_cpu(ipi_msg_queue, cpu);
263 spin_lock_irqsave(&msg_queue->lock, flags);
264 list_add(&msg->list, &msg_queue->head);
265 spin_unlock_irqrestore(&msg_queue->lock, flags);
266 platform_send_ipi_cpu(cpu);
269 while (!cpus_empty(msg->call_struct.waitmask))
270 blackfin_dcache_invalidate_range(
271 (unsigned long)(&msg->call_struct.waitmask),
272 (unsigned long)(&msg->call_struct.waitmask));
277 EXPORT_SYMBOL_GPL(smp_call_function_single);
279 void smp_send_reschedule(int cpu)
282 struct ipi_message_queue *msg_queue;
283 struct ipi_message *msg;
285 if (cpu_is_offline(cpu))
288 msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
289 memset(msg, 0, sizeof(msg));
290 INIT_LIST_HEAD(&msg->list);
291 msg->type = BFIN_IPI_RESCHEDULE;
293 msg_queue = &per_cpu(ipi_msg_queue, cpu);
294 spin_lock_irqsave(&msg_queue->lock, flags);
295 list_add(&msg->list, &msg_queue->head);
296 spin_unlock_irqrestore(&msg_queue->lock, flags);
297 platform_send_ipi_cpu(cpu);
302 void smp_send_stop(void)
307 struct ipi_message_queue *msg_queue;
308 struct ipi_message *msg;
310 callmap = cpu_online_map;
311 cpu_clear(smp_processor_id(), callmap);
312 if (cpus_empty(callmap))
315 msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
316 memset(msg, 0, sizeof(msg));
317 INIT_LIST_HEAD(&msg->list);
318 msg->type = BFIN_IPI_CPU_STOP;
320 for_each_cpu_mask(cpu, callmap) {
321 msg_queue = &per_cpu(ipi_msg_queue, cpu);
322 spin_lock_irqsave(&msg_queue->lock, flags);
323 list_add(&msg->list, &msg_queue->head);
324 spin_unlock_irqrestore(&msg_queue->lock, flags);
325 platform_send_ipi_cpu(cpu);
330 int __cpuinit __cpu_up(unsigned int cpu)
332 struct task_struct *idle;
335 idle = fork_idle(cpu);
337 printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
338 return PTR_ERR(idle);
341 secondary_stack = task_stack_page(idle) + THREAD_SIZE;
344 ret = platform_boot_secondary(cpu, idle);
347 cpu_clear(cpu, cpu_present_map);
348 printk(KERN_CRIT "CPU%u: processor failed to boot (%d)\n", cpu, ret);
351 cpu_set(cpu, cpu_online_map);
353 secondary_stack = NULL;
358 static void __cpuinit setup_secondary(unsigned int cpu)
360 #if !defined(CONFIG_TICKSOURCE_GPTMR0)
361 struct irq_desc *timer_desc;
367 ilat = bfin_read_ILAT();
369 bfin_write_ILAT(ilat);
372 /* Enable interrupt levels IVG7-15. IARs have been already
373 * programmed by the boot CPU. */
374 bfin_irq_flags |= IMASK_IVG15 |
375 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
376 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
378 #if defined(CONFIG_TICKSOURCE_GPTMR0)
379 /* Power down the core timer, just to play safe. */
382 /* system timer0 has been setup by CoreA. */
384 timer_desc = irq_desc + IRQ_CORETMR;
386 timer_desc->chip->enable(IRQ_CORETMR);
390 void __cpuinit secondary_start_kernel(void)
392 unsigned int cpu = smp_processor_id();
393 struct mm_struct *mm = &init_mm;
395 if (_bfin_swrst & SWRST_DBL_FAULT_B) {
396 printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
397 #ifdef CONFIG_DEBUG_DOUBLEFAULT
398 printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
399 (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
400 printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
401 printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
403 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
408 * We want the D-cache to be enabled early, in case the atomic
409 * support code emulates cache coherence (see
410 * __ARCH_SYNC_CORE_DCACHE).
412 init_exception_vectors();
414 bfin_setup_caches(cpu);
418 /* Attach the new idle task to the global mm. */
419 atomic_inc(&mm->mm_users);
420 atomic_inc(&mm->mm_count);
421 current->active_mm = mm;
422 BUG_ON(current->mm); /* Can't be, but better be safe than sorry. */
426 setup_secondary(cpu);
430 platform_secondary_init(cpu);
435 void __init smp_prepare_boot_cpu(void)
439 void __init smp_prepare_cpus(unsigned int max_cpus)
441 platform_prepare_cpus(max_cpus);
443 platform_request_ipi(&ipi_handler);
446 void __init smp_cpus_done(unsigned int max_cpus)
448 unsigned long bogosum = 0;
451 for_each_online_cpu(cpu)
452 bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;
454 printk(KERN_INFO "SMP: Total of %d processors activated "
455 "(%lu.%02lu BogoMIPS).\n",
457 bogosum / (500000/HZ),
458 (bogosum / (5000/HZ)) % 100);
461 void smp_icache_flush_range_others(unsigned long start, unsigned long end)
463 smp_flush_data.start = start;
464 smp_flush_data.end = end;
466 if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
467 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
469 EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
471 #ifdef __ARCH_SYNC_CORE_DCACHE
472 unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
474 void resync_core_dcache(void)
476 unsigned int cpu = get_cpu();
477 blackfin_invalidate_entire_dcache();
478 ++per_cpu(cpu_data, cpu).dcache_invld_count;
481 EXPORT_SYMBOL(resync_core_dcache);