2 * Set up the interrupt priorities
4 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
11 * Licensed under the GPL-2
14 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/irq.h>
19 #include <linux/ipipe.h>
22 #include <linux/kgdb.h>
24 #include <asm/traps.h>
25 #include <asm/blackfin.h>
27 #include <asm/irq_handler.h>
29 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
32 # define BF537_GENERIC_ERROR_INT_DEMUX
34 # undef BF537_GENERIC_ERROR_INT_DEMUX
39 * - we have separated the physical Hardware interrupt from the
40 * levels that the LINUX kernel sees (see the description in irq.h)
45 /* Initialize this to an actual value to force it into the .data
46 * section so that we know it is properly initialized at entry into
47 * the kernel but before bss is initialized to zero (which is where
48 * it would live otherwise). The 0x1f magic represents the IRQs we
49 * cannot actually mask out in hardware.
51 unsigned long bfin_irq_flags = 0x1f;
52 EXPORT_SYMBOL(bfin_irq_flags);
55 /* The number of spurious interrupts */
56 atomic_t num_spurious;
59 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
64 /* irq number for request_irq, available in mach-bf5xx/irq.h */
66 /* corresponding bit in the SIC_ISR register */
68 } ivg_table[NR_PERI_INTS];
71 /* position of first irq in ivg_table for given ivg */
74 } ivg7_13[IVG13 - IVG7 + 1];
78 * Search SIC_IAR and fill tables with the irqvalues
79 * and their positions in the SIC_ISR register.
81 static void __init search_IAR(void)
83 unsigned ivg, irq_pos = 0;
84 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
87 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
89 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
90 int iar_shift = (irqn & 7) * 4;
92 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
93 || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
94 bfin_read32((unsigned long *)SIC_IAR0 +
95 ((irqn % 32) >> 3) + ((irqn / 32) *
96 ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
98 bfin_read32((unsigned long *)SIC_IAR0 +
99 (irqn >> 3)) >> iar_shift)) {
101 ivg_table[irq_pos].irqno = IVG7 + irqn;
102 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
103 ivg7_13[ivg].istop++;
111 * This is for core internal IRQs
114 static void bfin_ack_noop(unsigned int irq)
116 /* Dummy function. */
119 static void bfin_core_mask_irq(unsigned int irq)
121 bfin_irq_flags &= ~(1 << irq);
122 if (!irqs_disabled_hw())
123 local_irq_enable_hw();
126 static void bfin_core_unmask_irq(unsigned int irq)
128 bfin_irq_flags |= 1 << irq;
130 * If interrupts are enabled, IMASK must contain the same value
131 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
132 * are currently disabled we need not do anything; one of the
133 * callers will take care of setting IMASK to the proper value
134 * when reenabling interrupts.
135 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
138 if (!irqs_disabled_hw())
139 local_irq_enable_hw();
143 static void bfin_internal_mask_irq(unsigned int irq)
148 local_irq_save_hw(flags);
149 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
150 ~(1 << SIC_SYSIRQ(irq)));
152 unsigned mask_bank, mask_bit;
153 local_irq_save_hw(flags);
154 mask_bank = SIC_SYSIRQ(irq) / 32;
155 mask_bit = SIC_SYSIRQ(irq) % 32;
156 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
159 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
163 local_irq_restore_hw(flags);
166 static void bfin_internal_unmask_irq(unsigned int irq)
171 local_irq_save_hw(flags);
172 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
173 (1 << SIC_SYSIRQ(irq)));
175 unsigned mask_bank, mask_bit;
176 local_irq_save_hw(flags);
177 mask_bank = SIC_SYSIRQ(irq) / 32;
178 mask_bit = SIC_SYSIRQ(irq) % 32;
179 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
182 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) |
186 local_irq_restore_hw(flags);
190 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
192 u32 bank, bit, wakeup = 0;
194 bank = SIC_SYSIRQ(irq) / 32;
195 bit = SIC_SYSIRQ(irq) % 32;
232 local_irq_save_hw(flags);
235 bfin_sic_iwr[bank] |= (1 << bit);
239 bfin_sic_iwr[bank] &= ~(1 << bit);
240 vr_wakeup &= ~wakeup;
243 local_irq_restore_hw(flags);
249 static struct irq_chip bfin_core_irqchip = {
251 .ack = bfin_ack_noop,
252 .mask = bfin_core_mask_irq,
253 .unmask = bfin_core_unmask_irq,
256 static struct irq_chip bfin_internal_irqchip = {
258 .ack = bfin_ack_noop,
259 .mask = bfin_internal_mask_irq,
260 .unmask = bfin_internal_unmask_irq,
261 .mask_ack = bfin_internal_mask_irq,
262 .disable = bfin_internal_mask_irq,
263 .enable = bfin_internal_unmask_irq,
265 .set_wake = bfin_internal_set_wake,
269 static void bfin_handle_irq(unsigned irq)
272 struct pt_regs regs; /* Contents not used. */
273 ipipe_trace_irq_entry(irq);
274 __ipipe_handle_irq(irq, ®s);
275 ipipe_trace_irq_exit(irq);
276 #else /* !CONFIG_IPIPE */
277 struct irq_desc *desc = irq_desc + irq;
278 desc->handle_irq(irq, desc);
279 #endif /* !CONFIG_IPIPE */
282 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
283 static int error_int_mask;
285 static void bfin_generic_error_mask_irq(unsigned int irq)
287 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
290 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
293 static void bfin_generic_error_unmask_irq(unsigned int irq)
295 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
296 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
299 static struct irq_chip bfin_generic_error_irqchip = {
301 .ack = bfin_ack_noop,
302 .mask_ack = bfin_generic_error_mask_irq,
303 .mask = bfin_generic_error_mask_irq,
304 .unmask = bfin_generic_error_unmask_irq,
307 static void bfin_demux_error_irq(unsigned int int_err_irq,
308 struct irq_desc *inta_desc)
312 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
313 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
317 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
318 irq = IRQ_SPORT0_ERROR;
319 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
320 irq = IRQ_SPORT1_ERROR;
321 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
323 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
325 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
327 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
328 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
329 irq = IRQ_UART0_ERROR;
330 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
331 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
332 irq = IRQ_UART1_ERROR;
335 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
336 bfin_handle_irq(irq);
341 bfin_write_PPI_STATUS(PPI_ERR_MASK);
343 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
345 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
348 case IRQ_SPORT0_ERROR:
349 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
352 case IRQ_SPORT1_ERROR:
353 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
357 bfin_write_CAN_GIS(CAN_ERR_MASK);
361 bfin_write_SPI_STAT(SPI_ERR_MASK);
369 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
374 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
375 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
376 __func__, __FILE__, __LINE__);
379 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
381 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
384 _set_irq_handler(irq, handle_level_irq);
386 struct irq_desc *desc = irq_desc + irq;
387 /* May not call generic set_irq_handler() due to spinlock
389 desc->handle_irq = handle;
393 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
394 extern void bfin_gpio_irq_prepare(unsigned gpio);
396 #if !defined(CONFIG_BF54x)
398 static void bfin_gpio_ack_irq(unsigned int irq)
400 /* AFAIK ack_irq in case mask_ack is provided
401 * get's only called for edge sense irqs
403 set_gpio_data(irq_to_gpio(irq), 0);
406 static void bfin_gpio_mask_ack_irq(unsigned int irq)
408 struct irq_desc *desc = irq_desc + irq;
409 u32 gpionr = irq_to_gpio(irq);
411 if (desc->handle_irq == handle_edge_irq)
412 set_gpio_data(gpionr, 0);
414 set_gpio_maska(gpionr, 0);
417 static void bfin_gpio_mask_irq(unsigned int irq)
419 set_gpio_maska(irq_to_gpio(irq), 0);
422 static void bfin_gpio_unmask_irq(unsigned int irq)
424 set_gpio_maska(irq_to_gpio(irq), 1);
427 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
429 u32 gpionr = irq_to_gpio(irq);
431 if (__test_and_set_bit(gpionr, gpio_enabled))
432 bfin_gpio_irq_prepare(gpionr);
434 bfin_gpio_unmask_irq(irq);
439 static void bfin_gpio_irq_shutdown(unsigned int irq)
441 u32 gpionr = irq_to_gpio(irq);
443 bfin_gpio_mask_irq(irq);
444 __clear_bit(gpionr, gpio_enabled);
445 bfin_gpio_irq_free(gpionr);
448 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
452 u32 gpionr = irq_to_gpio(irq);
454 if (type == IRQ_TYPE_PROBE) {
455 /* only probe unenabled GPIO interrupt lines */
456 if (test_bit(gpionr, gpio_enabled))
458 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
461 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
462 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
464 snprintf(buf, 16, "gpio-irq%d", irq);
465 ret = bfin_gpio_irq_request(gpionr, buf);
469 if (__test_and_set_bit(gpionr, gpio_enabled))
470 bfin_gpio_irq_prepare(gpionr);
473 __clear_bit(gpionr, gpio_enabled);
477 set_gpio_inen(gpionr, 0);
478 set_gpio_dir(gpionr, 0);
480 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
481 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
482 set_gpio_both(gpionr, 1);
484 set_gpio_both(gpionr, 0);
486 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
487 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
489 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
491 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
492 set_gpio_edge(gpionr, 1);
493 set_gpio_inen(gpionr, 1);
494 set_gpio_data(gpionr, 0);
497 set_gpio_edge(gpionr, 0);
498 set_gpio_inen(gpionr, 1);
501 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
502 bfin_set_irq_handler(irq, handle_edge_irq);
504 bfin_set_irq_handler(irq, handle_level_irq);
510 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
512 unsigned gpio = irq_to_gpio(irq);
515 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
517 gpio_pm_wakeup_free(gpio);
523 static void bfin_demux_gpio_irq(unsigned int inta_irq,
524 struct irq_desc *desc)
526 unsigned int i, gpio, mask, irq, search = 0;
529 #if defined(CONFIG_BF53x)
534 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
539 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
543 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
553 #elif defined(CONFIG_BF561)
570 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
573 mask = get_gpiop_data(i) & get_gpiop_maska(i);
577 bfin_handle_irq(irq);
583 gpio = irq_to_gpio(irq);
584 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
588 bfin_handle_irq(irq);
596 #else /* CONFIG_BF54x */
598 #define NR_PINT_SYS_IRQS 4
599 #define NR_PINT_BITS 32
601 #define IRQ_NOT_AVAIL 0xFF
603 #define PINT_2_BANK(x) ((x) >> 5)
604 #define PINT_2_BIT(x) ((x) & 0x1F)
605 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
607 static unsigned char irq2pint_lut[NR_PINTS];
608 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
611 unsigned int mask_set;
612 unsigned int mask_clear;
613 unsigned int request;
615 unsigned int edge_set;
616 unsigned int edge_clear;
617 unsigned int invert_set;
618 unsigned int invert_clear;
619 unsigned int pinstate;
623 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
624 (struct pin_int_t *)PINT0_MASK_SET,
625 (struct pin_int_t *)PINT1_MASK_SET,
626 (struct pin_int_t *)PINT2_MASK_SET,
627 (struct pin_int_t *)PINT3_MASK_SET,
630 inline unsigned int get_irq_base(u32 bank, u8 bmap)
632 unsigned int irq_base;
634 if (bank < 2) { /*PA-PB */
635 irq_base = IRQ_PA0 + bmap * 16;
637 irq_base = IRQ_PC0 + bmap * 16;
643 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
644 void init_pint_lut(void)
646 u16 bank, bit, irq_base, bit_pos;
650 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
652 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
654 pint_assign = pint[bank]->assign;
656 for (bit = 0; bit < NR_PINT_BITS; bit++) {
658 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
660 irq_base = get_irq_base(bank, bmap);
662 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
663 bit_pos = bit + bank * NR_PINT_BITS;
665 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
666 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
671 static void bfin_gpio_ack_irq(unsigned int irq)
673 struct irq_desc *desc = irq_desc + irq;
674 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
675 u32 pintbit = PINT_BIT(pint_val);
676 u32 bank = PINT_2_BANK(pint_val);
678 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
679 if (pint[bank]->invert_set & pintbit)
680 pint[bank]->invert_clear = pintbit;
682 pint[bank]->invert_set = pintbit;
684 pint[bank]->request = pintbit;
688 static void bfin_gpio_mask_ack_irq(unsigned int irq)
690 struct irq_desc *desc = irq_desc + irq;
691 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
692 u32 pintbit = PINT_BIT(pint_val);
693 u32 bank = PINT_2_BANK(pint_val);
695 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
696 if (pint[bank]->invert_set & pintbit)
697 pint[bank]->invert_clear = pintbit;
699 pint[bank]->invert_set = pintbit;
702 pint[bank]->request = pintbit;
703 pint[bank]->mask_clear = pintbit;
706 static void bfin_gpio_mask_irq(unsigned int irq)
708 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
710 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
713 static void bfin_gpio_unmask_irq(unsigned int irq)
715 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
716 u32 pintbit = PINT_BIT(pint_val);
717 u32 bank = PINT_2_BANK(pint_val);
719 pint[bank]->request = pintbit;
720 pint[bank]->mask_set = pintbit;
723 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
725 u32 gpionr = irq_to_gpio(irq);
726 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
728 if (pint_val == IRQ_NOT_AVAIL) {
730 "GPIO IRQ %d :Not in PINT Assign table "
731 "Reconfigure Interrupt to Port Assignemt\n", irq);
735 if (__test_and_set_bit(gpionr, gpio_enabled))
736 bfin_gpio_irq_prepare(gpionr);
738 bfin_gpio_unmask_irq(irq);
743 static void bfin_gpio_irq_shutdown(unsigned int irq)
745 u32 gpionr = irq_to_gpio(irq);
747 bfin_gpio_mask_irq(irq);
748 __clear_bit(gpionr, gpio_enabled);
749 bfin_gpio_irq_free(gpionr);
752 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
756 u32 gpionr = irq_to_gpio(irq);
757 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
758 u32 pintbit = PINT_BIT(pint_val);
759 u32 bank = PINT_2_BANK(pint_val);
761 if (pint_val == IRQ_NOT_AVAIL)
764 if (type == IRQ_TYPE_PROBE) {
765 /* only probe unenabled GPIO interrupt lines */
766 if (test_bit(gpionr, gpio_enabled))
768 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
771 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
772 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
774 snprintf(buf, 16, "gpio-irq%d", irq);
775 ret = bfin_gpio_irq_request(gpionr, buf);
779 if (__test_and_set_bit(gpionr, gpio_enabled))
780 bfin_gpio_irq_prepare(gpionr);
783 __clear_bit(gpionr, gpio_enabled);
787 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
788 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
790 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
792 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
793 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
794 if (gpio_get_value(gpionr))
795 pint[bank]->invert_set = pintbit;
797 pint[bank]->invert_clear = pintbit;
800 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
801 pint[bank]->edge_set = pintbit;
802 bfin_set_irq_handler(irq, handle_edge_irq);
804 pint[bank]->edge_clear = pintbit;
805 bfin_set_irq_handler(irq, handle_level_irq);
812 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
813 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
815 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
818 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
819 u32 bank = PINT_2_BANK(pint_val);
820 u32 pintbit = PINT_BIT(pint_val);
824 pint_irq = IRQ_PINT0;
827 pint_irq = IRQ_PINT2;
830 pint_irq = IRQ_PINT3;
833 pint_irq = IRQ_PINT1;
839 bfin_internal_set_wake(pint_irq, state);
842 pint_wakeup_masks[bank] |= pintbit;
844 pint_wakeup_masks[bank] &= ~pintbit;
849 u32 bfin_pm_setup(void)
853 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
854 val = pint[i]->mask_clear;
855 pint_saved_masks[i] = val;
856 if (val ^ pint_wakeup_masks[i]) {
857 pint[i]->mask_clear = val;
858 pint[i]->mask_set = pint_wakeup_masks[i];
865 void bfin_pm_restore(void)
869 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
870 val = pint_saved_masks[i];
871 if (val ^ pint_wakeup_masks[i]) {
872 pint[i]->mask_clear = pint[i]->mask_clear;
873 pint[i]->mask_set = val;
879 static void bfin_demux_gpio_irq(unsigned int inta_irq,
880 struct irq_desc *desc)
902 pint_val = bank * NR_PINT_BITS;
904 request = pint[bank]->request;
908 irq = pint2irq_lut[pint_val] + SYS_IRQS;
909 bfin_handle_irq(irq);
918 static struct irq_chip bfin_gpio_irqchip = {
920 .ack = bfin_gpio_ack_irq,
921 .mask = bfin_gpio_mask_irq,
922 .mask_ack = bfin_gpio_mask_ack_irq,
923 .unmask = bfin_gpio_unmask_irq,
924 .disable = bfin_gpio_mask_irq,
925 .enable = bfin_gpio_unmask_irq,
926 .set_type = bfin_gpio_irq_type,
927 .startup = bfin_gpio_irq_startup,
928 .shutdown = bfin_gpio_irq_shutdown,
930 .set_wake = bfin_gpio_set_wake,
934 void __cpuinit init_exception_vectors(void)
936 /* cannot program in software:
937 * evt0 - emulation (jtag)
940 bfin_write_EVT2(evt_nmi);
941 bfin_write_EVT3(trap);
942 bfin_write_EVT5(evt_ivhw);
943 bfin_write_EVT6(evt_timer);
944 bfin_write_EVT7(evt_evt7);
945 bfin_write_EVT8(evt_evt8);
946 bfin_write_EVT9(evt_evt9);
947 bfin_write_EVT10(evt_evt10);
948 bfin_write_EVT11(evt_evt11);
949 bfin_write_EVT12(evt_evt12);
950 bfin_write_EVT13(evt_evt13);
951 bfin_write_EVT14(evt_evt14);
952 bfin_write_EVT15(evt_system_call);
957 * This function should be called during kernel startup to initialize
958 * the BFin IRQ handling routines.
961 int __init init_arch_irq(void)
964 unsigned long ilat = 0;
965 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
966 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
967 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
968 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
969 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
971 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
974 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
975 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
978 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
983 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
984 /* Clear EMAC Interrupt Status bits so we can demux it later */
985 bfin_write_EMAC_SYSTAT(-1);
989 # ifdef CONFIG_PINTx_REASSIGN
990 pint[0]->assign = CONFIG_PINT0_ASSIGN;
991 pint[1]->assign = CONFIG_PINT1_ASSIGN;
992 pint[2]->assign = CONFIG_PINT2_ASSIGN;
993 pint[3]->assign = CONFIG_PINT3_ASSIGN;
995 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
999 for (irq = 0; irq <= SYS_IRQS; irq++) {
1000 if (irq <= IRQ_CORETMR)
1001 set_irq_chip(irq, &bfin_core_irqchip);
1003 set_irq_chip(irq, &bfin_internal_irqchip);
1006 #if defined(CONFIG_BF53x)
1008 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1011 #elif defined(CONFIG_BF54x)
1016 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1017 case IRQ_PORTF_INTA:
1018 case IRQ_PORTG_INTA:
1019 case IRQ_PORTH_INTA:
1020 #elif defined(CONFIG_BF561)
1021 case IRQ_PROG0_INTA:
1022 case IRQ_PROG1_INTA:
1023 case IRQ_PROG2_INTA:
1024 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1025 case IRQ_PORTF_INTA:
1028 set_irq_chained_handler(irq,
1029 bfin_demux_gpio_irq);
1031 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1032 case IRQ_GENERIC_ERROR:
1033 set_irq_chained_handler(irq, bfin_demux_error_irq);
1038 #ifdef CONFIG_TICKSOURCE_GPTMR0
1041 #ifdef CONFIG_TICKSOURCE_CORETMR
1046 set_irq_handler(irq, handle_percpu_irq);
1051 #ifndef CONFIG_TICKSOURCE_CORETMR
1053 set_irq_handler(irq, handle_simple_irq);
1057 set_irq_handler(irq, handle_simple_irq);
1060 set_irq_handler(irq, handle_level_irq);
1062 #else /* !CONFIG_IPIPE */
1064 set_irq_handler(irq, handle_simple_irq);
1066 #endif /* !CONFIG_IPIPE */
1070 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1071 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1072 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1076 /* if configured as edge, then will be changed to do_edge_IRQ */
1077 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1078 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1082 bfin_write_IMASK(0);
1084 ilat = bfin_read_ILAT();
1086 bfin_write_ILAT(ilat);
1089 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1090 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1091 * local_irq_enable()
1094 /* Therefore it's better to setup IARs before interrupts enabled */
1097 /* Enable interrupts IVG7-15 */
1098 bfin_irq_flags |= IMASK_IVG15 |
1099 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1100 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1102 /* This implicitly covers ANOMALY_05000171
1103 * Boot-ROM code modifies SICA_IWRx wakeup registers
1106 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1108 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1109 * will screw up the bootrom as it relies on MDMA0/1 waking it
1110 * up from IDLE instructions. See this report for more info:
1111 * http://blackfin.uclinux.org/gf/tracker/4323
1113 if (ANOMALY_05000435)
1114 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1116 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1119 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1122 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1128 #ifdef CONFIG_DO_IRQ_L1
1129 __attribute__((l1_text))
1131 void do_irq(int vec, struct pt_regs *fp)
1133 if (vec == EVT_IVTMR_P) {
1136 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1137 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1138 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1139 unsigned long sic_status[3];
1141 if (smp_processor_id()) {
1143 /* This will be optimized out in UP mode. */
1144 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1145 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1148 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1149 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1152 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1155 if (ivg >= ivg_stop) {
1156 atomic_inc(&num_spurious);
1159 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1163 unsigned long sic_status;
1165 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1168 if (ivg >= ivg_stop) {
1169 atomic_inc(&num_spurious);
1171 } else if (sic_status & ivg->isrflag)
1177 asm_do_IRQ(vec, fp);
1182 int __ipipe_get_irq_priority(unsigned irq)
1186 if (irq <= IRQ_CORETMR)
1189 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1190 struct ivgx *ivg = ivg_table + ient;
1191 if (ivg->irqno == irq) {
1192 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1193 if (ivg7_13[prio].ifirst <= ivg &&
1194 ivg7_13[prio].istop > ivg)
1203 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1204 #ifdef CONFIG_DO_IRQ_L1
1205 __attribute__((l1_text))
1207 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1209 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1210 struct ipipe_domain *this_domain = __ipipe_current_domain;
1211 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1212 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1215 if (likely(vec == EVT_IVTMR_P))
1218 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1219 unsigned long sic_status[3];
1221 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1222 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1224 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1227 if (ivg >= ivg_stop) {
1228 atomic_inc(&num_spurious);
1231 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1235 unsigned long sic_status;
1237 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1240 if (ivg >= ivg_stop) {
1241 atomic_inc(&num_spurious);
1243 } else if (sic_status & ivg->isrflag)
1250 if (irq == IRQ_SYSTMR) {
1251 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1252 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1254 /* This is basically what we need from the register frame. */
1255 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1256 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1257 if (this_domain != ipipe_root_domain)
1258 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1260 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1263 if (this_domain == ipipe_root_domain) {
1264 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1268 ipipe_trace_irq_entry(irq);
1269 __ipipe_handle_irq(irq, regs);
1270 ipipe_trace_irq_exit(irq);
1272 if (this_domain == ipipe_root_domain) {
1273 set_thread_flag(TIF_IRQ_SYNC);
1275 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1276 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1283 #endif /* CONFIG_IPIPE */