2 * arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
4 * Copyright 2005-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #include <linux/string.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/smp.h>
13 #include <linux/spinlock.h>
14 #include <linux/delay.h>
15 #include <linux/ptrace.h> /* for linux pt_regs struct */
16 #include <linux/kgdb.h>
17 #include <linux/console.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/irq.h>
21 #include <linux/uaccess.h>
22 #include <asm/system.h>
23 #include <asm/traps.h>
24 #include <asm/blackfin.h>
27 void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
29 gdb_regs[BFIN_R0] = regs->r0;
30 gdb_regs[BFIN_R1] = regs->r1;
31 gdb_regs[BFIN_R2] = regs->r2;
32 gdb_regs[BFIN_R3] = regs->r3;
33 gdb_regs[BFIN_R4] = regs->r4;
34 gdb_regs[BFIN_R5] = regs->r5;
35 gdb_regs[BFIN_R6] = regs->r6;
36 gdb_regs[BFIN_R7] = regs->r7;
37 gdb_regs[BFIN_P0] = regs->p0;
38 gdb_regs[BFIN_P1] = regs->p1;
39 gdb_regs[BFIN_P2] = regs->p2;
40 gdb_regs[BFIN_P3] = regs->p3;
41 gdb_regs[BFIN_P4] = regs->p4;
42 gdb_regs[BFIN_P5] = regs->p5;
43 gdb_regs[BFIN_SP] = regs->reserved;
44 gdb_regs[BFIN_FP] = regs->fp;
45 gdb_regs[BFIN_I0] = regs->i0;
46 gdb_regs[BFIN_I1] = regs->i1;
47 gdb_regs[BFIN_I2] = regs->i2;
48 gdb_regs[BFIN_I3] = regs->i3;
49 gdb_regs[BFIN_M0] = regs->m0;
50 gdb_regs[BFIN_M1] = regs->m1;
51 gdb_regs[BFIN_M2] = regs->m2;
52 gdb_regs[BFIN_M3] = regs->m3;
53 gdb_regs[BFIN_B0] = regs->b0;
54 gdb_regs[BFIN_B1] = regs->b1;
55 gdb_regs[BFIN_B2] = regs->b2;
56 gdb_regs[BFIN_B3] = regs->b3;
57 gdb_regs[BFIN_L0] = regs->l0;
58 gdb_regs[BFIN_L1] = regs->l1;
59 gdb_regs[BFIN_L2] = regs->l2;
60 gdb_regs[BFIN_L3] = regs->l3;
61 gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
62 gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
63 gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
64 gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
65 gdb_regs[BFIN_ASTAT] = regs->astat;
66 gdb_regs[BFIN_RETS] = regs->rets;
67 gdb_regs[BFIN_LC0] = regs->lc0;
68 gdb_regs[BFIN_LT0] = regs->lt0;
69 gdb_regs[BFIN_LB0] = regs->lb0;
70 gdb_regs[BFIN_LC1] = regs->lc1;
71 gdb_regs[BFIN_LT1] = regs->lt1;
72 gdb_regs[BFIN_LB1] = regs->lb1;
73 gdb_regs[BFIN_CYCLES] = 0;
74 gdb_regs[BFIN_CYCLES2] = 0;
75 gdb_regs[BFIN_USP] = regs->usp;
76 gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
77 gdb_regs[BFIN_SYSCFG] = regs->syscfg;
78 gdb_regs[BFIN_RETI] = regs->pc;
79 gdb_regs[BFIN_RETX] = regs->retx;
80 gdb_regs[BFIN_RETN] = regs->retn;
81 gdb_regs[BFIN_RETE] = regs->rete;
82 gdb_regs[BFIN_PC] = regs->pc;
83 gdb_regs[BFIN_CC] = 0;
84 gdb_regs[BFIN_EXTRA1] = 0;
85 gdb_regs[BFIN_EXTRA2] = 0;
86 gdb_regs[BFIN_EXTRA3] = 0;
87 gdb_regs[BFIN_IPEND] = regs->ipend;
91 * Extracts ebp, esp and eip values understandable by gdb from the values
93 * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
94 * prior to entering switch_to is 8 greater than the value that is saved.
95 * If switch_to changes, change following code appropriately.
97 void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
99 gdb_regs[BFIN_SP] = p->thread.ksp;
100 gdb_regs[BFIN_PC] = p->thread.pc;
101 gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
104 void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
106 regs->r0 = gdb_regs[BFIN_R0];
107 regs->r1 = gdb_regs[BFIN_R1];
108 regs->r2 = gdb_regs[BFIN_R2];
109 regs->r3 = gdb_regs[BFIN_R3];
110 regs->r4 = gdb_regs[BFIN_R4];
111 regs->r5 = gdb_regs[BFIN_R5];
112 regs->r6 = gdb_regs[BFIN_R6];
113 regs->r7 = gdb_regs[BFIN_R7];
114 regs->p0 = gdb_regs[BFIN_P0];
115 regs->p1 = gdb_regs[BFIN_P1];
116 regs->p2 = gdb_regs[BFIN_P2];
117 regs->p3 = gdb_regs[BFIN_P3];
118 regs->p4 = gdb_regs[BFIN_P4];
119 regs->p5 = gdb_regs[BFIN_P5];
120 regs->fp = gdb_regs[BFIN_FP];
121 regs->i0 = gdb_regs[BFIN_I0];
122 regs->i1 = gdb_regs[BFIN_I1];
123 regs->i2 = gdb_regs[BFIN_I2];
124 regs->i3 = gdb_regs[BFIN_I3];
125 regs->m0 = gdb_regs[BFIN_M0];
126 regs->m1 = gdb_regs[BFIN_M1];
127 regs->m2 = gdb_regs[BFIN_M2];
128 regs->m3 = gdb_regs[BFIN_M3];
129 regs->b0 = gdb_regs[BFIN_B0];
130 regs->b1 = gdb_regs[BFIN_B1];
131 regs->b2 = gdb_regs[BFIN_B2];
132 regs->b3 = gdb_regs[BFIN_B3];
133 regs->l0 = gdb_regs[BFIN_L0];
134 regs->l1 = gdb_regs[BFIN_L1];
135 regs->l2 = gdb_regs[BFIN_L2];
136 regs->l3 = gdb_regs[BFIN_L3];
137 regs->a0x = gdb_regs[BFIN_A0_DOT_X];
138 regs->a0w = gdb_regs[BFIN_A0_DOT_W];
139 regs->a1x = gdb_regs[BFIN_A1_DOT_X];
140 regs->a1w = gdb_regs[BFIN_A1_DOT_W];
141 regs->rets = gdb_regs[BFIN_RETS];
142 regs->lc0 = gdb_regs[BFIN_LC0];
143 regs->lt0 = gdb_regs[BFIN_LT0];
144 regs->lb0 = gdb_regs[BFIN_LB0];
145 regs->lc1 = gdb_regs[BFIN_LC1];
146 regs->lt1 = gdb_regs[BFIN_LT1];
147 regs->lb1 = gdb_regs[BFIN_LB1];
148 regs->usp = gdb_regs[BFIN_USP];
149 regs->syscfg = gdb_regs[BFIN_SYSCFG];
150 regs->retx = gdb_regs[BFIN_PC];
151 regs->retn = gdb_regs[BFIN_RETN];
152 regs->rete = gdb_regs[BFIN_RETE];
153 regs->pc = gdb_regs[BFIN_PC];
155 #if 0 /* can't change these */
156 regs->astat = gdb_regs[BFIN_ASTAT];
157 regs->seqstat = gdb_regs[BFIN_SEQSTAT];
158 regs->ipend = gdb_regs[BFIN_IPEND];
162 struct hw_breakpoint {
163 unsigned int occupied:1;
165 unsigned int enabled:1;
167 unsigned int dataacc:2;
168 unsigned short count;
170 } breakinfo[HW_WATCHPOINT_NUM];
172 int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
179 case BP_HARDWARE_BREAKPOINT:
180 bfin_type = TYPE_INST_WATCHPOINT;
182 case BP_WRITE_WATCHPOINT:
184 bfin_type = TYPE_DATA_WATCHPOINT;
186 case BP_READ_WATCHPOINT:
188 bfin_type = TYPE_DATA_WATCHPOINT;
190 case BP_ACCESS_WATCHPOINT:
192 bfin_type = TYPE_DATA_WATCHPOINT;
198 /* Becasue hardware data watchpoint impelemented in current
199 * Blackfin can not trigger an exception event as the hardware
200 * instrction watchpoint does, we ignaore all data watch point here.
201 * They can be turned on easily after future blackfin design
202 * supports this feature.
204 for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
205 if (bfin_type == breakinfo[breakno].type
206 && !breakinfo[breakno].occupied) {
207 breakinfo[breakno].occupied = 1;
208 breakinfo[breakno].skip = 0;
209 breakinfo[breakno].enabled = 1;
210 breakinfo[breakno].addr = addr;
211 breakinfo[breakno].dataacc = dataacc;
212 breakinfo[breakno].count = 0;
219 int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
225 case BP_HARDWARE_BREAKPOINT:
226 bfin_type = TYPE_INST_WATCHPOINT;
228 case BP_WRITE_WATCHPOINT:
229 case BP_READ_WATCHPOINT:
230 case BP_ACCESS_WATCHPOINT:
231 bfin_type = TYPE_DATA_WATCHPOINT;
236 for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
237 if (bfin_type == breakinfo[breakno].type
238 && breakinfo[breakno].occupied
239 && breakinfo[breakno].addr == addr) {
240 breakinfo[breakno].occupied = 0;
241 breakinfo[breakno].enabled = 0;
247 void bfin_remove_all_hw_break(void)
251 memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM);
253 for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
254 breakinfo[breakno].type = TYPE_INST_WATCHPOINT;
255 for (; breakno < HW_WATCHPOINT_NUM; breakno++)
256 breakinfo[breakno].type = TYPE_DATA_WATCHPOINT;
259 void bfin_correct_hw_break(void)
262 unsigned int wpiactl = 0;
263 unsigned int wpdactl = 0;
266 for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
267 if (breakinfo[breakno].enabled) {
272 wpiactl |= WPIAEN0|WPICNTEN0;
273 bfin_write_WPIA0(breakinfo[breakno].addr);
274 bfin_write_WPIACNT0(breakinfo[breakno].count
278 wpiactl |= WPIAEN1|WPICNTEN1;
279 bfin_write_WPIA1(breakinfo[breakno].addr);
280 bfin_write_WPIACNT1(breakinfo[breakno].count
284 wpiactl |= WPIAEN2|WPICNTEN2;
285 bfin_write_WPIA2(breakinfo[breakno].addr);
286 bfin_write_WPIACNT2(breakinfo[breakno].count
290 wpiactl |= WPIAEN3|WPICNTEN3;
291 bfin_write_WPIA3(breakinfo[breakno].addr);
292 bfin_write_WPIACNT3(breakinfo[breakno].count
296 wpiactl |= WPIAEN4|WPICNTEN4;
297 bfin_write_WPIA4(breakinfo[breakno].addr);
298 bfin_write_WPIACNT4(breakinfo[breakno].count
302 wpiactl |= WPIAEN5|WPICNTEN5;
303 bfin_write_WPIA5(breakinfo[breakno].addr);
304 bfin_write_WPIACNT5(breakinfo[breakno].count
308 wpdactl |= WPDAEN0|WPDCNTEN0|WPDSRC0;
309 wpdactl |= breakinfo[breakno].dataacc
311 bfin_write_WPDA0(breakinfo[breakno].addr);
312 bfin_write_WPDACNT0(breakinfo[breakno].count
316 wpdactl |= WPDAEN1|WPDCNTEN1|WPDSRC1;
317 wpdactl |= breakinfo[breakno].dataacc
319 bfin_write_WPDA1(breakinfo[breakno].addr);
320 bfin_write_WPDACNT1(breakinfo[breakno].count
326 /* Should enable WPPWR bit first before set any other
327 * WPIACTL and WPDACTL bits */
329 bfin_write_WPIACTL(WPPWR);
331 bfin_write_WPIACTL(wpiactl|WPPWR);
332 bfin_write_WPDACTL(wpdactl);
337 void kgdb_disable_hw_debug(struct pt_regs *regs)
339 /* Disable hardware debugging while we are in kgdb */
340 bfin_write_WPIACTL(0);
341 bfin_write_WPDACTL(0);
346 void kgdb_passive_cpu_callback(void *info)
348 kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
351 void kgdb_roundup_cpus(unsigned long flags)
353 smp_call_function(kgdb_passive_cpu_callback, NULL, 0);
356 void kgdb_roundup_cpu(int cpu, unsigned long flags)
358 smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0);
362 int kgdb_arch_handle_exception(int vector, int signo,
363 int err_code, char *remcom_in_buffer,
364 char *remcom_out_buffer,
365 struct pt_regs *regs)
372 switch (remcom_in_buffer[0]) {
375 if (kgdb_contthread && kgdb_contthread != current) {
376 strcpy(remcom_out_buffer, "E00");
380 kgdb_contthread = NULL;
382 /* try to read optional parameter, pc unchanged if no parm */
383 ptr = &remcom_in_buffer[1];
384 if (kgdb_hex2long(&ptr, &addr)) {
389 /* clear the trace bit */
390 regs->syscfg &= 0xfffffffe;
392 /* set the trace bit if we're stepping */
393 if (remcom_in_buffer[0] == 's') {
395 kgdb_single_step = regs->ipend;
396 kgdb_single_step >>= 6;
397 for (i = 10; i > 0; i--, kgdb_single_step >>= 1)
398 if (kgdb_single_step & 1)
400 /* i indicate event priority of current stopped instruction
401 * user space instruction is 0, IVG15 is 1, IVTMR is 10.
402 * kgdb_single_step > 0 means in single step mode
404 kgdb_single_step = i + 1;
407 bfin_correct_hw_break();
411 return -1; /* this means that we do not want to exit from the handler */
414 struct kgdb_arch arch_kgdb_ops = {
415 .gdb_bpt_instr = {0xa1},
417 .flags = KGDB_HW_BREAKPOINT|KGDB_THR_PROC_SWAP,
419 .flags = KGDB_HW_BREAKPOINT,
421 .set_hw_breakpoint = bfin_set_hw_break,
422 .remove_hw_breakpoint = bfin_remove_hw_break,
423 .remove_all_hw_break = bfin_remove_all_hw_break,
424 .correct_hw_break = bfin_correct_hw_break,
427 static int hex(char ch)
429 if ((ch >= 'a') && (ch <= 'f'))
430 return ch - 'a' + 10;
431 if ((ch >= '0') && (ch <= '9'))
433 if ((ch >= 'A') && (ch <= 'F'))
434 return ch - 'A' + 10;
438 static int validate_memory_access_address(unsigned long addr, int size)
440 if (size < 0 || addr == 0)
442 return bfin_mem_access_type(addr, size);
445 static int bfin_probe_kernel_read(char *dst, char *src, int size)
447 unsigned long lsrc = (unsigned long)src;
450 mem_type = validate_memory_access_address(lsrc, size);
454 if (lsrc >= SYSMMR_BASE) {
455 if (size == 2 && lsrc % 2 == 0) {
456 u16 mmr = bfin_read16(src);
457 memcpy(dst, &mmr, sizeof(mmr));
459 } else if (size == 4 && lsrc % 4 == 0) {
460 u32 mmr = bfin_read32(src);
461 memcpy(dst, &mmr, sizeof(mmr));
466 case BFIN_MEM_ACCESS_CORE:
467 case BFIN_MEM_ACCESS_CORE_ONLY:
468 return probe_kernel_read(dst, src, size);
469 /* XXX: should support IDMA here with SMP */
470 case BFIN_MEM_ACCESS_DMA:
471 if (dma_memcpy(dst, src, size))
474 case BFIN_MEM_ACCESS_ITEST:
475 if (isram_memcpy(dst, src, size))
484 static int bfin_probe_kernel_write(char *dst, char *src, int size)
486 unsigned long ldst = (unsigned long)dst;
489 mem_type = validate_memory_access_address(ldst, size);
493 if (ldst >= SYSMMR_BASE) {
494 if (size == 2 && ldst % 2 == 0) {
496 memcpy(&mmr, src, sizeof(mmr));
497 bfin_write16(dst, mmr);
499 } else if (size == 4 && ldst % 4 == 0) {
501 memcpy(&mmr, src, sizeof(mmr));
502 bfin_write32(dst, mmr);
507 case BFIN_MEM_ACCESS_CORE:
508 case BFIN_MEM_ACCESS_CORE_ONLY:
509 return probe_kernel_write(dst, src, size);
510 /* XXX: should support IDMA here with SMP */
511 case BFIN_MEM_ACCESS_DMA:
512 if (dma_memcpy(dst, src, size))
515 case BFIN_MEM_ACCESS_ITEST:
516 if (isram_memcpy(dst, src, size))
526 * Convert the memory pointed to by mem into hex, placing result in buf.
527 * Return a pointer to the last char put in buf (null). May return an error.
529 int kgdb_mem2hex(char *mem, char *buf, int count)
535 * We use the upper half of buf as an intermediate buffer for the
536 * raw memory copy. Hex conversion will work against this one.
540 err = bfin_probe_kernel_read(tmp, mem, count);
543 buf = pack_hex_byte(buf, *tmp);
555 * Copy the binary array pointed to by buf into mem. Fix $, #, and
556 * 0x7d escaped with 0x7d. Return a pointer to the character after
557 * the last byte written.
559 int kgdb_ebin2mem(char *buf, char *mem, int count)
561 char *tmp_old, *tmp_new;
564 tmp_old = tmp_new = buf;
566 for (size = 0; size < count; ++size) {
567 if (*tmp_old == 0x7d)
568 *tmp_new = *(++tmp_old) ^ 0x20;
575 return bfin_probe_kernel_write(mem, buf, count);
579 * Convert the hex array pointed to by buf into binary to be placed in mem.
580 * Return a pointer to the character AFTER the last byte written.
581 * May return an error.
583 int kgdb_hex2mem(char *buf, char *mem, int count)
585 char *tmp_raw, *tmp_hex;
588 * We use the upper half of buf as an intermediate buffer for the
589 * raw memory that is converted from hex.
591 tmp_raw = buf + count * 2;
593 tmp_hex = tmp_raw - 1;
594 while (tmp_hex >= buf) {
596 *tmp_raw = hex(*tmp_hex--);
597 *tmp_raw |= hex(*tmp_hex--) << 4;
600 return bfin_probe_kernel_write(mem, tmp_raw, count);
603 #define IN_MEM(addr, size, l1_addr, l1_size) \
605 unsigned long __addr = (unsigned long)(addr); \
606 (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
608 #define ASYNC_BANK_SIZE \
609 (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
610 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
612 int kgdb_validate_break_address(unsigned long addr)
614 int cpu = raw_smp_processor_id();
616 if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
618 if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
620 if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
623 else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
626 if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH))
632 int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)
634 int err = bfin_probe_kernel_read(saved_instr, (char *)addr,
638 return bfin_probe_kernel_write((char *)addr, arch_kgdb_ops.gdb_bpt_instr,
642 int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle)
644 return bfin_probe_kernel_write((char *)addr, bundle, BREAK_INSTR_SIZE);
647 int kgdb_arch_init(void)
649 kgdb_single_step = 0;
651 bfin_remove_all_hw_break();
655 void kgdb_arch_exit(void)