2 * Blackfin CPLB exception handling.
3 * Copyright 2004-2007 Analog Devices Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see the file COPYING, or write
17 * to the Free Software Foundation, Inc.,
18 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/module.h>
23 #include <asm/blackfin.h>
24 #include <asm/cacheflush.h>
25 #include <asm/cplbinit.h>
26 #include <asm/mmu_context.h>
28 #define FAULT_RW (1 << 16)
29 #define FAULT_USERSUPV (1 << 17)
33 unsigned long *current_rwx_mask[NR_CPUS];
35 int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
36 int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
37 int nr_cplb_flush[NR_CPUS];
39 static inline void disable_dcplb(void)
43 ctrl = bfin_read_DMEM_CONTROL();
45 bfin_write_DMEM_CONTROL(ctrl);
49 static inline void enable_dcplb(void)
53 ctrl = bfin_read_DMEM_CONTROL();
55 bfin_write_DMEM_CONTROL(ctrl);
59 static inline void disable_icplb(void)
63 ctrl = bfin_read_IMEM_CONTROL();
65 bfin_write_IMEM_CONTROL(ctrl);
69 static inline void enable_icplb(void)
73 ctrl = bfin_read_IMEM_CONTROL();
75 bfin_write_IMEM_CONTROL(ctrl);
80 * Given the contents of the status register, return the index of the
81 * CPLB that caused the fault.
83 static inline int faulting_cplb_index(int status)
85 int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
90 * Given the contents of the status register and the DCPLB_DATA contents,
91 * return true if a write access should be permitted.
93 static inline int write_permitted(int status, unsigned long data)
95 if (status & FAULT_USERSUPV)
96 return !!(data & CPLB_SUPV_WR);
98 return !!(data & CPLB_USER_WR);
101 /* Counters to implement round-robin replacement. */
102 static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];
105 * Find an ICPLB entry to be evicted and return its index.
107 static int evict_one_icplb(unsigned int cpu)
110 for (i = first_switched_icplb; i < MAX_CPLBS; i++)
111 if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
113 i = first_switched_icplb + icplb_rr_index[cpu];
114 if (i >= MAX_CPLBS) {
115 i -= MAX_CPLBS - first_switched_icplb;
116 icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
118 icplb_rr_index[cpu]++;
122 static int evict_one_dcplb(unsigned int cpu)
125 for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
126 if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
128 i = first_switched_dcplb + dcplb_rr_index[cpu];
129 if (i >= MAX_CPLBS) {
130 i -= MAX_CPLBS - first_switched_dcplb;
131 dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
133 dcplb_rr_index[cpu]++;
137 static noinline int dcplb_miss(unsigned int cpu)
139 unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
140 int status = bfin_read_DCPLB_STATUS();
143 unsigned long d_data;
145 nr_dcplb_miss[cpu]++;
147 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
148 #ifdef CONFIG_BFIN_DCACHE
149 if (bfin_addr_dcachable(addr)) {
150 d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
151 #ifdef CONFIG_BFIN_WT
152 d_data |= CPLB_L1_AOW | CPLB_WT;
156 if (addr >= physical_mem_end) {
157 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE
158 && (status & FAULT_USERSUPV)) {
160 d_data &= ~PAGE_SIZE_4KB;
161 d_data |= PAGE_SIZE_4MB;
162 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
163 && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
164 addr &= ~(1 * 1024 * 1024 - 1);
165 d_data &= ~PAGE_SIZE_4KB;
166 d_data |= PAGE_SIZE_1MB;
168 return CPLB_PROT_VIOL;
169 } else if (addr >= _ramend) {
170 d_data |= CPLB_USER_RD | CPLB_USER_WR;
172 mask = current_rwx_mask[cpu];
174 int page = addr >> PAGE_SHIFT;
176 int bit = 1 << (page & 31);
179 d_data |= CPLB_USER_RD;
181 mask += page_mask_nelts;
183 d_data |= CPLB_USER_WR;
186 idx = evict_one_dcplb(cpu);
189 dcplb_tbl[cpu][idx].addr = addr;
190 dcplb_tbl[cpu][idx].data = d_data;
193 bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
194 bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
200 static noinline int icplb_miss(unsigned int cpu)
202 unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
203 int status = bfin_read_ICPLB_STATUS();
205 unsigned long i_data;
207 nr_icplb_miss[cpu]++;
209 /* If inside the uncached DMA region, fault. */
210 if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
211 return CPLB_PROT_VIOL;
213 if (status & FAULT_USERSUPV)
214 nr_icplb_supv_miss[cpu]++;
217 * First, try to find a CPLB that matches this address. If we
218 * find one, then the fact that we're in the miss handler means
219 * that the instruction crosses a page boundary.
221 for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
222 if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
223 unsigned long this_addr = icplb_tbl[cpu][idx].addr;
224 if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
231 i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
233 #ifdef CONFIG_BFIN_ICACHE
235 * Normal RAM, and possibly the reserved memory area, are
238 if (addr < _ramend ||
239 (addr < physical_mem_end && reserved_mem_icache_on))
240 i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
243 if (addr >= physical_mem_end) {
244 if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
245 && (status & FAULT_USERSUPV)) {
246 addr &= ~(1 * 1024 * 1024 - 1);
247 i_data &= ~PAGE_SIZE_4KB;
248 i_data |= PAGE_SIZE_1MB;
250 return CPLB_PROT_VIOL;
251 } else if (addr >= _ramend) {
252 i_data |= CPLB_USER_RD;
255 * Two cases to distinguish - a supervisor access must
256 * necessarily be for a module page; we grant it
257 * unconditionally (could do better here in the future).
258 * Otherwise, check the x bitmap of the current process.
260 if (!(status & FAULT_USERSUPV)) {
261 unsigned long *mask = current_rwx_mask[cpu];
264 int page = addr >> PAGE_SHIFT;
266 int bit = 1 << (page & 31);
268 mask += 2 * page_mask_nelts;
270 i_data |= CPLB_USER_RD;
274 idx = evict_one_icplb(cpu);
276 icplb_tbl[cpu][idx].addr = addr;
277 icplb_tbl[cpu][idx].data = i_data;
280 bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
281 bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
287 static noinline int dcplb_protection_fault(unsigned int cpu)
289 int status = bfin_read_DCPLB_STATUS();
291 nr_dcplb_prot[cpu]++;
293 if (status & FAULT_RW) {
294 int idx = faulting_cplb_index(status);
295 unsigned long data = dcplb_tbl[cpu][idx].data;
296 if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
297 write_permitted(status, data)) {
299 dcplb_tbl[cpu][idx].data = data;
300 bfin_write32(DCPLB_DATA0 + idx * 4, data);
304 return CPLB_PROT_VIOL;
307 int cplb_hdr(int seqstat, struct pt_regs *regs)
309 int cause = seqstat & 0x3f;
310 unsigned int cpu = smp_processor_id();
313 return dcplb_protection_fault(cpu);
315 return icplb_miss(cpu);
317 return dcplb_miss(cpu);
323 void flush_switched_cplbs(unsigned int cpu)
328 nr_cplb_flush[cpu]++;
330 local_irq_save(flags);
332 for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
333 icplb_tbl[cpu][i].data = 0;
334 bfin_write32(ICPLB_DATA0 + i * 4, 0);
339 for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
340 dcplb_tbl[cpu][i].data = 0;
341 bfin_write32(DCPLB_DATA0 + i * 4, 0);
344 local_irq_restore(flags);
348 void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
351 unsigned long addr = (unsigned long)masks;
352 unsigned long d_data;
356 current_rwx_mask[cpu] = masks;
360 local_irq_save(flags);
361 current_rwx_mask[cpu] = masks;
363 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
364 #ifdef CONFIG_BFIN_DCACHE
365 d_data |= CPLB_L1_CHBL;
366 #ifdef CONFIG_BFIN_WT
367 d_data |= CPLB_L1_AOW | CPLB_WT;
372 for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
373 dcplb_tbl[cpu][i].addr = addr;
374 dcplb_tbl[cpu][i].data = d_data;
375 bfin_write32(DCPLB_DATA0 + i * 4, d_data);
376 bfin_write32(DCPLB_ADDR0 + i * 4, addr);
380 local_irq_restore(flags);