arch/blackfin/include/asm/bfin_twi.h

   1 /*
   2  * bfin_twi.h - interface to Blackfin TWIs
   3  *
   4  * Copyright 2005-2010 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #ifndef __ASM_BFIN_TWI_H__
  10 #define __ASM_BFIN_TWI_H__
  11
  12 #include <linux/types.h>
  13
  14 /*
  15  * All Blackfin system MMRs are padded to 32bits even if the register
  16  * itself is only 16bits.  So use a helper macro to streamline this.
  17  */
  18 #define __BFP(m) u16 m; u16 __pad_##m
  19
  20 /*
  21  * bfin twi registers layout
  22  */
  23 struct bfin_twi_regs {
  24         __BFP(clkdiv);
  25         __BFP(control);
  26         __BFP(slave_ctl);
  27         __BFP(slave_stat);
  28         __BFP(slave_addr);
  29         __BFP(master_ctl);
  30         __BFP(master_stat);
  31         __BFP(master_addr);
  32         __BFP(int_stat);
  33         __BFP(int_mask);
  34         __BFP(fifo_ctl);
  35         __BFP(fifo_stat);
  36         u32 __pad[20];
  37         __BFP(xmt_data8);
  38         __BFP(xmt_data16);
  39         __BFP(rcv_data8);
  40         __BFP(rcv_data16);
  41 };
  42
  43 #undef __BFP
  44
  45 struct bfin_twi_iface {
  46         int                     irq;
  47         spinlock_t              lock;
  48         char                    read_write;
  49         u8                      command;
  50         u8                      *transPtr;
  51         int                     readNum;
  52         int                     writeNum;
  53         int                     cur_mode;
  54         int                     manual_stop;
  55         int                     result;
  56         struct i2c_adapter      adap;
  57         struct completion       complete;
  58         struct i2c_msg          *pmsg;
  59         int                     msg_num;
  60         int                     cur_msg;
  61         u16                     saved_clkdiv;
  62         u16                     saved_control;
  63         struct bfin_twi_regs    *regs_base;
  64 };
  65
  66 #define DEFINE_TWI_REG(reg_name, reg) \
  67 static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
  68         { return iface->regs_base->reg; } \
  69 static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
  70         { iface->regs_base->reg = v; }
  71
  72 DEFINE_TWI_REG(CLKDIV, clkdiv)
  73 DEFINE_TWI_REG(CONTROL, control)
  74 DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
  75 DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
  76 DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
  77 DEFINE_TWI_REG(MASTER_CTL, master_ctl)
  78 DEFINE_TWI_REG(MASTER_STAT, master_stat)
  79 DEFINE_TWI_REG(MASTER_ADDR, master_addr)
  80 DEFINE_TWI_REG(INT_STAT, int_stat)
  81 DEFINE_TWI_REG(INT_MASK, int_mask)
  82 DEFINE_TWI_REG(FIFO_CTL, fifo_ctl)
  83 DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
  84 DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
  85 DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
  86 DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
  87 DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
  88
  89 /*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
  90 /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
  91 #define CLKLOW(x)       ((x) & 0xFF)    /* Periods Clock Is Held Low                    */
  92 #define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
  93
  94 /* TWI_PRESCALE Masks                                                                                                                   */
  95 #define PRESCALE        0x007F  /* SCLKs Per Internal Time Reference (10MHz)    */
  96 #define TWI_ENA         0x0080  /* TWI Enable                                                                   */
  97 #define SCCB            0x0200  /* SCCB Compatibility Enable                                    */
  98
  99 /* TWI_SLAVE_CTL Masks                                                                                                                  */
 100 #define SEN                     0x0001  /* Slave Enable                                                                 */
 101 #define SADD_LEN        0x0002  /* Slave Address Length                                                 */
 102 #define STDVAL          0x0004  /* Slave Transmit Data Valid                                    */
 103 #define NAK                     0x0008  /* NAK/ACK* Generated At Conclusion Of Transfer */
 104 #define GEN                     0x0010  /* General Call Address Matching Enabled                */
 105
 106 /* TWI_SLAVE_STAT Masks                                                                                                                 */
 107 #define SDIR            0x0001  /* Slave Transfer Direction (Transmit/Receive*) */
 108 #define GCALL           0x0002  /* General Call Indicator                                               */
 109
 110 /* TWI_MASTER_CTL Masks                                                                                                 */
 111 #define MEN                     0x0001  /* Master Mode Enable                                           */
 112 #define MADD_LEN        0x0002  /* Master Address Length                                        */
 113 #define MDIR            0x0004  /* Master Transmit Direction (RX/TX*)           */
 114 #define FAST            0x0008  /* Use Fast Mode Timing Specs                           */
 115 #define STOP            0x0010  /* Issue Stop Condition                                         */
 116 #define RSTART          0x0020  /* Repeat Start or Stop* At End Of Transfer     */
 117 #define DCNT            0x3FC0  /* Data Bytes To Transfer                                       */
 118 #define SDAOVR          0x4000  /* Serial Data Override                                         */
 119 #define SCLOVR          0x8000  /* Serial Clock Override                                        */
 120
 121 /* TWI_MASTER_STAT Masks                                                                                                                */
 122 #define MPROG           0x0001  /* Master Transfer In Progress                                  */
 123 #define LOSTARB         0x0002  /* Lost Arbitration Indicator (Xfer Aborted)    */
 124 #define ANAK            0x0004  /* Address Not Acknowledged                                             */
 125 #define DNAK            0x0008  /* Data Not Acknowledged                                                */
 126 #define BUFRDERR        0x0010  /* Buffer Read Error                                                    */
 127 #define BUFWRERR        0x0020  /* Buffer Write Error                                                   */
 128 #define SDASEN          0x0040  /* Serial Data Sense                                                    */
 129 #define SCLSEN          0x0080  /* Serial Clock Sense                                                   */
 130 #define BUSBUSY         0x0100  /* Bus Busy Indicator                                                   */
 131
 132 /* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
 133 #define SINIT           0x0001  /* Slave Transfer Initiated     */
 134 #define SCOMP           0x0002  /* Slave Transfer Complete      */
 135 #define SERR            0x0004  /* Slave Transfer Error         */
 136 #define SOVF            0x0008  /* Slave Overflow                       */
 137 #define MCOMP           0x0010  /* Master Transfer Complete     */
 138 #define MERR            0x0020  /* Master Transfer Error        */
 139 #define XMTSERV         0x0040  /* Transmit FIFO Service        */
 140 #define RCVSERV         0x0080  /* Receive FIFO Service         */
 141
 142 /* TWI_FIFO_CTRL Masks                                                                                          */
 143 #define XMTFLUSH        0x0001  /* Transmit Buffer Flush                        */
 144 #define RCVFLUSH        0x0002  /* Receive Buffer Flush                         */
 145 #define XMTINTLEN       0x0004  /* Transmit Buffer Interrupt Length     */
 146 #define RCVINTLEN       0x0008  /* Receive Buffer Interrupt Length      */
 147
 148 /* TWI_FIFO_STAT Masks                                                                                                                  */
 149 #define XMTSTAT         0x0003  /* Transmit FIFO Status                                                 */
 150 #define XMT_EMPTY       0x0000  /*              Transmit FIFO Empty                                             */
 151 #define XMT_HALF        0x0001  /*              Transmit FIFO Has 1 Byte To Write               */
 152 #define XMT_FULL        0x0003  /*              Transmit FIFO Full (2 Bytes To Write)   */
 153
 154 #define RCVSTAT         0x000C  /* Receive FIFO Status                                                  */
 155 #define RCV_EMPTY       0x0000  /*              Receive FIFO Empty                                              */
 156 #define RCV_HALF        0x0004  /*              Receive FIFO Has 1 Byte To Read                 */
 157 #define RCV_FULL        0x000C  /*              Receive FIFO Full (2 Bytes To Read)             */
 158
 159 #endif