2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
18 config RWSEM_GENERIC_SPINLOCK
21 config RWSEM_XCHGADD_ALGORITHM
27 select HAVE_ARCH_TRACEHOOK
28 select HAVE_FUNCTION_GRAPH_TRACER
29 select HAVE_FUNCTION_TRACER
30 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
32 select HAVE_KERNEL_GZIP if RAMKERNEL
33 select HAVE_KERNEL_BZIP2 if RAMKERNEL
34 select HAVE_KERNEL_LZMA if RAMKERNEL
36 select ARCH_WANT_OPTIONAL_GPIOLIB
48 config GENERIC_FIND_NEXT_BIT
51 config GENERIC_HARDIRQS
54 config GENERIC_IRQ_PROBE
57 config GENERIC_HARDIRQS_NO__DO_IRQ
63 config FORCE_MAX_ZONEORDER
67 config GENERIC_CALIBRATE_DELAY
70 config LOCKDEP_SUPPORT
73 config STACKTRACE_SUPPORT
76 config TRACE_IRQFLAGS_SUPPORT
81 source "kernel/Kconfig.preempt"
83 source "kernel/Kconfig.freezer"
85 menu "Blackfin Processor Options"
87 comment "Processor and Board Settings"
96 BF512 Processor Support.
101 BF514 Processor Support.
106 BF516 Processor Support.
111 BF518 Processor Support.
116 BF522 Processor Support.
121 BF523 Processor Support.
126 BF524 Processor Support.
131 BF525 Processor Support.
136 BF526 Processor Support.
141 BF527 Processor Support.
146 BF531 Processor Support.
151 BF532 Processor Support.
156 BF533 Processor Support.
161 BF534 Processor Support.
166 BF536 Processor Support.
171 BF537 Processor Support.
176 BF538 Processor Support.
181 BF539 Processor Support.
186 BF542 Processor Support.
191 BF542 Processor Support.
196 BF544 Processor Support.
201 BF544 Processor Support.
206 BF547 Processor Support.
211 BF547 Processor Support.
216 BF548 Processor Support.
221 BF548 Processor Support.
226 BF549 Processor Support.
231 BF549 Processor Support.
236 BF561 Processor Support.
242 select TICKSOURCE_CORETMR
243 bool "Symmetric multi-processing support"
245 This enables support for systems with more than one CPU,
246 like the dual core BF561. If you have a system with only one
247 CPU, say N. If you have a system with more than one CPU, say Y.
249 If you don't know what to do here, say N.
257 bool "Support for hot-pluggable CPUs"
258 depends on SMP && HOTPLUG
266 config HAVE_LEGACY_PER_CPU_AREA
272 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
273 default 2 if (BF537 || BF536 || BF534)
274 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
275 default 4 if (BF538 || BF539)
279 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
280 default 3 if (BF537 || BF536 || BF534 || BF54xM)
281 default 5 if (BF561 || BF538 || BF539)
282 default 6 if (BF533 || BF532 || BF531)
286 default BF_REV_0_0 if (BF51x || BF52x)
287 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
288 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
292 depends on (BF51x || BF52x || (BF54x && !BF54xM))
296 depends on (BF51x || BF52x || (BF54x && !BF54xM))
300 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
304 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
308 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
312 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
316 depends on (BF533 || BF532 || BF531)
328 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
331 config MEM_GENERIC_BOARD
333 depends on GENERIC_BOARD
336 config MEM_MT48LC64M4A2FB_7E
338 depends on (BFIN533_STAMP)
341 config MEM_MT48LC16M16A2TG_75
343 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
344 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
345 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
346 || BFIN527_BLUETECHNIX_CM)
349 config MEM_MT48LC32M8A2_75
351 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
354 config MEM_MT48LC8M32B2B5_7
356 depends on (BFIN561_BLUETECHNIX_CM)
359 config MEM_MT48LC32M16A2TG_75
361 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
364 config MEM_MT48H32M16LFCJ_75
366 depends on (BFIN526_EZBRD)
369 source "arch/blackfin/mach-bf518/Kconfig"
370 source "arch/blackfin/mach-bf527/Kconfig"
371 source "arch/blackfin/mach-bf533/Kconfig"
372 source "arch/blackfin/mach-bf561/Kconfig"
373 source "arch/blackfin/mach-bf537/Kconfig"
374 source "arch/blackfin/mach-bf538/Kconfig"
375 source "arch/blackfin/mach-bf548/Kconfig"
377 menu "Board customizations"
380 bool "Default bootloader kernel arguments"
383 string "Initial kernel command string"
384 depends on CMDLINE_BOOL
385 default "console=ttyBF0,57600"
387 If you don't have a boot loader capable of passing a command line string
388 to the kernel, you may specify one here. As a minimum, you should specify
389 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
392 hex "Kernel load address for booting"
394 range 0x1000 0x20000000
396 This option allows you to set the load address of the kernel.
397 This can be useful if you are on a board which has a small amount
398 of memory or you wish to reserve some memory at the beginning of
401 Note that you need to keep this value above 4k (0x1000) as this
402 memory region is used to capture NULL pointer references as well
403 as some core kernel functions.
406 hex "Kernel ROM Base"
409 range 0x20000000 0x20400000 if !(BF54x || BF561)
410 range 0x20000000 0x30000000 if (BF54x || BF561)
412 Make sure your ROM base does not include any file-header
413 information that is prepended to the kernel.
415 For example, the bootable U-Boot format (created with
416 mkimage) has a 64 byte header (0x40). So while the image
417 you write to flash might start at say 0x20080000, you have
418 to add 0x40 to get the kernel's ROM base as it will come
421 comment "Clock/PLL Setup"
424 int "Frequency of the crystal on the board in Hz"
425 default "10000000" if BFIN532_IP0X
426 default "11059200" if BFIN533_STAMP
427 default "24576000" if PNAV10
428 default "25000000" # most people use this
429 default "27000000" if BFIN533_EZKIT
430 default "30000000" if BFIN561_EZKIT
432 The frequency of CLKIN crystal oscillator on the board in Hz.
433 Warning: This value should match the crystal on the board. Otherwise,
434 peripherals won't work properly.
436 config BFIN_KERNEL_CLOCK
437 bool "Re-program Clocks while Kernel boots?"
440 This option decides if kernel clocks are re-programed from the
441 bootloader settings. If the clocks are not set, the SDRAM settings
442 are also not changed, and the Bootloader does 100% of the hardware
447 depends on BFIN_KERNEL_CLOCK
452 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
455 If this is set the clock will be divided by 2, before it goes to the PLL.
459 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
461 default "22" if BFIN533_EZKIT
462 default "45" if BFIN533_STAMP
463 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
464 default "22" if BFIN533_BLUETECHNIX_CM
465 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
466 default "20" if BFIN561_EZKIT
467 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
469 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
470 PLL Frequency = (Crystal Frequency) * (this setting)
473 prompt "Core Clock Divider"
474 depends on BFIN_KERNEL_CLOCK
477 This sets the frequency of the core. It can be 1, 2, 4 or 8
478 Core Frequency = (PLL frequency) / (this setting)
494 int "System Clock Divider"
495 depends on BFIN_KERNEL_CLOCK
499 This sets the frequency of the system clock (including SDRAM or DDR).
500 This can be between 1 and 15
501 System Clock = (PLL frequency) / (this setting)
504 prompt "DDR SDRAM Chip Type"
505 depends on BFIN_KERNEL_CLOCK
507 default MEM_MT46V32M16_5B
509 config MEM_MT46V32M16_6T
512 config MEM_MT46V32M16_5B
517 prompt "DDR/SDRAM Timing"
518 depends on BFIN_KERNEL_CLOCK
519 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
521 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
522 The calculated SDRAM timing parameters may not be 100%
523 accurate - This option is therefore marked experimental.
525 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
526 bool "Calculate Timings (EXPERIMENTAL)"
527 depends on EXPERIMENTAL
529 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
530 bool "Provide accurate Timings based on target SCLK"
532 Please consult the Blackfin Hardware Reference Manuals as well
533 as the memory device datasheet.
534 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
537 menu "Memory Init Control"
538 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
555 config MEM_EBIU_DDRQUE
572 # Max & Min Speeds for various Chips
576 default 400000000 if BF512
577 default 400000000 if BF514
578 default 400000000 if BF516
579 default 400000000 if BF518
580 default 400000000 if BF522
581 default 600000000 if BF523
582 default 400000000 if BF524
583 default 600000000 if BF525
584 default 400000000 if BF526
585 default 600000000 if BF527
586 default 400000000 if BF531
587 default 400000000 if BF532
588 default 750000000 if BF533
589 default 500000000 if BF534
590 default 400000000 if BF536
591 default 600000000 if BF537
592 default 533333333 if BF538
593 default 533333333 if BF539
594 default 600000000 if BF542
595 default 533333333 if BF544
596 default 600000000 if BF547
597 default 600000000 if BF548
598 default 533333333 if BF549
599 default 600000000 if BF561
613 comment "Kernel Timer/Scheduler"
615 source kernel/Kconfig.hz
617 config GENERIC_CLOCKEVENTS
618 bool "Generic clock events"
621 menu "Clock event device"
622 depends on GENERIC_CLOCKEVENTS
623 config TICKSOURCE_GPTMR0
628 config TICKSOURCE_CORETMR
634 depends on GENERIC_CLOCKEVENTS
635 config CYCLES_CLOCKSOURCE
638 depends on !BFIN_SCRATCH_REG_CYCLES
641 If you say Y here, you will enable support for using the 'cycles'
642 registers as a clock source. Doing so means you will be unable to
643 safely write to the 'cycles' register during runtime. You will
644 still be able to read it (such as for performance monitoring), but
645 writing the registers will most likely crash the kernel.
647 config GPTMR0_CLOCKSOURCE
650 depends on !TICKSOURCE_GPTMR0
653 config ARCH_USES_GETTIMEOFFSET
654 depends on !GENERIC_CLOCKEVENTS
657 source kernel/time/Kconfig
662 prompt "Blackfin Exception Scratch Register"
663 default BFIN_SCRATCH_REG_RETN
665 Select the resource to reserve for the Exception handler:
666 - RETN: Non-Maskable Interrupt (NMI)
667 - RETE: Exception Return (JTAG/ICE)
668 - CYCLES: Performance counter
670 If you are unsure, please select "RETN".
672 config BFIN_SCRATCH_REG_RETN
675 Use the RETN register in the Blackfin exception handler
676 as a stack scratch register. This means you cannot
677 safely use NMI on the Blackfin while running Linux, but
678 you can debug the system with a JTAG ICE and use the
679 CYCLES performance registers.
681 If you are unsure, please select "RETN".
683 config BFIN_SCRATCH_REG_RETE
686 Use the RETE register in the Blackfin exception handler
687 as a stack scratch register. This means you cannot
688 safely use a JTAG ICE while debugging a Blackfin board,
689 but you can safely use the CYCLES performance registers
692 If you are unsure, please select "RETN".
694 config BFIN_SCRATCH_REG_CYCLES
697 Use the CYCLES register in the Blackfin exception handler
698 as a stack scratch register. This means you cannot
699 safely use the CYCLES performance registers on a Blackfin
700 board at anytime, but you can debug the system with a JTAG
703 If you are unsure, please select "RETN".
710 menu "Blackfin Kernel Optimizations"
713 comment "Memory Optimizations"
716 bool "Locate interrupt entry code in L1 Memory"
719 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
720 into L1 instruction memory. (less latency)
722 config EXCPT_IRQ_SYSC_L1
723 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
726 If enabled, the entire ASM lowlevel exception and interrupt entry code
727 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
731 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
734 If enabled, the frequently called do_irq dispatcher function is linked
735 into L1 instruction memory. (less latency)
737 config CORE_TIMER_IRQ_L1
738 bool "Locate frequently called timer_interrupt() function in L1 Memory"
741 If enabled, the frequently called timer_interrupt() function is linked
742 into L1 instruction memory. (less latency)
745 bool "Locate frequently idle function in L1 Memory"
748 If enabled, the frequently called idle function is linked
749 into L1 instruction memory. (less latency)
752 bool "Locate kernel schedule function in L1 Memory"
755 If enabled, the frequently called kernel schedule is linked
756 into L1 instruction memory. (less latency)
758 config ARITHMETIC_OPS_L1
759 bool "Locate kernel owned arithmetic functions in L1 Memory"
762 If enabled, arithmetic functions are linked
763 into L1 instruction memory. (less latency)
766 bool "Locate access_ok function in L1 Memory"
769 If enabled, the access_ok function is linked
770 into L1 instruction memory. (less latency)
773 bool "Locate memset function in L1 Memory"
776 If enabled, the memset function is linked
777 into L1 instruction memory. (less latency)
780 bool "Locate memcpy function in L1 Memory"
783 If enabled, the memcpy function is linked
784 into L1 instruction memory. (less latency)
787 bool "locate strcmp function in L1 Memory"
790 If enabled, the strcmp function is linked
791 into L1 instruction memory (less latency).
794 bool "locate strncmp function in L1 Memory"
797 If enabled, the strncmp function is linked
798 into L1 instruction memory (less latency).
801 bool "locate strcpy function in L1 Memory"
804 If enabled, the strcpy function is linked
805 into L1 instruction memory (less latency).
808 bool "locate strncpy function in L1 Memory"
811 If enabled, the strncpy function is linked
812 into L1 instruction memory (less latency).
814 config SYS_BFIN_SPINLOCK_L1
815 bool "Locate sys_bfin_spinlock function in L1 Memory"
818 If enabled, sys_bfin_spinlock function is linked
819 into L1 instruction memory. (less latency)
821 config IP_CHECKSUM_L1
822 bool "Locate IP Checksum function in L1 Memory"
825 If enabled, the IP Checksum function is linked
826 into L1 instruction memory. (less latency)
828 config CACHELINE_ALIGNED_L1
829 bool "Locate cacheline_aligned data to L1 Data Memory"
834 If enabled, cacheline_aligned data is linked
835 into L1 data memory. (less latency)
837 config SYSCALL_TAB_L1
838 bool "Locate Syscall Table L1 Data Memory"
842 If enabled, the Syscall LUT is linked
843 into L1 data memory. (less latency)
845 config CPLB_SWITCH_TAB_L1
846 bool "Locate CPLB Switch Tables L1 Data Memory"
850 If enabled, the CPLB Switch Tables are linked
851 into L1 data memory. (less latency)
854 bool "Support locating application stack in L1 Scratch Memory"
857 If enabled the application stack can be located in L1
858 scratch memory (less latency).
860 Currently only works with FLAT binaries.
862 config EXCEPTION_L1_SCRATCH
863 bool "Locate exception stack in L1 Scratch Memory"
865 depends on !APP_STACK_L1
867 Whenever an exception occurs, use the L1 Scratch memory for
868 stack storage. You cannot place the stacks of FLAT binaries
869 in L1 when using this option.
871 If you don't use L1 Scratch, then you should say Y here.
873 comment "Speed Optimizations"
874 config BFIN_INS_LOWOVERHEAD
875 bool "ins[bwl] low overhead, higher interrupt latency"
878 Reads on the Blackfin are speculative. In Blackfin terms, this means
879 they can be interrupted at any time (even after they have been issued
880 on to the external bus), and re-issued after the interrupt occurs.
881 For memory - this is not a big deal, since memory does not change if
884 If a FIFO is sitting on the end of the read, it will see two reads,
885 when the core only sees one since the FIFO receives both the read
886 which is cancelled (and not delivered to the core) and the one which
887 is re-issued (which is delivered to the core).
889 To solve this, interrupts are turned off before reads occur to
890 I/O space. This option controls which the overhead/latency of
891 controlling interrupts during this time
892 "n" turns interrupts off every read
893 (higher overhead, but lower interrupt latency)
894 "y" turns interrupts off every loop
895 (low overhead, but longer interrupt latency)
897 default behavior is to leave this set to on (type "Y"). If you are experiencing
898 interrupt latency issues, it is safe and OK to turn this off.
903 prompt "Kernel executes from"
905 Choose the memory type that the kernel will be running in.
910 The kernel will be resident in RAM when running.
915 The kernel will be resident in FLASH/ROM when running.
922 tristate "Enable Blackfin General Purpose Timers API"
925 Enable support for the General Purpose Timers API. If you
928 To compile this driver as a module, choose M here: the module
929 will be called gptimers.
932 prompt "Uncached DMA region"
933 default DMA_UNCACHED_1M
934 config DMA_UNCACHED_4M
935 bool "Enable 4M DMA region"
936 config DMA_UNCACHED_2M
937 bool "Enable 2M DMA region"
938 config DMA_UNCACHED_1M
939 bool "Enable 1M DMA region"
940 config DMA_UNCACHED_512K
941 bool "Enable 512K DMA region"
942 config DMA_UNCACHED_256K
943 bool "Enable 256K DMA region"
944 config DMA_UNCACHED_128K
945 bool "Enable 128K DMA region"
946 config DMA_UNCACHED_NONE
947 bool "Disable DMA region"
951 comment "Cache Support"
956 config BFIN_EXTMEM_ICACHEABLE
957 bool "Enable ICACHE for external memory"
958 depends on BFIN_ICACHE
960 config BFIN_L2_ICACHEABLE
961 bool "Enable ICACHE for L2 SRAM"
962 depends on BFIN_ICACHE
963 depends on BF54x || BF561
969 config BFIN_DCACHE_BANKA
970 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
971 depends on BFIN_DCACHE && !BF531
973 config BFIN_EXTMEM_DCACHEABLE
974 bool "Enable DCACHE for external memory"
975 depends on BFIN_DCACHE
978 prompt "External memory DCACHE policy"
979 depends on BFIN_EXTMEM_DCACHEABLE
980 default BFIN_EXTMEM_WRITEBACK if !SMP
981 default BFIN_EXTMEM_WRITETHROUGH if SMP
982 config BFIN_EXTMEM_WRITEBACK
987 Cached data will be written back to SDRAM only when needed.
988 This can give a nice increase in performance, but beware of
989 broken drivers that do not properly invalidate/flush their
992 Write Through Policy:
993 Cached data will always be written back to SDRAM when the
994 cache is updated. This is a completely safe setting, but
995 performance is worse than Write Back.
997 If you are unsure of the options and you want to be safe,
998 then go with Write Through.
1000 config BFIN_EXTMEM_WRITETHROUGH
1001 bool "Write through"
1004 Cached data will be written back to SDRAM only when needed.
1005 This can give a nice increase in performance, but beware of
1006 broken drivers that do not properly invalidate/flush their
1009 Write Through Policy:
1010 Cached data will always be written back to SDRAM when the
1011 cache is updated. This is a completely safe setting, but
1012 performance is worse than Write Back.
1014 If you are unsure of the options and you want to be safe,
1015 then go with Write Through.
1019 config BFIN_L2_DCACHEABLE
1020 bool "Enable DCACHE for L2 SRAM"
1021 depends on BFIN_DCACHE
1022 depends on (BF54x || BF561) && !SMP
1025 prompt "L2 SRAM DCACHE policy"
1026 depends on BFIN_L2_DCACHEABLE
1027 default BFIN_L2_WRITEBACK
1028 config BFIN_L2_WRITEBACK
1031 config BFIN_L2_WRITETHROUGH
1032 bool "Write through"
1036 comment "Memory Protection Unit"
1038 bool "Enable the memory protection unit (EXPERIMENTAL)"
1041 Use the processor's MPU to protect applications from accessing
1042 memory they do not own. This comes at a performance penalty
1043 and is recommended only for debugging.
1045 comment "Asynchronous Memory Configuration"
1047 menu "EBIU_AMGCTL Global Control"
1049 bool "Enable CLKOUT"
1053 bool "DMA has priority over core for ext. accesses"
1058 bool "Bank 0 16 bit packing enable"
1063 bool "Bank 1 16 bit packing enable"
1068 bool "Bank 2 16 bit packing enable"
1073 bool "Bank 3 16 bit packing enable"
1077 prompt "Enable Asynchronous Memory Banks"
1081 bool "Disable All Banks"
1084 bool "Enable Bank 0"
1086 config C_AMBEN_B0_B1
1087 bool "Enable Bank 0 & 1"
1089 config C_AMBEN_B0_B1_B2
1090 bool "Enable Bank 0 & 1 & 2"
1093 bool "Enable All Banks"
1097 menu "EBIU_AMBCTL Control"
1099 hex "Bank 0 (AMBCTL0.L)"
1102 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1103 used to control the Asynchronous Memory Bank 0 settings.
1106 hex "Bank 1 (AMBCTL0.H)"
1108 default 0x5558 if BF54x
1110 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1111 used to control the Asynchronous Memory Bank 1 settings.
1114 hex "Bank 2 (AMBCTL1.L)"
1117 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1118 used to control the Asynchronous Memory Bank 2 settings.
1121 hex "Bank 3 (AMBCTL1.H)"
1124 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1125 used to control the Asynchronous Memory Bank 3 settings.
1129 config EBIU_MBSCTLVAL
1130 hex "EBIU Bank Select Control Register"
1135 hex "Flash Memory Mode Control Register"
1140 hex "Flash Memory Bank Control Register"
1145 #############################################################################
1146 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1152 Support for PCI bus.
1154 source "drivers/pci/Kconfig"
1156 source "drivers/pcmcia/Kconfig"
1158 source "drivers/pci/hotplug/Kconfig"
1162 menu "Executable file formats"
1164 source "fs/Kconfig.binfmt"
1168 menu "Power management options"
1170 source "kernel/power/Kconfig"
1172 config ARCH_SUSPEND_POSSIBLE
1176 prompt "Standby Power Saving Mode"
1178 default PM_BFIN_SLEEP_DEEPER
1179 config PM_BFIN_SLEEP_DEEPER
1182 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1183 power dissipation by disabling the clock to the processor core (CCLK).
1184 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1185 to 0.85 V to provide the greatest power savings, while preserving the
1187 The PLL and system clock (SCLK) continue to operate at a very low
1188 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1189 the SDRAM is put into Self Refresh Mode. Typically an external event
1190 such as GPIO interrupt or RTC activity wakes up the processor.
1191 Various Peripherals such as UART, SPORT, PPI may not function as
1192 normal during Sleep Deeper, due to the reduced SCLK frequency.
1193 When in the sleep mode, system DMA access to L1 memory is not supported.
1195 If unsure, select "Sleep Deeper".
1197 config PM_BFIN_SLEEP
1200 Sleep Mode (High Power Savings) - The sleep mode reduces power
1201 dissipation by disabling the clock to the processor core (CCLK).
1202 The PLL and system clock (SCLK), however, continue to operate in
1203 this mode. Typically an external event or RTC activity will wake
1204 up the processor. When in the sleep mode, system DMA access to L1
1205 memory is not supported.
1207 If unsure, select "Sleep Deeper".
1210 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1213 config PM_BFIN_WAKE_PH6
1214 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1215 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1218 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1220 config PM_BFIN_WAKE_GP
1221 bool "Allow Wake-Up from GPIOs"
1222 depends on PM && BF54x
1225 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1226 (all processors, except ADSP-BF549). This option sets
1227 the general-purpose wake-up enable (GPWE) control bit to enable
1228 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1229 On ADSP-BF549 this option enables the the same functionality on the
1230 /MRXON pin also PH7.
1234 menu "CPU Frequency scaling"
1236 source "drivers/cpufreq/Kconfig"
1238 config BFIN_CPU_FREQ
1241 select CPU_FREQ_TABLE
1245 bool "CPU Voltage scaling"
1246 depends on EXPERIMENTAL
1250 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1251 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1252 manuals. There is a theoretical risk that during VDDINT transitions
1257 source "net/Kconfig"
1259 source "drivers/Kconfig"
1261 source "drivers/firmware/Kconfig"
1265 source "arch/blackfin/Kconfig.debug"
1267 source "security/Kconfig"
1269 source "crypto/Kconfig"
1271 source "lib/Kconfig"