1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/mm/fault.c
5 * Copyright (C) 1995 Linus Torvalds
6 * Copyright (C) 1995-2004 Russell King
7 * Copyright (C) 2012 ARM Ltd.
10 #include <linux/acpi.h>
11 #include <linux/bitfield.h>
12 #include <linux/extable.h>
13 #include <linux/signal.h>
15 #include <linux/hardirq.h>
16 #include <linux/init.h>
17 #include <linux/kprobes.h>
18 #include <linux/uaccess.h>
19 #include <linux/page-flags.h>
20 #include <linux/sched/signal.h>
21 #include <linux/sched/debug.h>
22 #include <linux/highmem.h>
23 #include <linux/perf_event.h>
24 #include <linux/preempt.h>
25 #include <linux/hugetlb.h>
29 #include <asm/cmpxchg.h>
30 #include <asm/cpufeature.h>
31 #include <asm/exception.h>
32 #include <asm/daifflags.h>
33 #include <asm/debug-monitors.h>
35 #include <asm/kprobes.h>
36 #include <asm/processor.h>
37 #include <asm/sysreg.h>
38 #include <asm/system_misc.h>
39 #include <asm/pgtable.h>
40 #include <asm/tlbflush.h>
41 #include <asm/traps.h>
44 int (*fn)(unsigned long addr, unsigned int esr,
45 struct pt_regs *regs);
51 static const struct fault_info fault_info[];
52 static struct fault_info debug_fault_info[];
54 static inline const struct fault_info *esr_to_fault_info(unsigned int esr)
56 return fault_info + (esr & ESR_ELx_FSC);
59 static inline const struct fault_info *esr_to_debug_fault_info(unsigned int esr)
61 return debug_fault_info + DBG_ESR_EVT(esr);
64 static void data_abort_decode(unsigned int esr)
66 pr_alert("Data abort info:\n");
68 if (esr & ESR_ELx_ISV) {
69 pr_alert(" Access size = %u byte(s)\n",
70 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT));
71 pr_alert(" SSE = %lu, SRT = %lu\n",
72 (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT,
73 (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT);
74 pr_alert(" SF = %lu, AR = %lu\n",
75 (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT,
76 (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT);
78 pr_alert(" ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK);
81 pr_alert(" CM = %lu, WnR = %lu\n",
82 (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT,
83 (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT);
86 static void mem_abort_decode(unsigned int esr)
88 pr_alert("Mem abort info:\n");
90 pr_alert(" ESR = 0x%08x\n", esr);
91 pr_alert(" EC = 0x%02lx: %s, IL = %u bits\n",
92 ESR_ELx_EC(esr), esr_get_class_string(esr),
93 (esr & ESR_ELx_IL) ? 32 : 16);
94 pr_alert(" SET = %lu, FnV = %lu\n",
95 (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT,
96 (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT);
97 pr_alert(" EA = %lu, S1PTW = %lu\n",
98 (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT,
99 (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT);
101 if (esr_is_data_abort(esr))
102 data_abort_decode(esr);
105 static inline unsigned long mm_to_pgd_phys(struct mm_struct *mm)
107 /* Either init_pg_dir or swapper_pg_dir */
109 return __pa_symbol(mm->pgd);
111 return (unsigned long)virt_to_phys(mm->pgd);
115 * Dump out the page tables associated with 'addr' in the currently active mm.
117 static void show_pte(unsigned long addr)
119 struct mm_struct *mm;
123 if (is_ttbr0_addr(addr)) {
125 mm = current->active_mm;
126 if (mm == &init_mm) {
127 pr_alert("[%016lx] user address but active_mm is swapper\n",
131 } else if (is_ttbr1_addr(addr)) {
135 pr_alert("[%016lx] address between user and kernel address ranges\n",
140 pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n",
141 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K,
142 vabits_actual, mm_to_pgd_phys(mm));
143 pgdp = pgd_offset(mm, addr);
144 pgd = READ_ONCE(*pgdp);
145 pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd));
153 if (pgd_none(pgd) || pgd_bad(pgd))
156 p4dp = p4d_offset(pgdp, addr);
157 p4d = READ_ONCE(*p4dp);
158 pr_cont(", p4d=%016llx", p4d_val(p4d));
159 if (p4d_none(p4d) || p4d_bad(p4d))
162 pudp = pud_offset(p4dp, addr);
163 pud = READ_ONCE(*pudp);
164 pr_cont(", pud=%016llx", pud_val(pud));
165 if (pud_none(pud) || pud_bad(pud))
168 pmdp = pmd_offset(pudp, addr);
169 pmd = READ_ONCE(*pmdp);
170 pr_cont(", pmd=%016llx", pmd_val(pmd));
171 if (pmd_none(pmd) || pmd_bad(pmd))
174 ptep = pte_offset_map(pmdp, addr);
175 pte = READ_ONCE(*ptep);
176 pr_cont(", pte=%016llx", pte_val(pte));
184 * This function sets the access flags (dirty, accessed), as well as write
185 * permission, and only to a more permissive setting.
187 * It needs to cope with hardware update of the accessed/dirty state by other
188 * agents in the system and can safely skip the __sync_icache_dcache() call as,
189 * like set_pte_at(), the PTE is never changed from no-exec to exec here.
191 * Returns whether or not the PTE actually changed.
193 int ptep_set_access_flags(struct vm_area_struct *vma,
194 unsigned long address, pte_t *ptep,
195 pte_t entry, int dirty)
197 pteval_t old_pteval, pteval;
198 pte_t pte = READ_ONCE(*ptep);
200 if (pte_same(pte, entry))
203 /* only preserve the access flags and write permission */
204 pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY;
207 * Setting the flags must be done atomically to avoid racing with the
208 * hardware update of the access/dirty state. The PTE_RDONLY bit must
209 * be set to the most permissive (lowest value) of *ptep and entry
210 * (calculated as: a & b == ~(~a | ~b)).
212 pte_val(entry) ^= PTE_RDONLY;
213 pteval = pte_val(pte);
216 pteval ^= PTE_RDONLY;
217 pteval |= pte_val(entry);
218 pteval ^= PTE_RDONLY;
219 pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval);
220 } while (pteval != old_pteval);
222 flush_tlb_fix_spurious_fault(vma, address);
226 static bool is_el1_instruction_abort(unsigned int esr)
228 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR;
231 static inline bool is_el1_permission_fault(unsigned long addr, unsigned int esr,
232 struct pt_regs *regs)
234 unsigned int ec = ESR_ELx_EC(esr);
235 unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE;
237 if (ec != ESR_ELx_EC_DABT_CUR && ec != ESR_ELx_EC_IABT_CUR)
240 if (fsc_type == ESR_ELx_FSC_PERM)
243 if (is_ttbr0_addr(addr) && system_uses_ttbr0_pan())
244 return fsc_type == ESR_ELx_FSC_FAULT &&
245 (regs->pstate & PSR_PAN_BIT);
250 static bool __kprobes is_spurious_el1_translation_fault(unsigned long addr,
252 struct pt_regs *regs)
257 if (ESR_ELx_EC(esr) != ESR_ELx_EC_DABT_CUR ||
258 (esr & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT)
261 local_irq_save(flags);
262 asm volatile("at s1e1r, %0" :: "r" (addr));
264 par = read_sysreg(par_el1);
265 local_irq_restore(flags);
268 * If we now have a valid translation, treat the translation fault as
271 if (!(par & SYS_PAR_EL1_F))
275 * If we got a different type of fault from the AT instruction,
276 * treat the translation fault as spurious.
278 dfsc = FIELD_GET(SYS_PAR_EL1_FST, par);
279 return (dfsc & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT;
282 static void die_kernel_fault(const char *msg, unsigned long addr,
283 unsigned int esr, struct pt_regs *regs)
287 pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg,
290 mem_abort_decode(esr);
293 die("Oops", regs, esr);
298 static void __do_kernel_fault(unsigned long addr, unsigned int esr,
299 struct pt_regs *regs)
304 * Are we prepared to handle this kernel fault?
305 * We are almost certainly not prepared to handle instruction faults.
307 if (!is_el1_instruction_abort(esr) && fixup_exception(regs))
310 if (WARN_RATELIMIT(is_spurious_el1_translation_fault(addr, esr, regs),
311 "Ignoring spurious kernel translation fault at virtual address %016lx\n", addr))
314 if (is_el1_permission_fault(addr, esr, regs)) {
315 if (esr & ESR_ELx_WNR)
316 msg = "write to read-only memory";
317 else if (is_el1_instruction_abort(esr))
318 msg = "execute from non-executable memory";
320 msg = "read from unreadable memory";
321 } else if (addr < PAGE_SIZE) {
322 msg = "NULL pointer dereference";
324 msg = "paging request";
327 die_kernel_fault(msg, addr, esr, regs);
330 static void set_thread_esr(unsigned long address, unsigned int esr)
332 current->thread.fault_address = address;
335 * If the faulting address is in the kernel, we must sanitize the ESR.
336 * From userspace's point of view, kernel-only mappings don't exist
337 * at all, so we report them as level 0 translation faults.
338 * (This is not quite the way that "no mapping there at all" behaves:
339 * an alignment fault not caused by the memory type would take
340 * precedence over translation fault for a real access to empty
341 * space. Unfortunately we can't easily distinguish "alignment fault
342 * not caused by memory type" from "alignment fault caused by memory
343 * type", so we ignore this wrinkle and just return the translation
346 if (!is_ttbr0_addr(current->thread.fault_address)) {
347 switch (ESR_ELx_EC(esr)) {
348 case ESR_ELx_EC_DABT_LOW:
350 * These bits provide only information about the
351 * faulting instruction, which userspace knows already.
352 * We explicitly clear bits which are architecturally
353 * RES0 in case they are given meanings in future.
354 * We always report the ESR as if the fault was taken
355 * to EL1 and so ISV and the bits in ISS[23:14] are
356 * clear. (In fact it always will be a fault to EL1.)
358 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL |
359 ESR_ELx_CM | ESR_ELx_WNR;
360 esr |= ESR_ELx_FSC_FAULT;
362 case ESR_ELx_EC_IABT_LOW:
364 * Claim a level 0 translation fault.
365 * All other bits are architecturally RES0 for faults
366 * reported with that DFSC value, so we clear them.
368 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL;
369 esr |= ESR_ELx_FSC_FAULT;
373 * This should never happen (entry.S only brings us
374 * into this code for insn and data aborts from a lower
375 * exception level). Fail safe by not providing an ESR
376 * context record at all.
378 WARN(1, "ESR 0x%x is not DABT or IABT from EL0\n", esr);
384 current->thread.fault_code = esr;
387 static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs)
390 * If we are in kernel mode at this point, we have no context to
391 * handle this fault with.
393 if (user_mode(regs)) {
394 const struct fault_info *inf = esr_to_fault_info(esr);
396 set_thread_esr(addr, esr);
397 arm64_force_sig_fault(inf->sig, inf->code, (void __user *)addr,
400 __do_kernel_fault(addr, esr, regs);
404 #define VM_FAULT_BADMAP 0x010000
405 #define VM_FAULT_BADACCESS 0x020000
407 static vm_fault_t __do_page_fault(struct mm_struct *mm, unsigned long addr,
408 unsigned int mm_flags, unsigned long vm_flags)
410 struct vm_area_struct *vma = find_vma(mm, addr);
413 return VM_FAULT_BADMAP;
416 * Ok, we have a good vm_area for this memory access, so we can handle
419 if (unlikely(vma->vm_start > addr)) {
420 if (!(vma->vm_flags & VM_GROWSDOWN))
421 return VM_FAULT_BADMAP;
422 if (expand_stack(vma, addr))
423 return VM_FAULT_BADMAP;
427 * Check that the permissions on the VMA allow for the fault which
430 if (!(vma->vm_flags & vm_flags))
431 return VM_FAULT_BADACCESS;
432 return handle_mm_fault(vma, addr & PAGE_MASK, mm_flags);
435 static bool is_el0_instruction_abort(unsigned int esr)
437 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW;
441 * Note: not valid for EL1 DC IVAC, but we never use that such that it
442 * should fault. EL0 cannot issue DC IVAC (undef).
444 static bool is_write_abort(unsigned int esr)
446 return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM);
449 static int __kprobes do_page_fault(unsigned long addr, unsigned int esr,
450 struct pt_regs *regs)
452 const struct fault_info *inf;
453 struct mm_struct *mm = current->mm;
454 vm_fault_t fault, major = 0;
455 unsigned long vm_flags = VM_ACCESS_FLAGS;
456 unsigned int mm_flags = FAULT_FLAG_DEFAULT;
458 if (kprobe_page_fault(regs, esr))
462 * If we're in an interrupt or have no user context, we must not take
465 if (faulthandler_disabled() || !mm)
469 mm_flags |= FAULT_FLAG_USER;
471 if (is_el0_instruction_abort(esr)) {
473 mm_flags |= FAULT_FLAG_INSTRUCTION;
474 } else if (is_write_abort(esr)) {
476 mm_flags |= FAULT_FLAG_WRITE;
479 if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) {
480 /* regs->orig_addr_limit may be 0 if we entered from EL0 */
481 if (regs->orig_addr_limit == KERNEL_DS)
482 die_kernel_fault("access to user memory with fs=KERNEL_DS",
485 if (is_el1_instruction_abort(esr))
486 die_kernel_fault("execution of user memory",
489 if (!search_exception_tables(regs->pc))
490 die_kernel_fault("access to user memory outside uaccess routines",
494 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
497 * As per x86, we may deadlock here. However, since the kernel only
498 * validly references user space from well defined areas of the code,
499 * we can bug out early if this is from code which shouldn't.
501 if (!down_read_trylock(&mm->mmap_sem)) {
502 if (!user_mode(regs) && !search_exception_tables(regs->pc))
505 down_read(&mm->mmap_sem);
508 * The above down_read_trylock() might have succeeded in which
509 * case, we'll have missed the might_sleep() from down_read().
512 #ifdef CONFIG_DEBUG_VM
513 if (!user_mode(regs) && !search_exception_tables(regs->pc)) {
514 up_read(&mm->mmap_sem);
520 fault = __do_page_fault(mm, addr, mm_flags, vm_flags);
521 major |= fault & VM_FAULT_MAJOR;
523 /* Quick path to respond to signals */
524 if (fault_signal_pending(fault, regs)) {
525 if (!user_mode(regs))
530 if (fault & VM_FAULT_RETRY) {
531 if (mm_flags & FAULT_FLAG_ALLOW_RETRY) {
532 mm_flags |= FAULT_FLAG_TRIED;
536 up_read(&mm->mmap_sem);
539 * Handle the "normal" (no error) case first.
541 if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP |
542 VM_FAULT_BADACCESS)))) {
544 * Major/minor page fault accounting is only done
545 * once. If we go through a retry, it is extremely
546 * likely that the page will be found in page cache at
551 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs,
555 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs,
563 * If we are in kernel mode at this point, we have no context to
564 * handle this fault with.
566 if (!user_mode(regs))
569 if (fault & VM_FAULT_OOM) {
571 * We ran out of memory, call the OOM killer, and return to
572 * userspace (which will retry the fault, or kill us if we got
575 pagefault_out_of_memory();
579 inf = esr_to_fault_info(esr);
580 set_thread_esr(addr, esr);
581 if (fault & VM_FAULT_SIGBUS) {
583 * We had some memory, but were unable to successfully fix up
586 arm64_force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)addr,
588 } else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) {
592 if (fault & VM_FAULT_HWPOISON_LARGE)
593 lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault));
595 arm64_force_sig_mceerr(BUS_MCEERR_AR, (void __user *)addr, lsb,
599 * Something tried to access memory that isn't in our memory
602 arm64_force_sig_fault(SIGSEGV,
603 fault == VM_FAULT_BADACCESS ? SEGV_ACCERR : SEGV_MAPERR,
611 __do_kernel_fault(addr, esr, regs);
615 static int __kprobes do_translation_fault(unsigned long addr,
617 struct pt_regs *regs)
619 if (is_ttbr0_addr(addr))
620 return do_page_fault(addr, esr, regs);
622 do_bad_area(addr, esr, regs);
626 static int do_alignment_fault(unsigned long addr, unsigned int esr,
627 struct pt_regs *regs)
629 do_bad_area(addr, esr, regs);
633 static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs)
635 return 1; /* "fault" */
638 static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs)
640 const struct fault_info *inf;
643 inf = esr_to_fault_info(esr);
645 if (user_mode(regs) && apei_claim_sea(regs) == 0) {
647 * APEI claimed this as a firmware-first notification.
648 * Some processing deferred to task_work before ret_to_user().
653 if (esr & ESR_ELx_FnV)
656 siaddr = (void __user *)addr;
657 arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr);
662 static const struct fault_info fault_info[] = {
663 { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" },
664 { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" },
665 { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" },
666 { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" },
667 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" },
668 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" },
669 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" },
670 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
671 { do_bad, SIGKILL, SI_KERNEL, "unknown 8" },
672 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" },
673 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" },
674 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" },
675 { do_bad, SIGKILL, SI_KERNEL, "unknown 12" },
676 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" },
677 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" },
678 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" },
679 { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" },
680 { do_bad, SIGKILL, SI_KERNEL, "unknown 17" },
681 { do_bad, SIGKILL, SI_KERNEL, "unknown 18" },
682 { do_bad, SIGKILL, SI_KERNEL, "unknown 19" },
683 { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" },
684 { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" },
685 { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" },
686 { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" },
687 { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented
688 { do_bad, SIGKILL, SI_KERNEL, "unknown 25" },
689 { do_bad, SIGKILL, SI_KERNEL, "unknown 26" },
690 { do_bad, SIGKILL, SI_KERNEL, "unknown 27" },
691 { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
692 { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
693 { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
694 { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
695 { do_bad, SIGKILL, SI_KERNEL, "unknown 32" },
696 { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" },
697 { do_bad, SIGKILL, SI_KERNEL, "unknown 34" },
698 { do_bad, SIGKILL, SI_KERNEL, "unknown 35" },
699 { do_bad, SIGKILL, SI_KERNEL, "unknown 36" },
700 { do_bad, SIGKILL, SI_KERNEL, "unknown 37" },
701 { do_bad, SIGKILL, SI_KERNEL, "unknown 38" },
702 { do_bad, SIGKILL, SI_KERNEL, "unknown 39" },
703 { do_bad, SIGKILL, SI_KERNEL, "unknown 40" },
704 { do_bad, SIGKILL, SI_KERNEL, "unknown 41" },
705 { do_bad, SIGKILL, SI_KERNEL, "unknown 42" },
706 { do_bad, SIGKILL, SI_KERNEL, "unknown 43" },
707 { do_bad, SIGKILL, SI_KERNEL, "unknown 44" },
708 { do_bad, SIGKILL, SI_KERNEL, "unknown 45" },
709 { do_bad, SIGKILL, SI_KERNEL, "unknown 46" },
710 { do_bad, SIGKILL, SI_KERNEL, "unknown 47" },
711 { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" },
712 { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" },
713 { do_bad, SIGKILL, SI_KERNEL, "unknown 50" },
714 { do_bad, SIGKILL, SI_KERNEL, "unknown 51" },
715 { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" },
716 { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" },
717 { do_bad, SIGKILL, SI_KERNEL, "unknown 54" },
718 { do_bad, SIGKILL, SI_KERNEL, "unknown 55" },
719 { do_bad, SIGKILL, SI_KERNEL, "unknown 56" },
720 { do_bad, SIGKILL, SI_KERNEL, "unknown 57" },
721 { do_bad, SIGKILL, SI_KERNEL, "unknown 58" },
722 { do_bad, SIGKILL, SI_KERNEL, "unknown 59" },
723 { do_bad, SIGKILL, SI_KERNEL, "unknown 60" },
724 { do_bad, SIGKILL, SI_KERNEL, "section domain fault" },
725 { do_bad, SIGKILL, SI_KERNEL, "page domain fault" },
726 { do_bad, SIGKILL, SI_KERNEL, "unknown 63" },
729 void do_mem_abort(unsigned long addr, unsigned int esr, struct pt_regs *regs)
731 const struct fault_info *inf = esr_to_fault_info(esr);
733 if (!inf->fn(addr, esr, regs))
736 if (!user_mode(regs)) {
737 pr_alert("Unhandled fault at 0x%016lx\n", addr);
738 mem_abort_decode(esr);
742 arm64_notify_die(inf->name, regs,
743 inf->sig, inf->code, (void __user *)addr, esr);
745 NOKPROBE_SYMBOL(do_mem_abort);
747 void do_el0_irq_bp_hardening(void)
749 /* PC has already been checked in entry.S */
750 arm64_apply_bp_hardening();
752 NOKPROBE_SYMBOL(do_el0_irq_bp_hardening);
754 void do_sp_pc_abort(unsigned long addr, unsigned int esr, struct pt_regs *regs)
756 arm64_notify_die("SP/PC alignment exception", regs,
757 SIGBUS, BUS_ADRALN, (void __user *)addr, esr);
759 NOKPROBE_SYMBOL(do_sp_pc_abort);
761 int __init early_brk64(unsigned long addr, unsigned int esr,
762 struct pt_regs *regs);
765 * __refdata because early_brk64 is __init, but the reference to it is
766 * clobbered at arch_initcall time.
767 * See traps.c and debug-monitors.c:debug_traps_init().
769 static struct fault_info __refdata debug_fault_info[] = {
770 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware breakpoint" },
771 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware single-step" },
772 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware watchpoint" },
773 { do_bad, SIGKILL, SI_KERNEL, "unknown 3" },
774 { do_bad, SIGTRAP, TRAP_BRKPT, "aarch32 BKPT" },
775 { do_bad, SIGKILL, SI_KERNEL, "aarch32 vector catch" },
776 { early_brk64, SIGTRAP, TRAP_BRKPT, "aarch64 BRK" },
777 { do_bad, SIGKILL, SI_KERNEL, "unknown 7" },
780 void __init hook_debug_fault_code(int nr,
781 int (*fn)(unsigned long, unsigned int, struct pt_regs *),
782 int sig, int code, const char *name)
784 BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info));
786 debug_fault_info[nr].fn = fn;
787 debug_fault_info[nr].sig = sig;
788 debug_fault_info[nr].code = code;
789 debug_fault_info[nr].name = name;
793 * In debug exception context, we explicitly disable preemption despite
794 * having interrupts disabled.
795 * This serves two purposes: it makes it much less likely that we would
796 * accidentally schedule in exception context and it will force a warning
797 * if we somehow manage to schedule by accident.
799 static void debug_exception_enter(struct pt_regs *regs)
802 * Tell lockdep we disabled irqs in entry.S. Do nothing if they were
803 * already disabled to preserve the last enabled/disabled addresses.
805 if (interrupts_enabled(regs))
806 trace_hardirqs_off();
808 if (user_mode(regs)) {
809 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
812 * We might have interrupted pretty much anything. In
813 * fact, if we're a debug exception, we can even interrupt
814 * NMI processing. We don't want this code makes in_nmi()
815 * to return true, but we need to notify RCU.
822 /* This code is a bit fragile. Test it. */
823 RCU_LOCKDEP_WARN(!rcu_is_watching(), "exception_enter didn't work");
825 NOKPROBE_SYMBOL(debug_exception_enter);
827 static void debug_exception_exit(struct pt_regs *regs)
829 preempt_enable_no_resched();
831 if (!user_mode(regs))
834 if (interrupts_enabled(regs))
837 NOKPROBE_SYMBOL(debug_exception_exit);
839 #ifdef CONFIG_ARM64_ERRATUM_1463225
840 DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
842 static int cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
847 if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa))
851 * We've taken a dummy step exception from the kernel to ensure
852 * that interrupts are re-enabled on the syscall path. Return back
853 * to cortex_a76_erratum_1463225_svc_handler() with debug exceptions
854 * masked so that we can safely restore the mdscr and get on with
855 * handling the syscall.
857 regs->pstate |= PSR_D_BIT;
861 static int cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
865 #endif /* CONFIG_ARM64_ERRATUM_1463225 */
866 NOKPROBE_SYMBOL(cortex_a76_erratum_1463225_debug_handler);
868 void do_debug_exception(unsigned long addr_if_watchpoint, unsigned int esr,
869 struct pt_regs *regs)
871 const struct fault_info *inf = esr_to_debug_fault_info(esr);
872 unsigned long pc = instruction_pointer(regs);
874 if (cortex_a76_erratum_1463225_debug_handler(regs))
877 debug_exception_enter(regs);
879 if (user_mode(regs) && !is_ttbr0_addr(pc))
880 arm64_apply_bp_hardening();
882 if (inf->fn(addr_if_watchpoint, esr, regs)) {
883 arm64_notify_die(inf->name, regs,
884 inf->sig, inf->code, (void __user *)pc, esr);
887 debug_exception_exit(regs);
889 NOKPROBE_SYMBOL(do_debug_exception);