1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/mm/fault.c
5 * Copyright (C) 1995 Linus Torvalds
6 * Copyright (C) 1995-2004 Russell King
7 * Copyright (C) 2012 ARM Ltd.
10 #include <linux/acpi.h>
11 #include <linux/bitfield.h>
12 #include <linux/extable.h>
13 #include <linux/signal.h>
15 #include <linux/hardirq.h>
16 #include <linux/init.h>
17 #include <linux/kprobes.h>
18 #include <linux/uaccess.h>
19 #include <linux/page-flags.h>
20 #include <linux/sched/signal.h>
21 #include <linux/sched/debug.h>
22 #include <linux/highmem.h>
23 #include <linux/perf_event.h>
24 #include <linux/preempt.h>
25 #include <linux/hugetlb.h>
29 #include <asm/cmpxchg.h>
30 #include <asm/cpufeature.h>
31 #include <asm/exception.h>
32 #include <asm/daifflags.h>
33 #include <asm/debug-monitors.h>
35 #include <asm/kprobes.h>
36 #include <asm/processor.h>
37 #include <asm/sysreg.h>
38 #include <asm/system_misc.h>
39 #include <asm/tlbflush.h>
40 #include <asm/traps.h>
43 int (*fn)(unsigned long addr, unsigned int esr,
44 struct pt_regs *regs);
50 static const struct fault_info fault_info[];
51 static struct fault_info debug_fault_info[];
53 static inline const struct fault_info *esr_to_fault_info(unsigned int esr)
55 return fault_info + (esr & ESR_ELx_FSC);
58 static inline const struct fault_info *esr_to_debug_fault_info(unsigned int esr)
60 return debug_fault_info + DBG_ESR_EVT(esr);
63 static void data_abort_decode(unsigned int esr)
65 pr_alert("Data abort info:\n");
67 if (esr & ESR_ELx_ISV) {
68 pr_alert(" Access size = %u byte(s)\n",
69 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT));
70 pr_alert(" SSE = %lu, SRT = %lu\n",
71 (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT,
72 (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT);
73 pr_alert(" SF = %lu, AR = %lu\n",
74 (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT,
75 (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT);
77 pr_alert(" ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK);
80 pr_alert(" CM = %lu, WnR = %lu\n",
81 (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT,
82 (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT);
85 static void mem_abort_decode(unsigned int esr)
87 pr_alert("Mem abort info:\n");
89 pr_alert(" ESR = 0x%08x\n", esr);
90 pr_alert(" EC = 0x%02lx: %s, IL = %u bits\n",
91 ESR_ELx_EC(esr), esr_get_class_string(esr),
92 (esr & ESR_ELx_IL) ? 32 : 16);
93 pr_alert(" SET = %lu, FnV = %lu\n",
94 (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT,
95 (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT);
96 pr_alert(" EA = %lu, S1PTW = %lu\n",
97 (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT,
98 (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT);
100 if (esr_is_data_abort(esr))
101 data_abort_decode(esr);
104 static inline unsigned long mm_to_pgd_phys(struct mm_struct *mm)
106 /* Either init_pg_dir or swapper_pg_dir */
108 return __pa_symbol(mm->pgd);
110 return (unsigned long)virt_to_phys(mm->pgd);
114 * Dump out the page tables associated with 'addr' in the currently active mm.
116 static void show_pte(unsigned long addr)
118 struct mm_struct *mm;
122 if (is_ttbr0_addr(addr)) {
124 mm = current->active_mm;
125 if (mm == &init_mm) {
126 pr_alert("[%016lx] user address but active_mm is swapper\n",
130 } else if (is_ttbr1_addr(addr)) {
134 pr_alert("[%016lx] address between user and kernel address ranges\n",
139 pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n",
140 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K,
141 vabits_actual, mm_to_pgd_phys(mm));
142 pgdp = pgd_offset(mm, addr);
143 pgd = READ_ONCE(*pgdp);
144 pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd));
152 if (pgd_none(pgd) || pgd_bad(pgd))
155 p4dp = p4d_offset(pgdp, addr);
156 p4d = READ_ONCE(*p4dp);
157 pr_cont(", p4d=%016llx", p4d_val(p4d));
158 if (p4d_none(p4d) || p4d_bad(p4d))
161 pudp = pud_offset(p4dp, addr);
162 pud = READ_ONCE(*pudp);
163 pr_cont(", pud=%016llx", pud_val(pud));
164 if (pud_none(pud) || pud_bad(pud))
167 pmdp = pmd_offset(pudp, addr);
168 pmd = READ_ONCE(*pmdp);
169 pr_cont(", pmd=%016llx", pmd_val(pmd));
170 if (pmd_none(pmd) || pmd_bad(pmd))
173 ptep = pte_offset_map(pmdp, addr);
174 pte = READ_ONCE(*ptep);
175 pr_cont(", pte=%016llx", pte_val(pte));
183 * This function sets the access flags (dirty, accessed), as well as write
184 * permission, and only to a more permissive setting.
186 * It needs to cope with hardware update of the accessed/dirty state by other
187 * agents in the system and can safely skip the __sync_icache_dcache() call as,
188 * like set_pte_at(), the PTE is never changed from no-exec to exec here.
190 * Returns whether or not the PTE actually changed.
192 int ptep_set_access_flags(struct vm_area_struct *vma,
193 unsigned long address, pte_t *ptep,
194 pte_t entry, int dirty)
196 pteval_t old_pteval, pteval;
197 pte_t pte = READ_ONCE(*ptep);
199 if (pte_same(pte, entry))
202 /* only preserve the access flags and write permission */
203 pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY;
206 * Setting the flags must be done atomically to avoid racing with the
207 * hardware update of the access/dirty state. The PTE_RDONLY bit must
208 * be set to the most permissive (lowest value) of *ptep and entry
209 * (calculated as: a & b == ~(~a | ~b)).
211 pte_val(entry) ^= PTE_RDONLY;
212 pteval = pte_val(pte);
215 pteval ^= PTE_RDONLY;
216 pteval |= pte_val(entry);
217 pteval ^= PTE_RDONLY;
218 pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval);
219 } while (pteval != old_pteval);
221 flush_tlb_fix_spurious_fault(vma, address);
225 static bool is_el1_instruction_abort(unsigned int esr)
227 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR;
230 static inline bool is_el1_permission_fault(unsigned long addr, unsigned int esr,
231 struct pt_regs *regs)
233 unsigned int ec = ESR_ELx_EC(esr);
234 unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE;
236 if (ec != ESR_ELx_EC_DABT_CUR && ec != ESR_ELx_EC_IABT_CUR)
239 if (fsc_type == ESR_ELx_FSC_PERM)
242 if (is_ttbr0_addr(addr) && system_uses_ttbr0_pan())
243 return fsc_type == ESR_ELx_FSC_FAULT &&
244 (regs->pstate & PSR_PAN_BIT);
249 static bool __kprobes is_spurious_el1_translation_fault(unsigned long addr,
251 struct pt_regs *regs)
256 if (ESR_ELx_EC(esr) != ESR_ELx_EC_DABT_CUR ||
257 (esr & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT)
260 local_irq_save(flags);
261 asm volatile("at s1e1r, %0" :: "r" (addr));
263 par = read_sysreg(par_el1);
264 local_irq_restore(flags);
267 * If we now have a valid translation, treat the translation fault as
270 if (!(par & SYS_PAR_EL1_F))
274 * If we got a different type of fault from the AT instruction,
275 * treat the translation fault as spurious.
277 dfsc = FIELD_GET(SYS_PAR_EL1_FST, par);
278 return (dfsc & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT;
281 static void die_kernel_fault(const char *msg, unsigned long addr,
282 unsigned int esr, struct pt_regs *regs)
286 pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg,
289 mem_abort_decode(esr);
292 die("Oops", regs, esr);
297 static void __do_kernel_fault(unsigned long addr, unsigned int esr,
298 struct pt_regs *regs)
303 * Are we prepared to handle this kernel fault?
304 * We are almost certainly not prepared to handle instruction faults.
306 if (!is_el1_instruction_abort(esr) && fixup_exception(regs))
309 if (WARN_RATELIMIT(is_spurious_el1_translation_fault(addr, esr, regs),
310 "Ignoring spurious kernel translation fault at virtual address %016lx\n", addr))
313 if (is_el1_permission_fault(addr, esr, regs)) {
314 if (esr & ESR_ELx_WNR)
315 msg = "write to read-only memory";
316 else if (is_el1_instruction_abort(esr))
317 msg = "execute from non-executable memory";
319 msg = "read from unreadable memory";
320 } else if (addr < PAGE_SIZE) {
321 msg = "NULL pointer dereference";
323 msg = "paging request";
326 die_kernel_fault(msg, addr, esr, regs);
329 static void set_thread_esr(unsigned long address, unsigned int esr)
331 current->thread.fault_address = address;
334 * If the faulting address is in the kernel, we must sanitize the ESR.
335 * From userspace's point of view, kernel-only mappings don't exist
336 * at all, so we report them as level 0 translation faults.
337 * (This is not quite the way that "no mapping there at all" behaves:
338 * an alignment fault not caused by the memory type would take
339 * precedence over translation fault for a real access to empty
340 * space. Unfortunately we can't easily distinguish "alignment fault
341 * not caused by memory type" from "alignment fault caused by memory
342 * type", so we ignore this wrinkle and just return the translation
345 if (!is_ttbr0_addr(current->thread.fault_address)) {
346 switch (ESR_ELx_EC(esr)) {
347 case ESR_ELx_EC_DABT_LOW:
349 * These bits provide only information about the
350 * faulting instruction, which userspace knows already.
351 * We explicitly clear bits which are architecturally
352 * RES0 in case they are given meanings in future.
353 * We always report the ESR as if the fault was taken
354 * to EL1 and so ISV and the bits in ISS[23:14] are
355 * clear. (In fact it always will be a fault to EL1.)
357 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL |
358 ESR_ELx_CM | ESR_ELx_WNR;
359 esr |= ESR_ELx_FSC_FAULT;
361 case ESR_ELx_EC_IABT_LOW:
363 * Claim a level 0 translation fault.
364 * All other bits are architecturally RES0 for faults
365 * reported with that DFSC value, so we clear them.
367 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL;
368 esr |= ESR_ELx_FSC_FAULT;
372 * This should never happen (entry.S only brings us
373 * into this code for insn and data aborts from a lower
374 * exception level). Fail safe by not providing an ESR
375 * context record at all.
377 WARN(1, "ESR 0x%x is not DABT or IABT from EL0\n", esr);
383 current->thread.fault_code = esr;
386 static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs)
389 * If we are in kernel mode at this point, we have no context to
390 * handle this fault with.
392 if (user_mode(regs)) {
393 const struct fault_info *inf = esr_to_fault_info(esr);
395 set_thread_esr(addr, esr);
396 arm64_force_sig_fault(inf->sig, inf->code, (void __user *)addr,
399 __do_kernel_fault(addr, esr, regs);
403 #define VM_FAULT_BADMAP 0x010000
404 #define VM_FAULT_BADACCESS 0x020000
406 static vm_fault_t __do_page_fault(struct mm_struct *mm, unsigned long addr,
407 unsigned int mm_flags, unsigned long vm_flags)
409 struct vm_area_struct *vma = find_vma(mm, addr);
412 return VM_FAULT_BADMAP;
415 * Ok, we have a good vm_area for this memory access, so we can handle
418 if (unlikely(vma->vm_start > addr)) {
419 if (!(vma->vm_flags & VM_GROWSDOWN))
420 return VM_FAULT_BADMAP;
421 if (expand_stack(vma, addr))
422 return VM_FAULT_BADMAP;
426 * Check that the permissions on the VMA allow for the fault which
429 if (!(vma->vm_flags & vm_flags))
430 return VM_FAULT_BADACCESS;
431 return handle_mm_fault(vma, addr & PAGE_MASK, mm_flags);
434 static bool is_el0_instruction_abort(unsigned int esr)
436 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW;
440 * Note: not valid for EL1 DC IVAC, but we never use that such that it
441 * should fault. EL0 cannot issue DC IVAC (undef).
443 static bool is_write_abort(unsigned int esr)
445 return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM);
448 static int __kprobes do_page_fault(unsigned long addr, unsigned int esr,
449 struct pt_regs *regs)
451 const struct fault_info *inf;
452 struct mm_struct *mm = current->mm;
453 vm_fault_t fault, major = 0;
454 unsigned long vm_flags = VM_ACCESS_FLAGS;
455 unsigned int mm_flags = FAULT_FLAG_DEFAULT;
457 if (kprobe_page_fault(regs, esr))
461 * If we're in an interrupt or have no user context, we must not take
464 if (faulthandler_disabled() || !mm)
468 mm_flags |= FAULT_FLAG_USER;
470 if (is_el0_instruction_abort(esr)) {
472 mm_flags |= FAULT_FLAG_INSTRUCTION;
473 } else if (is_write_abort(esr)) {
475 mm_flags |= FAULT_FLAG_WRITE;
478 if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) {
479 /* regs->orig_addr_limit may be 0 if we entered from EL0 */
480 if (regs->orig_addr_limit == KERNEL_DS)
481 die_kernel_fault("access to user memory with fs=KERNEL_DS",
484 if (is_el1_instruction_abort(esr))
485 die_kernel_fault("execution of user memory",
488 if (!search_exception_tables(regs->pc))
489 die_kernel_fault("access to user memory outside uaccess routines",
493 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
496 * As per x86, we may deadlock here. However, since the kernel only
497 * validly references user space from well defined areas of the code,
498 * we can bug out early if this is from code which shouldn't.
500 if (!mmap_read_trylock(mm)) {
501 if (!user_mode(regs) && !search_exception_tables(regs->pc))
507 * The above down_read_trylock() might have succeeded in which
508 * case, we'll have missed the might_sleep() from down_read().
511 #ifdef CONFIG_DEBUG_VM
512 if (!user_mode(regs) && !search_exception_tables(regs->pc)) {
513 mmap_read_unlock(mm);
519 fault = __do_page_fault(mm, addr, mm_flags, vm_flags);
520 major |= fault & VM_FAULT_MAJOR;
522 /* Quick path to respond to signals */
523 if (fault_signal_pending(fault, regs)) {
524 if (!user_mode(regs))
529 if (fault & VM_FAULT_RETRY) {
530 if (mm_flags & FAULT_FLAG_ALLOW_RETRY) {
531 mm_flags |= FAULT_FLAG_TRIED;
535 mmap_read_unlock(mm);
538 * Handle the "normal" (no error) case first.
540 if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP |
541 VM_FAULT_BADACCESS)))) {
543 * Major/minor page fault accounting is only done
544 * once. If we go through a retry, it is extremely
545 * likely that the page will be found in page cache at
550 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs,
554 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs,
562 * If we are in kernel mode at this point, we have no context to
563 * handle this fault with.
565 if (!user_mode(regs))
568 if (fault & VM_FAULT_OOM) {
570 * We ran out of memory, call the OOM killer, and return to
571 * userspace (which will retry the fault, or kill us if we got
574 pagefault_out_of_memory();
578 inf = esr_to_fault_info(esr);
579 set_thread_esr(addr, esr);
580 if (fault & VM_FAULT_SIGBUS) {
582 * We had some memory, but were unable to successfully fix up
585 arm64_force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)addr,
587 } else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) {
591 if (fault & VM_FAULT_HWPOISON_LARGE)
592 lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault));
594 arm64_force_sig_mceerr(BUS_MCEERR_AR, (void __user *)addr, lsb,
598 * Something tried to access memory that isn't in our memory
601 arm64_force_sig_fault(SIGSEGV,
602 fault == VM_FAULT_BADACCESS ? SEGV_ACCERR : SEGV_MAPERR,
610 __do_kernel_fault(addr, esr, regs);
614 static int __kprobes do_translation_fault(unsigned long addr,
616 struct pt_regs *regs)
618 if (is_ttbr0_addr(addr))
619 return do_page_fault(addr, esr, regs);
621 do_bad_area(addr, esr, regs);
625 static int do_alignment_fault(unsigned long addr, unsigned int esr,
626 struct pt_regs *regs)
628 do_bad_area(addr, esr, regs);
632 static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs)
634 return 1; /* "fault" */
637 static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs)
639 const struct fault_info *inf;
642 inf = esr_to_fault_info(esr);
644 if (user_mode(regs) && apei_claim_sea(regs) == 0) {
646 * APEI claimed this as a firmware-first notification.
647 * Some processing deferred to task_work before ret_to_user().
652 if (esr & ESR_ELx_FnV)
655 siaddr = (void __user *)addr;
656 arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr);
661 static const struct fault_info fault_info[] = {
662 { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" },
663 { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" },
664 { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" },
665 { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" },
666 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" },
667 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" },
668 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" },
669 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
670 { do_bad, SIGKILL, SI_KERNEL, "unknown 8" },
671 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" },
672 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" },
673 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" },
674 { do_bad, SIGKILL, SI_KERNEL, "unknown 12" },
675 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" },
676 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" },
677 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" },
678 { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" },
679 { do_bad, SIGKILL, SI_KERNEL, "unknown 17" },
680 { do_bad, SIGKILL, SI_KERNEL, "unknown 18" },
681 { do_bad, SIGKILL, SI_KERNEL, "unknown 19" },
682 { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" },
683 { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" },
684 { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" },
685 { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" },
686 { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented
687 { do_bad, SIGKILL, SI_KERNEL, "unknown 25" },
688 { do_bad, SIGKILL, SI_KERNEL, "unknown 26" },
689 { do_bad, SIGKILL, SI_KERNEL, "unknown 27" },
690 { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
691 { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
692 { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
693 { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
694 { do_bad, SIGKILL, SI_KERNEL, "unknown 32" },
695 { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" },
696 { do_bad, SIGKILL, SI_KERNEL, "unknown 34" },
697 { do_bad, SIGKILL, SI_KERNEL, "unknown 35" },
698 { do_bad, SIGKILL, SI_KERNEL, "unknown 36" },
699 { do_bad, SIGKILL, SI_KERNEL, "unknown 37" },
700 { do_bad, SIGKILL, SI_KERNEL, "unknown 38" },
701 { do_bad, SIGKILL, SI_KERNEL, "unknown 39" },
702 { do_bad, SIGKILL, SI_KERNEL, "unknown 40" },
703 { do_bad, SIGKILL, SI_KERNEL, "unknown 41" },
704 { do_bad, SIGKILL, SI_KERNEL, "unknown 42" },
705 { do_bad, SIGKILL, SI_KERNEL, "unknown 43" },
706 { do_bad, SIGKILL, SI_KERNEL, "unknown 44" },
707 { do_bad, SIGKILL, SI_KERNEL, "unknown 45" },
708 { do_bad, SIGKILL, SI_KERNEL, "unknown 46" },
709 { do_bad, SIGKILL, SI_KERNEL, "unknown 47" },
710 { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" },
711 { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" },
712 { do_bad, SIGKILL, SI_KERNEL, "unknown 50" },
713 { do_bad, SIGKILL, SI_KERNEL, "unknown 51" },
714 { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" },
715 { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" },
716 { do_bad, SIGKILL, SI_KERNEL, "unknown 54" },
717 { do_bad, SIGKILL, SI_KERNEL, "unknown 55" },
718 { do_bad, SIGKILL, SI_KERNEL, "unknown 56" },
719 { do_bad, SIGKILL, SI_KERNEL, "unknown 57" },
720 { do_bad, SIGKILL, SI_KERNEL, "unknown 58" },
721 { do_bad, SIGKILL, SI_KERNEL, "unknown 59" },
722 { do_bad, SIGKILL, SI_KERNEL, "unknown 60" },
723 { do_bad, SIGKILL, SI_KERNEL, "section domain fault" },
724 { do_bad, SIGKILL, SI_KERNEL, "page domain fault" },
725 { do_bad, SIGKILL, SI_KERNEL, "unknown 63" },
728 void do_mem_abort(unsigned long addr, unsigned int esr, struct pt_regs *regs)
730 const struct fault_info *inf = esr_to_fault_info(esr);
732 if (!inf->fn(addr, esr, regs))
735 if (!user_mode(regs)) {
736 pr_alert("Unhandled fault at 0x%016lx\n", addr);
737 mem_abort_decode(esr);
741 arm64_notify_die(inf->name, regs,
742 inf->sig, inf->code, (void __user *)addr, esr);
744 NOKPROBE_SYMBOL(do_mem_abort);
746 void do_el0_irq_bp_hardening(void)
748 /* PC has already been checked in entry.S */
749 arm64_apply_bp_hardening();
751 NOKPROBE_SYMBOL(do_el0_irq_bp_hardening);
753 void do_sp_pc_abort(unsigned long addr, unsigned int esr, struct pt_regs *regs)
755 arm64_notify_die("SP/PC alignment exception", regs,
756 SIGBUS, BUS_ADRALN, (void __user *)addr, esr);
758 NOKPROBE_SYMBOL(do_sp_pc_abort);
760 int __init early_brk64(unsigned long addr, unsigned int esr,
761 struct pt_regs *regs);
764 * __refdata because early_brk64 is __init, but the reference to it is
765 * clobbered at arch_initcall time.
766 * See traps.c and debug-monitors.c:debug_traps_init().
768 static struct fault_info __refdata debug_fault_info[] = {
769 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware breakpoint" },
770 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware single-step" },
771 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware watchpoint" },
772 { do_bad, SIGKILL, SI_KERNEL, "unknown 3" },
773 { do_bad, SIGTRAP, TRAP_BRKPT, "aarch32 BKPT" },
774 { do_bad, SIGKILL, SI_KERNEL, "aarch32 vector catch" },
775 { early_brk64, SIGTRAP, TRAP_BRKPT, "aarch64 BRK" },
776 { do_bad, SIGKILL, SI_KERNEL, "unknown 7" },
779 void __init hook_debug_fault_code(int nr,
780 int (*fn)(unsigned long, unsigned int, struct pt_regs *),
781 int sig, int code, const char *name)
783 BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info));
785 debug_fault_info[nr].fn = fn;
786 debug_fault_info[nr].sig = sig;
787 debug_fault_info[nr].code = code;
788 debug_fault_info[nr].name = name;
792 * In debug exception context, we explicitly disable preemption despite
793 * having interrupts disabled.
794 * This serves two purposes: it makes it much less likely that we would
795 * accidentally schedule in exception context and it will force a warning
796 * if we somehow manage to schedule by accident.
798 static void debug_exception_enter(struct pt_regs *regs)
801 * Tell lockdep we disabled irqs in entry.S. Do nothing if they were
802 * already disabled to preserve the last enabled/disabled addresses.
804 if (interrupts_enabled(regs))
805 trace_hardirqs_off();
807 if (user_mode(regs)) {
808 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
811 * We might have interrupted pretty much anything. In
812 * fact, if we're a debug exception, we can even interrupt
813 * NMI processing. We don't want this code makes in_nmi()
814 * to return true, but we need to notify RCU.
821 /* This code is a bit fragile. Test it. */
822 RCU_LOCKDEP_WARN(!rcu_is_watching(), "exception_enter didn't work");
824 NOKPROBE_SYMBOL(debug_exception_enter);
826 static void debug_exception_exit(struct pt_regs *regs)
828 preempt_enable_no_resched();
830 if (!user_mode(regs))
833 if (interrupts_enabled(regs))
836 NOKPROBE_SYMBOL(debug_exception_exit);
838 #ifdef CONFIG_ARM64_ERRATUM_1463225
839 DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
841 static int cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
846 if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa))
850 * We've taken a dummy step exception from the kernel to ensure
851 * that interrupts are re-enabled on the syscall path. Return back
852 * to cortex_a76_erratum_1463225_svc_handler() with debug exceptions
853 * masked so that we can safely restore the mdscr and get on with
854 * handling the syscall.
856 regs->pstate |= PSR_D_BIT;
860 static int cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
864 #endif /* CONFIG_ARM64_ERRATUM_1463225 */
865 NOKPROBE_SYMBOL(cortex_a76_erratum_1463225_debug_handler);
867 void do_debug_exception(unsigned long addr_if_watchpoint, unsigned int esr,
868 struct pt_regs *regs)
870 const struct fault_info *inf = esr_to_debug_fault_info(esr);
871 unsigned long pc = instruction_pointer(regs);
873 if (cortex_a76_erratum_1463225_debug_handler(regs))
876 debug_exception_enter(regs);
878 if (user_mode(regs) && !is_ttbr0_addr(pc))
879 arm64_apply_bp_hardening();
881 if (inf->fn(addr_if_watchpoint, esr, regs)) {
882 arm64_notify_die(inf->name, regs,
883 inf->sig, inf->code, (void __user *)pc, esr);
886 debug_exception_exit(regs);
888 NOKPROBE_SYMBOL(do_debug_exception);