1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
12 #include <linux/bitfield.h>
13 #include <linux/bsearch.h>
14 #include <linux/kvm_host.h>
16 #include <linux/printk.h>
17 #include <linux/uaccess.h>
19 #include <asm/cacheflush.h>
20 #include <asm/cputype.h>
21 #include <asm/debug-monitors.h>
23 #include <asm/kvm_arm.h>
24 #include <asm/kvm_emulate.h>
25 #include <asm/kvm_hyp.h>
26 #include <asm/kvm_mmu.h>
27 #include <asm/perf_event.h>
28 #include <asm/sysreg.h>
30 #include <trace/events/kvm.h>
37 * For AArch32, we only take care of what is being trapped. Anything
38 * that has to do with init and userspace access has to go via the
42 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
44 static bool read_from_write_only(struct kvm_vcpu *vcpu,
45 struct sys_reg_params *params,
46 const struct sys_reg_desc *r)
48 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
49 print_sys_reg_instr(params);
50 kvm_inject_undefined(vcpu);
54 static bool write_to_read_only(struct kvm_vcpu *vcpu,
55 struct sys_reg_params *params,
56 const struct sys_reg_desc *r)
58 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
59 print_sys_reg_instr(params);
60 kvm_inject_undefined(vcpu);
64 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
66 u64 val = 0x8badf00d8badf00d;
68 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) &&
69 __vcpu_read_sys_reg_from_cpu(reg, &val))
72 return __vcpu_sys_reg(vcpu, reg);
75 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
77 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) &&
78 __vcpu_write_sys_reg_to_cpu(val, reg))
81 __vcpu_sys_reg(vcpu, reg) = val;
84 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
85 static u32 cache_levels;
87 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
90 /* Which cache CCSIDR represents depends on CSSELR value. */
91 static u32 get_ccsidr(u32 csselr)
95 /* Make sure noone else changes CSSELR during this! */
97 write_sysreg(csselr, csselr_el1);
99 ccsidr = read_sysreg(ccsidr_el1);
106 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
108 static bool access_dcsw(struct kvm_vcpu *vcpu,
109 struct sys_reg_params *p,
110 const struct sys_reg_desc *r)
113 return read_from_write_only(vcpu, p, r);
116 * Only track S/W ops if we don't have FWB. It still indicates
117 * that the guest is a bit broken (S/W operations should only
118 * be done by firmware, knowing that there is only a single
119 * CPU left in the system, and certainly not from non-secure
122 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
123 kvm_set_way_flush(vcpu);
128 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift)
130 switch (r->aarch32_map) {
132 *mask = GENMASK_ULL(31, 0);
136 *mask = GENMASK_ULL(63, 32);
140 *mask = GENMASK_ULL(63, 0);
147 * Generic accessor for VM registers. Only called as long as HCR_TVM
148 * is set. If the guest enables the MMU, we stop trapping the VM
149 * sys_regs and leave it in complete control of the caches.
151 static bool access_vm_reg(struct kvm_vcpu *vcpu,
152 struct sys_reg_params *p,
153 const struct sys_reg_desc *r)
155 bool was_enabled = vcpu_has_cache_enabled(vcpu);
156 u64 val, mask, shift;
158 BUG_ON(!p->is_write);
160 get_access_mask(r, &mask, &shift);
163 val = vcpu_read_sys_reg(vcpu, r->reg);
169 val |= (p->regval & (mask >> shift)) << shift;
170 vcpu_write_sys_reg(vcpu, val, r->reg);
172 kvm_toggle_cache(vcpu, was_enabled);
176 static bool access_actlr(struct kvm_vcpu *vcpu,
177 struct sys_reg_params *p,
178 const struct sys_reg_desc *r)
183 return ignore_write(vcpu, p);
185 get_access_mask(r, &mask, &shift);
186 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;
192 * Trap handler for the GICv3 SGI generation system register.
193 * Forward the request to the VGIC emulation.
194 * The cp15_64 code makes sure this automatically works
195 * for both AArch64 and AArch32 accesses.
197 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
198 struct sys_reg_params *p,
199 const struct sys_reg_desc *r)
204 return read_from_write_only(vcpu, p, r);
207 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
208 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
209 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
210 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
213 if (p->Op0 == 0) { /* AArch32 */
215 default: /* Keep GCC quiet */
216 case 0: /* ICC_SGI1R */
219 case 1: /* ICC_ASGI1R */
220 case 2: /* ICC_SGI0R */
224 } else { /* AArch64 */
226 default: /* Keep GCC quiet */
227 case 5: /* ICC_SGI1R_EL1 */
230 case 6: /* ICC_ASGI1R_EL1 */
231 case 7: /* ICC_SGI0R_EL1 */
237 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
242 static bool access_gic_sre(struct kvm_vcpu *vcpu,
243 struct sys_reg_params *p,
244 const struct sys_reg_desc *r)
247 return ignore_write(vcpu, p);
249 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
253 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
254 struct sys_reg_params *p,
255 const struct sys_reg_desc *r)
258 return ignore_write(vcpu, p);
260 return read_zero(vcpu, p);
264 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
265 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
266 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
267 * treat it separately.
269 static bool trap_loregion(struct kvm_vcpu *vcpu,
270 struct sys_reg_params *p,
271 const struct sys_reg_desc *r)
273 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
274 u32 sr = reg_to_encoding(r);
276 if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) {
277 kvm_inject_undefined(vcpu);
281 if (p->is_write && sr == SYS_LORID_EL1)
282 return write_to_read_only(vcpu, p, r);
284 return trap_raz_wi(vcpu, p, r);
287 static bool trap_oslar_el1(struct kvm_vcpu *vcpu,
288 struct sys_reg_params *p,
289 const struct sys_reg_desc *r)
294 return read_from_write_only(vcpu, p, r);
296 /* Forward the OSLK bit to OSLSR */
297 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~SYS_OSLSR_OSLK;
298 if (p->regval & SYS_OSLAR_OSLK)
299 oslsr |= SYS_OSLSR_OSLK;
301 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr;
305 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
306 struct sys_reg_params *p,
307 const struct sys_reg_desc *r)
310 return write_to_read_only(vcpu, p, r);
312 p->regval = __vcpu_sys_reg(vcpu, r->reg);
316 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
320 * The only modifiable bit is the OSLK bit. Refuse the write if
321 * userspace attempts to change any other bit in the register.
323 if ((val ^ rd->val) & ~SYS_OSLSR_OSLK)
326 __vcpu_sys_reg(vcpu, rd->reg) = val;
330 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
331 struct sys_reg_params *p,
332 const struct sys_reg_desc *r)
335 return ignore_write(vcpu, p);
337 p->regval = read_sysreg(dbgauthstatus_el1);
343 * We want to avoid world-switching all the DBG registers all the
346 * - If we've touched any debug register, it is likely that we're
347 * going to touch more of them. It then makes sense to disable the
348 * traps and start doing the save/restore dance
349 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
350 * then mandatory to save/restore the registers, as the guest
353 * For this, we use a DIRTY bit, indicating the guest has modified the
354 * debug registers, used as follow:
357 * - If the dirty bit is set (because we're coming back from trapping),
358 * disable the traps, save host registers, restore guest registers.
359 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
360 * set the dirty bit, disable the traps, save host registers,
361 * restore guest registers.
362 * - Otherwise, enable the traps
365 * - If the dirty bit is set, save guest registers, restore host
366 * registers and clear the dirty bit. This ensure that the host can
367 * now use the debug registers.
369 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
370 struct sys_reg_params *p,
371 const struct sys_reg_desc *r)
374 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
375 vcpu_set_flag(vcpu, DEBUG_DIRTY);
377 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
380 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
386 * reg_to_dbg/dbg_to_reg
388 * A 32 bit write to a debug register leave top bits alone
389 * A 32 bit read from a debug register only returns the bottom bits
391 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code
392 * switches between host and guest values in future.
394 static void reg_to_dbg(struct kvm_vcpu *vcpu,
395 struct sys_reg_params *p,
396 const struct sys_reg_desc *rd,
399 u64 mask, shift, val;
401 get_access_mask(rd, &mask, &shift);
405 val |= (p->regval & (mask >> shift)) << shift;
408 vcpu_set_flag(vcpu, DEBUG_DIRTY);
411 static void dbg_to_reg(struct kvm_vcpu *vcpu,
412 struct sys_reg_params *p,
413 const struct sys_reg_desc *rd,
418 get_access_mask(rd, &mask, &shift);
419 p->regval = (*dbg_reg & mask) >> shift;
422 static bool trap_bvr(struct kvm_vcpu *vcpu,
423 struct sys_reg_params *p,
424 const struct sys_reg_desc *rd)
426 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
429 reg_to_dbg(vcpu, p, rd, dbg_reg);
431 dbg_to_reg(vcpu, p, rd, dbg_reg);
433 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
438 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
441 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val;
445 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
448 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
452 static void reset_bvr(struct kvm_vcpu *vcpu,
453 const struct sys_reg_desc *rd)
455 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
458 static bool trap_bcr(struct kvm_vcpu *vcpu,
459 struct sys_reg_params *p,
460 const struct sys_reg_desc *rd)
462 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
465 reg_to_dbg(vcpu, p, rd, dbg_reg);
467 dbg_to_reg(vcpu, p, rd, dbg_reg);
469 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
474 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
477 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val;
481 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
484 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
488 static void reset_bcr(struct kvm_vcpu *vcpu,
489 const struct sys_reg_desc *rd)
491 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
494 static bool trap_wvr(struct kvm_vcpu *vcpu,
495 struct sys_reg_params *p,
496 const struct sys_reg_desc *rd)
498 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
501 reg_to_dbg(vcpu, p, rd, dbg_reg);
503 dbg_to_reg(vcpu, p, rd, dbg_reg);
505 trace_trap_reg(__func__, rd->CRm, p->is_write,
506 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
511 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
514 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val;
518 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
521 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
525 static void reset_wvr(struct kvm_vcpu *vcpu,
526 const struct sys_reg_desc *rd)
528 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
531 static bool trap_wcr(struct kvm_vcpu *vcpu,
532 struct sys_reg_params *p,
533 const struct sys_reg_desc *rd)
535 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
538 reg_to_dbg(vcpu, p, rd, dbg_reg);
540 dbg_to_reg(vcpu, p, rd, dbg_reg);
542 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
547 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
550 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val;
554 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
557 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
561 static void reset_wcr(struct kvm_vcpu *vcpu,
562 const struct sys_reg_desc *rd)
564 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
567 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
569 u64 amair = read_sysreg(amair_el1);
570 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
573 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
575 u64 actlr = read_sysreg(actlr_el1);
576 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
579 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
584 * Map the vcpu_id into the first three affinity level fields of
585 * the MPIDR. We limit the number of VCPUs in level 0 due to a
586 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
587 * of the GICv3 to be able to address each CPU directly when
590 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
591 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
592 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
593 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
596 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
597 const struct sys_reg_desc *r)
599 if (kvm_vcpu_has_pmu(vcpu))
605 static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
607 u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
609 /* No PMU available, any PMU reg may UNDEF... */
610 if (!kvm_arm_support_pmu_v3())
613 n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
614 n &= ARMV8_PMU_PMCR_N_MASK;
616 mask |= GENMASK(n - 1, 0);
618 reset_unknown(vcpu, r);
619 __vcpu_sys_reg(vcpu, r->reg) &= mask;
622 static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
624 reset_unknown(vcpu, r);
625 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
628 static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
630 reset_unknown(vcpu, r);
631 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK;
634 static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
636 reset_unknown(vcpu, r);
637 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
640 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
644 /* No PMU available, PMCR_EL0 may UNDEF... */
645 if (!kvm_arm_support_pmu_v3())
648 pmcr = read_sysreg(pmcr_el0);
650 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
651 * except PMCR.E resetting to zero.
653 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
654 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
655 if (!kvm_supports_32bit_el0())
656 val |= ARMV8_PMU_PMCR_LC;
657 __vcpu_sys_reg(vcpu, r->reg) = val;
660 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
662 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
663 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
666 kvm_inject_undefined(vcpu);
671 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
673 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
676 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
678 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
681 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
683 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
686 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
688 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
691 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
692 const struct sys_reg_desc *r)
696 if (pmu_access_el0_disabled(vcpu))
700 /* Only update writeable bits of PMCR */
701 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
702 val &= ~ARMV8_PMU_PMCR_MASK;
703 val |= p->regval & ARMV8_PMU_PMCR_MASK;
704 if (!kvm_supports_32bit_el0())
705 val |= ARMV8_PMU_PMCR_LC;
706 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
707 kvm_pmu_handle_pmcr(vcpu, val);
708 kvm_vcpu_pmu_restore_guest(vcpu);
710 /* PMCR.P & PMCR.C are RAZ */
711 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
712 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
719 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
720 const struct sys_reg_desc *r)
722 if (pmu_access_event_counter_el0_disabled(vcpu))
726 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
728 /* return PMSELR.SEL field */
729 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
730 & ARMV8_PMU_COUNTER_MASK;
735 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
736 const struct sys_reg_desc *r)
738 u64 pmceid, mask, shift;
742 if (pmu_access_el0_disabled(vcpu))
745 get_access_mask(r, &mask, &shift);
747 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
756 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
760 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
761 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
762 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
763 kvm_inject_undefined(vcpu);
770 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
771 struct sys_reg_params *p,
772 const struct sys_reg_desc *r)
776 if (r->CRn == 9 && r->CRm == 13) {
779 if (pmu_access_event_counter_el0_disabled(vcpu))
782 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
783 & ARMV8_PMU_COUNTER_MASK;
784 } else if (r->Op2 == 0) {
786 if (pmu_access_cycle_counter_el0_disabled(vcpu))
789 idx = ARMV8_PMU_CYCLE_IDX;
791 } else if (r->CRn == 0 && r->CRm == 9) {
793 if (pmu_access_event_counter_el0_disabled(vcpu))
796 idx = ARMV8_PMU_CYCLE_IDX;
797 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
799 if (pmu_access_event_counter_el0_disabled(vcpu))
802 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
805 /* Catch any decoding mistake */
806 WARN_ON(idx == ~0UL);
808 if (!pmu_counter_idx_valid(vcpu, idx))
812 if (pmu_access_el0_disabled(vcpu))
815 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
817 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
823 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
824 const struct sys_reg_desc *r)
828 if (pmu_access_el0_disabled(vcpu))
831 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
833 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
834 reg = PMEVTYPER0_EL0 + idx;
835 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
836 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
837 if (idx == ARMV8_PMU_CYCLE_IDX)
841 reg = PMEVTYPER0_EL0 + idx;
846 if (!pmu_counter_idx_valid(vcpu, idx))
850 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
851 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
852 kvm_vcpu_pmu_restore_guest(vcpu);
854 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
860 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
861 const struct sys_reg_desc *r)
865 if (pmu_access_el0_disabled(vcpu))
868 mask = kvm_pmu_valid_counter_mask(vcpu);
870 val = p->regval & mask;
872 /* accessing PMCNTENSET_EL0 */
873 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
874 kvm_pmu_enable_counter_mask(vcpu, val);
875 kvm_vcpu_pmu_restore_guest(vcpu);
877 /* accessing PMCNTENCLR_EL0 */
878 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
879 kvm_pmu_disable_counter_mask(vcpu, val);
882 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
888 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
889 const struct sys_reg_desc *r)
891 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
893 if (check_pmu_access_disabled(vcpu, 0))
897 u64 val = p->regval & mask;
900 /* accessing PMINTENSET_EL1 */
901 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
903 /* accessing PMINTENCLR_EL1 */
904 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
906 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
912 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
913 const struct sys_reg_desc *r)
915 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
917 if (pmu_access_el0_disabled(vcpu))
922 /* accessing PMOVSSET_EL0 */
923 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
925 /* accessing PMOVSCLR_EL0 */
926 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
928 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
934 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
935 const struct sys_reg_desc *r)
940 return read_from_write_only(vcpu, p, r);
942 if (pmu_write_swinc_el0_disabled(vcpu))
945 mask = kvm_pmu_valid_counter_mask(vcpu);
946 kvm_pmu_software_increment(vcpu, p->regval & mask);
950 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
951 const struct sys_reg_desc *r)
954 if (!vcpu_mode_priv(vcpu)) {
955 kvm_inject_undefined(vcpu);
959 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
960 p->regval & ARMV8_PMU_USERENR_MASK;
962 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
963 & ARMV8_PMU_USERENR_MASK;
969 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
970 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
971 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
972 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
973 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
974 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
975 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
976 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
977 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
978 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
980 #define PMU_SYS_REG(r) \
981 SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility
983 /* Macro to expand the PMEVCNTRn_EL0 register */
984 #define PMU_PMEVCNTR_EL0(n) \
985 { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \
986 .reset = reset_pmevcntr, \
987 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
989 /* Macro to expand the PMEVTYPERn_EL0 register */
990 #define PMU_PMEVTYPER_EL0(n) \
991 { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \
992 .reset = reset_pmevtyper, \
993 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
995 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
996 const struct sys_reg_desc *r)
998 kvm_inject_undefined(vcpu);
1003 /* Macro to expand the AMU counter and type registers*/
1004 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
1005 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
1006 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
1007 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
1009 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1010 const struct sys_reg_desc *rd)
1012 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
1016 * If we land here on a PtrAuth access, that is because we didn't
1017 * fixup the access on exit by allowing the PtrAuth sysregs. The only
1018 * way this happens is when the guest does not have PtrAuth support
1021 #define __PTRAUTH_KEY(k) \
1022 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
1023 .visibility = ptrauth_visibility}
1025 #define PTRAUTH_KEY(k) \
1026 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1027 __PTRAUTH_KEY(k ## KEYHI_EL1)
1029 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1030 struct sys_reg_params *p,
1031 const struct sys_reg_desc *r)
1033 enum kvm_arch_timers tmr;
1034 enum kvm_arch_timer_regs treg;
1035 u64 reg = reg_to_encoding(r);
1038 case SYS_CNTP_TVAL_EL0:
1039 case SYS_AARCH32_CNTP_TVAL:
1041 treg = TIMER_REG_TVAL;
1043 case SYS_CNTP_CTL_EL0:
1044 case SYS_AARCH32_CNTP_CTL:
1046 treg = TIMER_REG_CTL;
1048 case SYS_CNTP_CVAL_EL0:
1049 case SYS_AARCH32_CNTP_CVAL:
1051 treg = TIMER_REG_CVAL;
1058 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1060 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1065 /* Read a sanitised cpufeature ID register by sys_reg_desc */
1066 static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r)
1068 u32 id = reg_to_encoding(r);
1071 if (sysreg_visible_as_raz(vcpu, r))
1074 val = read_sanitised_ftr_reg(id);
1077 case SYS_ID_AA64PFR0_EL1:
1078 if (!vcpu_has_sve(vcpu))
1079 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE);
1080 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU);
1081 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2);
1082 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
1083 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3);
1084 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
1085 if (kvm_vgic_global_state.type == VGIC_V3) {
1086 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC);
1087 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1);
1090 case SYS_ID_AA64PFR1_EL1:
1091 if (!kvm_has_mte(vcpu->kvm))
1092 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
1094 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME);
1096 case SYS_ID_AA64ISAR1_EL1:
1097 if (!vcpu_has_ptrauth(vcpu))
1098 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
1099 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
1100 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
1101 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
1103 case SYS_ID_AA64ISAR2_EL1:
1104 if (!vcpu_has_ptrauth(vcpu))
1105 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
1106 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
1107 if (!cpus_have_final_cap(ARM64_HAS_WFXT))
1108 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
1110 case SYS_ID_AA64DFR0_EL1:
1111 /* Limit debug to ARMv8.0 */
1112 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
1113 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
1114 /* Limit guests to PMUv3 for ARMv8.4 */
1115 val = cpuid_feature_cap_perfmon_field(val,
1116 ID_AA64DFR0_EL1_PMUVer_SHIFT,
1117 kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_EL1_PMUVer_V3P4 : 0);
1118 /* Hide SPE from guests */
1119 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
1121 case SYS_ID_DFR0_EL1:
1122 /* Limit guests to PMUv3 for ARMv8.4 */
1123 val = cpuid_feature_cap_perfmon_field(val,
1124 ID_DFR0_PERFMON_SHIFT,
1125 kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
1132 static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1133 const struct sys_reg_desc *r)
1135 u32 id = reg_to_encoding(r);
1138 case SYS_ID_AA64ZFR0_EL1:
1139 if (!vcpu_has_sve(vcpu))
1147 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
1148 const struct sys_reg_desc *r)
1151 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any
1152 * EL. Promote to RAZ/WI in order to guarantee consistency between
1155 if (!kvm_supports_32bit_el0())
1156 return REG_RAZ | REG_USER_WI;
1158 return id_visibility(vcpu, r);
1161 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu,
1162 const struct sys_reg_desc *r)
1167 /* cpufeature ID register access trap handlers */
1169 static bool access_id_reg(struct kvm_vcpu *vcpu,
1170 struct sys_reg_params *p,
1171 const struct sys_reg_desc *r)
1174 return write_to_read_only(vcpu, p, r);
1176 p->regval = read_id_reg(vcpu, r);
1180 /* Visibility overrides for SVE-specific control registers */
1181 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1182 const struct sys_reg_desc *rd)
1184 if (vcpu_has_sve(vcpu))
1190 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1191 const struct sys_reg_desc *rd,
1197 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
1198 * it doesn't promise more than what is actually provided (the
1199 * guest could otherwise be covered in ectoplasmic residue).
1201 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV2_SHIFT);
1203 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED))
1206 /* Same thing for CSV3 */
1207 csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV3_SHIFT);
1209 (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
1212 /* We can only differ with CSV[23], and anything else is an error */
1213 val ^= read_id_reg(vcpu, rd);
1214 val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) |
1215 ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3));
1219 vcpu->kvm->arch.pfr0_csv2 = csv2;
1220 vcpu->kvm->arch.pfr0_csv3 = csv3;
1226 * cpufeature ID register user accessors
1228 * For now, these registers are immutable for userspace, so no values
1229 * are stored, and for set_id_reg() we don't allow the effective value
1232 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1235 *val = read_id_reg(vcpu, rd);
1239 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1242 /* This is what we mean by invariant: you can't change it. */
1243 if (val != read_id_reg(vcpu, rd))
1249 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1256 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1262 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1263 const struct sys_reg_desc *r)
1266 return write_to_read_only(vcpu, p, r);
1268 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1272 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1273 const struct sys_reg_desc *r)
1276 return write_to_read_only(vcpu, p, r);
1278 p->regval = read_sysreg(clidr_el1);
1282 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1283 const struct sys_reg_desc *r)
1288 vcpu_write_sys_reg(vcpu, p->regval, reg);
1290 p->regval = vcpu_read_sys_reg(vcpu, reg);
1294 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1295 const struct sys_reg_desc *r)
1300 return write_to_read_only(vcpu, p, r);
1302 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1303 p->regval = get_ccsidr(csselr);
1306 * Guests should not be doing cache operations by set/way at all, and
1307 * for this reason, we trap them and attempt to infer the intent, so
1308 * that we can flush the entire guest's address space at the appropriate
1310 * To prevent this trapping from causing performance problems, let's
1311 * expose the geometry of all data and unified caches (which are
1312 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1313 * [If guests should attempt to infer aliasing properties from the
1314 * geometry (which is not permitted by the architecture), they would
1315 * only do so for virtually indexed caches.]
1317 if (!(csselr & 1)) // data or unified cache
1318 p->regval &= ~GENMASK(27, 3);
1322 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu,
1323 const struct sys_reg_desc *rd)
1325 if (kvm_has_mte(vcpu->kvm))
1331 #define MTE_REG(name) { \
1332 SYS_DESC(SYS_##name), \
1333 .access = undef_access, \
1334 .reset = reset_unknown, \
1336 .visibility = mte_visibility, \
1339 /* sys_reg_desc initialiser for known cpufeature ID registers */
1340 #define ID_SANITISED(name) { \
1341 SYS_DESC(SYS_##name), \
1342 .access = access_id_reg, \
1343 .get_user = get_id_reg, \
1344 .set_user = set_id_reg, \
1345 .visibility = id_visibility, \
1348 /* sys_reg_desc initialiser for known cpufeature ID registers */
1349 #define AA32_ID_SANITISED(name) { \
1350 SYS_DESC(SYS_##name), \
1351 .access = access_id_reg, \
1352 .get_user = get_id_reg, \
1353 .set_user = set_id_reg, \
1354 .visibility = aa32_id_visibility, \
1358 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1359 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1360 * (1 <= crm < 8, 0 <= Op2 < 8).
1362 #define ID_UNALLOCATED(crm, op2) { \
1363 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1364 .access = access_id_reg, \
1365 .get_user = get_id_reg, \
1366 .set_user = set_id_reg, \
1367 .visibility = raz_visibility \
1371 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1372 * For now, these are exposed just like unallocated ID regs: they appear
1373 * RAZ for the guest.
1375 #define ID_HIDDEN(name) { \
1376 SYS_DESC(SYS_##name), \
1377 .access = access_id_reg, \
1378 .get_user = get_id_reg, \
1379 .set_user = set_id_reg, \
1380 .visibility = raz_visibility, \
1384 * Architected system registers.
1385 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1387 * Debug handling: We do trap most, if not all debug related system
1388 * registers. The implementation is good enough to ensure that a guest
1389 * can use these with minimal performance degradation. The drawback is
1390 * that we don't implement any of the external debug architecture.
1391 * This should be revisited if we ever encounter a more demanding
1394 static const struct sys_reg_desc sys_reg_descs[] = {
1395 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1396 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1397 { SYS_DESC(SYS_DC_CISW), access_dcsw },
1399 DBG_BCR_BVR_WCR_WVR_EL1(0),
1400 DBG_BCR_BVR_WCR_WVR_EL1(1),
1401 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1402 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1403 DBG_BCR_BVR_WCR_WVR_EL1(2),
1404 DBG_BCR_BVR_WCR_WVR_EL1(3),
1405 DBG_BCR_BVR_WCR_WVR_EL1(4),
1406 DBG_BCR_BVR_WCR_WVR_EL1(5),
1407 DBG_BCR_BVR_WCR_WVR_EL1(6),
1408 DBG_BCR_BVR_WCR_WVR_EL1(7),
1409 DBG_BCR_BVR_WCR_WVR_EL1(8),
1410 DBG_BCR_BVR_WCR_WVR_EL1(9),
1411 DBG_BCR_BVR_WCR_WVR_EL1(10),
1412 DBG_BCR_BVR_WCR_WVR_EL1(11),
1413 DBG_BCR_BVR_WCR_WVR_EL1(12),
1414 DBG_BCR_BVR_WCR_WVR_EL1(13),
1415 DBG_BCR_BVR_WCR_WVR_EL1(14),
1416 DBG_BCR_BVR_WCR_WVR_EL1(15),
1418 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1419 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 },
1420 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
1421 SYS_OSLSR_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, },
1422 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1423 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1424 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1425 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1426 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1428 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1429 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1430 // DBGDTR[TR]X_EL0 share the same encoding
1431 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1433 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1435 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1438 * ID regs: all ID_SANITISED() entries here must have corresponding
1439 * entries in arm64_ftr_regs[].
1442 /* AArch64 mappings of the AArch32 ID registers */
1444 AA32_ID_SANITISED(ID_PFR0_EL1),
1445 AA32_ID_SANITISED(ID_PFR1_EL1),
1446 AA32_ID_SANITISED(ID_DFR0_EL1),
1447 ID_HIDDEN(ID_AFR0_EL1),
1448 AA32_ID_SANITISED(ID_MMFR0_EL1),
1449 AA32_ID_SANITISED(ID_MMFR1_EL1),
1450 AA32_ID_SANITISED(ID_MMFR2_EL1),
1451 AA32_ID_SANITISED(ID_MMFR3_EL1),
1454 AA32_ID_SANITISED(ID_ISAR0_EL1),
1455 AA32_ID_SANITISED(ID_ISAR1_EL1),
1456 AA32_ID_SANITISED(ID_ISAR2_EL1),
1457 AA32_ID_SANITISED(ID_ISAR3_EL1),
1458 AA32_ID_SANITISED(ID_ISAR4_EL1),
1459 AA32_ID_SANITISED(ID_ISAR5_EL1),
1460 AA32_ID_SANITISED(ID_MMFR4_EL1),
1461 AA32_ID_SANITISED(ID_ISAR6_EL1),
1464 AA32_ID_SANITISED(MVFR0_EL1),
1465 AA32_ID_SANITISED(MVFR1_EL1),
1466 AA32_ID_SANITISED(MVFR2_EL1),
1467 ID_UNALLOCATED(3,3),
1468 AA32_ID_SANITISED(ID_PFR2_EL1),
1469 ID_HIDDEN(ID_DFR1_EL1),
1470 AA32_ID_SANITISED(ID_MMFR5_EL1),
1471 ID_UNALLOCATED(3,7),
1473 /* AArch64 ID registers */
1475 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
1476 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
1477 ID_SANITISED(ID_AA64PFR1_EL1),
1478 ID_UNALLOCATED(4,2),
1479 ID_UNALLOCATED(4,3),
1480 ID_SANITISED(ID_AA64ZFR0_EL1),
1481 ID_HIDDEN(ID_AA64SMFR0_EL1),
1482 ID_UNALLOCATED(4,6),
1483 ID_UNALLOCATED(4,7),
1486 ID_SANITISED(ID_AA64DFR0_EL1),
1487 ID_SANITISED(ID_AA64DFR1_EL1),
1488 ID_UNALLOCATED(5,2),
1489 ID_UNALLOCATED(5,3),
1490 ID_HIDDEN(ID_AA64AFR0_EL1),
1491 ID_HIDDEN(ID_AA64AFR1_EL1),
1492 ID_UNALLOCATED(5,6),
1493 ID_UNALLOCATED(5,7),
1496 ID_SANITISED(ID_AA64ISAR0_EL1),
1497 ID_SANITISED(ID_AA64ISAR1_EL1),
1498 ID_SANITISED(ID_AA64ISAR2_EL1),
1499 ID_UNALLOCATED(6,3),
1500 ID_UNALLOCATED(6,4),
1501 ID_UNALLOCATED(6,5),
1502 ID_UNALLOCATED(6,6),
1503 ID_UNALLOCATED(6,7),
1506 ID_SANITISED(ID_AA64MMFR0_EL1),
1507 ID_SANITISED(ID_AA64MMFR1_EL1),
1508 ID_SANITISED(ID_AA64MMFR2_EL1),
1509 ID_UNALLOCATED(7,3),
1510 ID_UNALLOCATED(7,4),
1511 ID_UNALLOCATED(7,5),
1512 ID_UNALLOCATED(7,6),
1513 ID_UNALLOCATED(7,7),
1515 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1516 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
1517 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
1522 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
1523 { SYS_DESC(SYS_TRFCR_EL1), undef_access },
1524 { SYS_DESC(SYS_SMPRI_EL1), undef_access },
1525 { SYS_DESC(SYS_SMCR_EL1), undef_access },
1526 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1527 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1528 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1536 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1537 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1538 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
1540 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1541 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1542 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1543 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1544 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1545 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1546 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1547 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1550 MTE_REG(TFSRE0_EL1),
1552 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1553 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
1555 { SYS_DESC(SYS_PMSCR_EL1), undef_access },
1556 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
1557 { SYS_DESC(SYS_PMSICR_EL1), undef_access },
1558 { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
1559 { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
1560 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
1561 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
1562 { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
1563 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
1564 { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
1565 { SYS_DESC(SYS_PMBSR_EL1), undef_access },
1566 /* PMBIDR_EL1 is not trapped */
1568 { PMU_SYS_REG(SYS_PMINTENSET_EL1),
1569 .access = access_pminten, .reg = PMINTENSET_EL1 },
1570 { PMU_SYS_REG(SYS_PMINTENCLR_EL1),
1571 .access = access_pminten, .reg = PMINTENSET_EL1 },
1572 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
1574 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1575 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1577 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1578 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1579 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1580 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1581 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
1583 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1584 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
1586 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
1587 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
1588 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
1589 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
1590 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
1591 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
1592 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1593 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
1594 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
1595 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
1596 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
1597 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
1599 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1600 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
1602 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
1604 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
1606 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1607 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1608 { SYS_DESC(SYS_SMIDR_EL1), undef_access },
1609 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1610 { SYS_DESC(SYS_CTR_EL0), access_ctr },
1611 { SYS_DESC(SYS_SVCR), undef_access },
1613 { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr,
1614 .reset = reset_pmcr, .reg = PMCR_EL0 },
1615 { PMU_SYS_REG(SYS_PMCNTENSET_EL0),
1616 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
1617 { PMU_SYS_REG(SYS_PMCNTENCLR_EL0),
1618 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
1619 { PMU_SYS_REG(SYS_PMOVSCLR_EL0),
1620 .access = access_pmovs, .reg = PMOVSSET_EL0 },
1622 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
1623 * previously (and pointlessly) advertised in the past...
1625 { PMU_SYS_REG(SYS_PMSWINC_EL0),
1626 .get_user = get_raz_reg, .set_user = set_wi_reg,
1627 .access = access_pmswinc, .reset = NULL },
1628 { PMU_SYS_REG(SYS_PMSELR_EL0),
1629 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
1630 { PMU_SYS_REG(SYS_PMCEID0_EL0),
1631 .access = access_pmceid, .reset = NULL },
1632 { PMU_SYS_REG(SYS_PMCEID1_EL0),
1633 .access = access_pmceid, .reset = NULL },
1634 { PMU_SYS_REG(SYS_PMCCNTR_EL0),
1635 .access = access_pmu_evcntr, .reset = reset_unknown, .reg = PMCCNTR_EL0 },
1636 { PMU_SYS_REG(SYS_PMXEVTYPER_EL0),
1637 .access = access_pmu_evtyper, .reset = NULL },
1638 { PMU_SYS_REG(SYS_PMXEVCNTR_EL0),
1639 .access = access_pmu_evcntr, .reset = NULL },
1641 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1642 * in 32bit mode. Here we choose to reset it as zero for consistency.
1644 { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr,
1645 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
1646 { PMU_SYS_REG(SYS_PMOVSSET_EL0),
1647 .access = access_pmovs, .reg = PMOVSSET_EL0 },
1649 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1650 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1651 { SYS_DESC(SYS_TPIDR2_EL0), undef_access },
1653 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
1655 { SYS_DESC(SYS_AMCR_EL0), undef_access },
1656 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
1657 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
1658 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
1659 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
1660 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
1661 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
1662 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
1663 AMU_AMEVCNTR0_EL0(0),
1664 AMU_AMEVCNTR0_EL0(1),
1665 AMU_AMEVCNTR0_EL0(2),
1666 AMU_AMEVCNTR0_EL0(3),
1667 AMU_AMEVCNTR0_EL0(4),
1668 AMU_AMEVCNTR0_EL0(5),
1669 AMU_AMEVCNTR0_EL0(6),
1670 AMU_AMEVCNTR0_EL0(7),
1671 AMU_AMEVCNTR0_EL0(8),
1672 AMU_AMEVCNTR0_EL0(9),
1673 AMU_AMEVCNTR0_EL0(10),
1674 AMU_AMEVCNTR0_EL0(11),
1675 AMU_AMEVCNTR0_EL0(12),
1676 AMU_AMEVCNTR0_EL0(13),
1677 AMU_AMEVCNTR0_EL0(14),
1678 AMU_AMEVCNTR0_EL0(15),
1679 AMU_AMEVTYPER0_EL0(0),
1680 AMU_AMEVTYPER0_EL0(1),
1681 AMU_AMEVTYPER0_EL0(2),
1682 AMU_AMEVTYPER0_EL0(3),
1683 AMU_AMEVTYPER0_EL0(4),
1684 AMU_AMEVTYPER0_EL0(5),
1685 AMU_AMEVTYPER0_EL0(6),
1686 AMU_AMEVTYPER0_EL0(7),
1687 AMU_AMEVTYPER0_EL0(8),
1688 AMU_AMEVTYPER0_EL0(9),
1689 AMU_AMEVTYPER0_EL0(10),
1690 AMU_AMEVTYPER0_EL0(11),
1691 AMU_AMEVTYPER0_EL0(12),
1692 AMU_AMEVTYPER0_EL0(13),
1693 AMU_AMEVTYPER0_EL0(14),
1694 AMU_AMEVTYPER0_EL0(15),
1695 AMU_AMEVCNTR1_EL0(0),
1696 AMU_AMEVCNTR1_EL0(1),
1697 AMU_AMEVCNTR1_EL0(2),
1698 AMU_AMEVCNTR1_EL0(3),
1699 AMU_AMEVCNTR1_EL0(4),
1700 AMU_AMEVCNTR1_EL0(5),
1701 AMU_AMEVCNTR1_EL0(6),
1702 AMU_AMEVCNTR1_EL0(7),
1703 AMU_AMEVCNTR1_EL0(8),
1704 AMU_AMEVCNTR1_EL0(9),
1705 AMU_AMEVCNTR1_EL0(10),
1706 AMU_AMEVCNTR1_EL0(11),
1707 AMU_AMEVCNTR1_EL0(12),
1708 AMU_AMEVCNTR1_EL0(13),
1709 AMU_AMEVCNTR1_EL0(14),
1710 AMU_AMEVCNTR1_EL0(15),
1711 AMU_AMEVTYPER1_EL0(0),
1712 AMU_AMEVTYPER1_EL0(1),
1713 AMU_AMEVTYPER1_EL0(2),
1714 AMU_AMEVTYPER1_EL0(3),
1715 AMU_AMEVTYPER1_EL0(4),
1716 AMU_AMEVTYPER1_EL0(5),
1717 AMU_AMEVTYPER1_EL0(6),
1718 AMU_AMEVTYPER1_EL0(7),
1719 AMU_AMEVTYPER1_EL0(8),
1720 AMU_AMEVTYPER1_EL0(9),
1721 AMU_AMEVTYPER1_EL0(10),
1722 AMU_AMEVTYPER1_EL0(11),
1723 AMU_AMEVTYPER1_EL0(12),
1724 AMU_AMEVTYPER1_EL0(13),
1725 AMU_AMEVTYPER1_EL0(14),
1726 AMU_AMEVTYPER1_EL0(15),
1728 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1729 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1730 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
1733 PMU_PMEVCNTR_EL0(0),
1734 PMU_PMEVCNTR_EL0(1),
1735 PMU_PMEVCNTR_EL0(2),
1736 PMU_PMEVCNTR_EL0(3),
1737 PMU_PMEVCNTR_EL0(4),
1738 PMU_PMEVCNTR_EL0(5),
1739 PMU_PMEVCNTR_EL0(6),
1740 PMU_PMEVCNTR_EL0(7),
1741 PMU_PMEVCNTR_EL0(8),
1742 PMU_PMEVCNTR_EL0(9),
1743 PMU_PMEVCNTR_EL0(10),
1744 PMU_PMEVCNTR_EL0(11),
1745 PMU_PMEVCNTR_EL0(12),
1746 PMU_PMEVCNTR_EL0(13),
1747 PMU_PMEVCNTR_EL0(14),
1748 PMU_PMEVCNTR_EL0(15),
1749 PMU_PMEVCNTR_EL0(16),
1750 PMU_PMEVCNTR_EL0(17),
1751 PMU_PMEVCNTR_EL0(18),
1752 PMU_PMEVCNTR_EL0(19),
1753 PMU_PMEVCNTR_EL0(20),
1754 PMU_PMEVCNTR_EL0(21),
1755 PMU_PMEVCNTR_EL0(22),
1756 PMU_PMEVCNTR_EL0(23),
1757 PMU_PMEVCNTR_EL0(24),
1758 PMU_PMEVCNTR_EL0(25),
1759 PMU_PMEVCNTR_EL0(26),
1760 PMU_PMEVCNTR_EL0(27),
1761 PMU_PMEVCNTR_EL0(28),
1762 PMU_PMEVCNTR_EL0(29),
1763 PMU_PMEVCNTR_EL0(30),
1764 /* PMEVTYPERn_EL0 */
1765 PMU_PMEVTYPER_EL0(0),
1766 PMU_PMEVTYPER_EL0(1),
1767 PMU_PMEVTYPER_EL0(2),
1768 PMU_PMEVTYPER_EL0(3),
1769 PMU_PMEVTYPER_EL0(4),
1770 PMU_PMEVTYPER_EL0(5),
1771 PMU_PMEVTYPER_EL0(6),
1772 PMU_PMEVTYPER_EL0(7),
1773 PMU_PMEVTYPER_EL0(8),
1774 PMU_PMEVTYPER_EL0(9),
1775 PMU_PMEVTYPER_EL0(10),
1776 PMU_PMEVTYPER_EL0(11),
1777 PMU_PMEVTYPER_EL0(12),
1778 PMU_PMEVTYPER_EL0(13),
1779 PMU_PMEVTYPER_EL0(14),
1780 PMU_PMEVTYPER_EL0(15),
1781 PMU_PMEVTYPER_EL0(16),
1782 PMU_PMEVTYPER_EL0(17),
1783 PMU_PMEVTYPER_EL0(18),
1784 PMU_PMEVTYPER_EL0(19),
1785 PMU_PMEVTYPER_EL0(20),
1786 PMU_PMEVTYPER_EL0(21),
1787 PMU_PMEVTYPER_EL0(22),
1788 PMU_PMEVTYPER_EL0(23),
1789 PMU_PMEVTYPER_EL0(24),
1790 PMU_PMEVTYPER_EL0(25),
1791 PMU_PMEVTYPER_EL0(26),
1792 PMU_PMEVTYPER_EL0(27),
1793 PMU_PMEVTYPER_EL0(28),
1794 PMU_PMEVTYPER_EL0(29),
1795 PMU_PMEVTYPER_EL0(30),
1797 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1798 * in 32bit mode. Here we choose to reset it as zero for consistency.
1800 { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper,
1801 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
1803 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1804 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1805 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1808 static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
1809 struct sys_reg_params *p,
1810 const struct sys_reg_desc *r)
1813 return ignore_write(vcpu, p);
1815 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1816 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1817 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL1_EL3_SHIFT);
1819 p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << 28) |
1820 (((dfr >> ID_AA64DFR0_EL1_BRPs_SHIFT) & 0xf) << 24) |
1821 (((dfr >> ID_AA64DFR0_EL1_CTX_CMPs_SHIFT) & 0xf) << 20)
1822 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12));
1828 * AArch32 debug register mappings
1830 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1831 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1833 * None of the other registers share their location, so treat them as
1834 * if they were 64bit.
1836 #define DBG_BCR_BVR_WCR_WVR(n) \
1838 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1840 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1842 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1844 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1846 #define DBGBXVR(n) \
1847 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
1850 * Trapped cp14 registers. We generally ignore most of the external
1851 * debug, on the principle that they don't really make sense to a
1852 * guest. Revisit this one day, would this principle change.
1854 static const struct sys_reg_desc cp14_regs[] = {
1856 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
1858 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1860 DBG_BCR_BVR_WCR_WVR(0),
1862 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1863 DBG_BCR_BVR_WCR_WVR(1),
1865 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
1867 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
1868 DBG_BCR_BVR_WCR_WVR(2),
1869 /* DBGDTR[RT]Xint */
1870 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1871 /* DBGDTR[RT]Xext */
1872 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1873 DBG_BCR_BVR_WCR_WVR(3),
1874 DBG_BCR_BVR_WCR_WVR(4),
1875 DBG_BCR_BVR_WCR_WVR(5),
1877 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1879 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1880 DBG_BCR_BVR_WCR_WVR(6),
1882 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
1883 DBG_BCR_BVR_WCR_WVR(7),
1884 DBG_BCR_BVR_WCR_WVR(8),
1885 DBG_BCR_BVR_WCR_WVR(9),
1886 DBG_BCR_BVR_WCR_WVR(10),
1887 DBG_BCR_BVR_WCR_WVR(11),
1888 DBG_BCR_BVR_WCR_WVR(12),
1889 DBG_BCR_BVR_WCR_WVR(13),
1890 DBG_BCR_BVR_WCR_WVR(14),
1891 DBG_BCR_BVR_WCR_WVR(15),
1893 /* DBGDRAR (32bit) */
1894 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1898 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 },
1901 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 },
1905 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1908 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1921 /* DBGDSAR (32bit) */
1922 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1925 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1927 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1929 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1931 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1933 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1935 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1938 /* Trapped cp14 64bit registers */
1939 static const struct sys_reg_desc cp14_64_regs[] = {
1940 /* DBGDRAR (64bit) */
1941 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1943 /* DBGDSAR (64bit) */
1944 { Op1( 0), CRm( 2), .access = trap_raz_wi },
1947 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \
1949 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \
1950 .visibility = pmu_visibility
1952 /* Macro to expand the PMEVCNTRn register */
1953 #define PMU_PMEVCNTR(n) \
1954 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
1955 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
1956 .access = access_pmu_evcntr }
1958 /* Macro to expand the PMEVTYPERn register */
1959 #define PMU_PMEVTYPER(n) \
1960 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
1961 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
1962 .access = access_pmu_evtyper }
1964 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1965 * depending on the way they are accessed (as a 32bit or a 64bit
1968 static const struct sys_reg_desc cp15_regs[] = {
1969 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
1970 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
1972 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
1974 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
1975 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
1976 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
1978 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
1980 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
1981 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
1983 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
1984 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
1986 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
1988 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
1990 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
1992 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
1995 * DC{C,I,CI}SW operations:
1997 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1998 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1999 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
2002 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr },
2003 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten },
2004 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten },
2005 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs },
2006 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc },
2007 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr },
2008 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid },
2009 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid },
2010 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr },
2011 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper },
2012 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr },
2013 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr },
2014 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten },
2015 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten },
2016 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs },
2017 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid },
2018 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid },
2020 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi },
2023 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
2025 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
2027 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
2029 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
2032 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
2034 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
2037 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
2038 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
2105 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper },
2107 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2108 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2109 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
2112 static const struct sys_reg_desc cp15_64_regs[] = {
2113 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2114 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr },
2115 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2116 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
2117 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2118 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2119 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
2122 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2127 for (i = 0; i < n; i++) {
2128 if (!is_32 && table[i].reg && !table[i].reset) {
2129 kvm_err("sys_reg table %pS entry %d lacks reset\n", &table[i], i);
2133 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2134 kvm_err("sys_reg table %pS entry %d out of order\n", &table[i - 1], i - 1);
2142 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
2144 kvm_inject_undefined(vcpu);
2148 static void perform_access(struct kvm_vcpu *vcpu,
2149 struct sys_reg_params *params,
2150 const struct sys_reg_desc *r)
2152 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2154 /* Check for regs disabled by runtime config */
2155 if (sysreg_hidden(vcpu, r)) {
2156 kvm_inject_undefined(vcpu);
2161 * Not having an accessor means that we have configured a trap
2162 * that we don't know how to handle. This certainly qualifies
2163 * as a gross bug that should be fixed right away.
2167 /* Skip instruction if instructed so */
2168 if (likely(r->access(vcpu, params, r)))
2173 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2174 * call the corresponding trap handler.
2176 * @params: pointer to the descriptor of the access
2177 * @table: array of trap descriptors
2178 * @num: size of the trap descriptor array
2180 * Return true if the access has been handled, false if not.
2182 static bool emulate_cp(struct kvm_vcpu *vcpu,
2183 struct sys_reg_params *params,
2184 const struct sys_reg_desc *table,
2187 const struct sys_reg_desc *r;
2190 return false; /* Not handled */
2192 r = find_reg(params, table, num);
2195 perform_access(vcpu, params, r);
2203 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2204 struct sys_reg_params *params)
2206 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
2210 case ESR_ELx_EC_CP15_32:
2211 case ESR_ELx_EC_CP15_64:
2214 case ESR_ELx_EC_CP14_MR:
2215 case ESR_ELx_EC_CP14_64:
2222 print_sys_reg_msg(params,
2223 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2224 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2225 kvm_inject_undefined(vcpu);
2229 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
2230 * @vcpu: The VCPU pointer
2231 * @run: The kvm_run struct
2233 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2234 const struct sys_reg_desc *global,
2237 struct sys_reg_params params;
2238 u64 esr = kvm_vcpu_get_esr(vcpu);
2239 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2240 int Rt2 = (esr >> 10) & 0x1f;
2242 params.CRm = (esr >> 1) & 0xf;
2243 params.is_write = ((esr & 1) == 0);
2246 params.Op1 = (esr >> 16) & 0xf;
2251 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
2252 * backends between AArch32 and AArch64, we get away with it.
2254 if (params.is_write) {
2255 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2256 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
2260 * If the table contains a handler, handle the
2261 * potential register operation in the case of a read and return
2264 if (emulate_cp(vcpu, ¶ms, global, nr_global)) {
2265 /* Split up the value between registers for the read side */
2266 if (!params.is_write) {
2267 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2268 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2274 unhandled_cp_access(vcpu, ¶ms);
2278 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params);
2281 * The CP10 ID registers are architecturally mapped to AArch64 feature
2282 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses
2285 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params)
2287 u8 reg_id = (esr >> 10) & 0xf;
2290 params->is_write = ((esr & 1) == 0);
2296 /* CP10 ID registers are read-only */
2297 valid = !params->is_write;
2319 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n",
2320 params->is_write ? "write" : "read", reg_id);
2325 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and
2326 * VFP Register' from AArch32.
2327 * @vcpu: The vCPU pointer
2329 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers.
2330 * Work out the correct AArch64 system register encoding and reroute to the
2331 * AArch64 system register emulation.
2333 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu)
2335 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2336 u64 esr = kvm_vcpu_get_esr(vcpu);
2337 struct sys_reg_params params;
2339 /* UNDEF on any unhandled register access */
2340 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) {
2341 kvm_inject_undefined(vcpu);
2345 if (emulate_sys_reg(vcpu, ¶ms))
2346 vcpu_set_reg(vcpu, Rt, params.regval);
2352 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where
2353 * CRn=0, which corresponds to the AArch32 feature
2355 * @vcpu: the vCPU pointer
2356 * @params: the system register access parameters.
2358 * Our cp15 system register tables do not enumerate the AArch32 feature
2359 * registers. Conveniently, our AArch64 table does, and the AArch32 system
2360 * register encoding can be trivially remapped into the AArch64 for the feature
2361 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same.
2363 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit
2364 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this
2365 * range are either UNKNOWN or RES0. Rerouting remains architectural as we
2366 * treat undefined registers in this range as RAZ.
2368 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu,
2369 struct sys_reg_params *params)
2371 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2373 /* Treat impossible writes to RO registers as UNDEFINED */
2374 if (params->is_write) {
2375 unhandled_cp_access(vcpu, params);
2382 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32.
2383 * Avoid conflicting with future expansion of AArch64 feature registers
2384 * and simply treat them as RAZ here.
2386 if (params->CRm > 3)
2388 else if (!emulate_sys_reg(vcpu, params))
2391 vcpu_set_reg(vcpu, Rt, params->regval);
2396 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
2397 * @vcpu: The VCPU pointer
2398 * @run: The kvm_run struct
2400 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2401 struct sys_reg_params *params,
2402 const struct sys_reg_desc *global,
2405 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2407 params->regval = vcpu_get_reg(vcpu, Rt);
2409 if (emulate_cp(vcpu, params, global, nr_global)) {
2410 if (!params->is_write)
2411 vcpu_set_reg(vcpu, Rt, params->regval);
2415 unhandled_cp_access(vcpu, params);
2419 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
2421 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
2424 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
2426 struct sys_reg_params params;
2428 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
2431 * Certain AArch32 ID registers are handled by rerouting to the AArch64
2432 * system register table. Registers in the ID range where CRm=0 are
2433 * excluded from this scheme as they do not trivially map into AArch64
2434 * system register encodings.
2436 if (params.Op1 == 0 && params.CRn == 0 && params.CRm)
2437 return kvm_emulate_cp15_id_reg(vcpu, ¶ms);
2439 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs));
2442 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
2444 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
2447 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
2449 struct sys_reg_params params;
2451 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
2453 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs));
2456 static bool is_imp_def_sys_reg(struct sys_reg_params *params)
2458 // See ARM DDI 0487E.a, section D12.3.2
2459 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
2463 * emulate_sys_reg - Emulate a guest access to an AArch64 system register
2464 * @vcpu: The VCPU pointer
2465 * @params: Decoded system register parameters
2467 * Return: true if the system register access was successful, false otherwise.
2469 static bool emulate_sys_reg(struct kvm_vcpu *vcpu,
2470 struct sys_reg_params *params)
2472 const struct sys_reg_desc *r;
2474 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2477 perform_access(vcpu, params, r);
2481 if (is_imp_def_sys_reg(params)) {
2482 kvm_inject_undefined(vcpu);
2484 print_sys_reg_msg(params,
2485 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
2486 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2487 kvm_inject_undefined(vcpu);
2493 * kvm_reset_sys_regs - sets system registers to reset value
2494 * @vcpu: The VCPU pointer
2496 * This function finds the right table above and sets the registers on the
2497 * virtual CPU struct to their architecturally defined reset values.
2499 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2503 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++)
2504 if (sys_reg_descs[i].reset)
2505 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]);
2509 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2510 * @vcpu: The VCPU pointer
2512 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
2514 struct sys_reg_params params;
2515 unsigned long esr = kvm_vcpu_get_esr(vcpu);
2516 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2518 trace_kvm_handle_sys_reg(esr);
2520 params = esr_sys64_to_params(esr);
2521 params.regval = vcpu_get_reg(vcpu, Rt);
2523 if (!emulate_sys_reg(vcpu, ¶ms))
2526 if (!params.is_write)
2527 vcpu_set_reg(vcpu, Rt, params.regval);
2531 /******************************************************************************
2533 *****************************************************************************/
2535 static bool index_to_params(u64 id, struct sys_reg_params *params)
2537 switch (id & KVM_REG_SIZE_MASK) {
2538 case KVM_REG_SIZE_U64:
2539 /* Any unused index bits means it's not valid. */
2540 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2541 | KVM_REG_ARM_COPROC_MASK
2542 | KVM_REG_ARM64_SYSREG_OP0_MASK
2543 | KVM_REG_ARM64_SYSREG_OP1_MASK
2544 | KVM_REG_ARM64_SYSREG_CRN_MASK
2545 | KVM_REG_ARM64_SYSREG_CRM_MASK
2546 | KVM_REG_ARM64_SYSREG_OP2_MASK))
2548 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2549 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2550 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2551 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2552 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2553 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2554 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2555 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2556 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2557 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2564 const struct sys_reg_desc *get_reg_by_id(u64 id,
2565 const struct sys_reg_desc table[],
2568 struct sys_reg_params params;
2570 if (!index_to_params(id, ¶ms))
2573 return find_reg(¶ms, table, num);
2576 /* Decode an index value, and find the sys_reg_desc entry. */
2577 static const struct sys_reg_desc *
2578 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id,
2579 const struct sys_reg_desc table[], unsigned int num)
2582 const struct sys_reg_desc *r;
2584 /* We only do sys_reg for now. */
2585 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2588 r = get_reg_by_id(id, table, num);
2590 /* Not saved in the sys_reg array and not otherwise accessible? */
2591 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r)))
2598 * These are the invariant sys_reg registers: we let the guest see the
2599 * host versions of these, so they're part of the guest state.
2601 * A future CPU may provide a mechanism to present different values to
2602 * the guest, or a future kvm may trap them.
2605 #define FUNCTION_INVARIANT(reg) \
2606 static void get_##reg(struct kvm_vcpu *v, \
2607 const struct sys_reg_desc *r) \
2609 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
2612 FUNCTION_INVARIANT(midr_el1)
2613 FUNCTION_INVARIANT(revidr_el1)
2614 FUNCTION_INVARIANT(clidr_el1)
2615 FUNCTION_INVARIANT(aidr_el1)
2617 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2619 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2622 /* ->val is filled in by kvm_sys_reg_table_init() */
2623 static struct sys_reg_desc invariant_sys_regs[] = {
2624 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2625 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
2626 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2627 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2628 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
2631 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr)
2633 const struct sys_reg_desc *r;
2635 r = get_reg_by_id(id, invariant_sys_regs,
2636 ARRAY_SIZE(invariant_sys_regs));
2640 return put_user(r->val, uaddr);
2643 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr)
2645 const struct sys_reg_desc *r;
2648 r = get_reg_by_id(id, invariant_sys_regs,
2649 ARRAY_SIZE(invariant_sys_regs));
2653 if (get_user(val, uaddr))
2656 /* This is what we mean by invariant: you can't change it. */
2663 static bool is_valid_cache(u32 val)
2667 if (val >= CSSELR_MAX)
2670 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2672 ctype = (cache_levels >> (level * 3)) & 7;
2675 case 0: /* No cache */
2677 case 1: /* Instruction cache only */
2679 case 2: /* Data cache only */
2680 case 4: /* Unified cache */
2682 case 3: /* Separate instruction and data caches */
2684 default: /* Reserved: we can't know instruction or data. */
2689 static int demux_c15_get(u64 id, void __user *uaddr)
2692 u32 __user *uval = uaddr;
2694 /* Fail if we have unknown bits set. */
2695 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2696 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2699 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2700 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2701 if (KVM_REG_SIZE(id) != 4)
2703 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2704 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2705 if (!is_valid_cache(val))
2708 return put_user(get_ccsidr(val), uval);
2714 static int demux_c15_set(u64 id, void __user *uaddr)
2717 u32 __user *uval = uaddr;
2719 /* Fail if we have unknown bits set. */
2720 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2721 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2724 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2725 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2726 if (KVM_REG_SIZE(id) != 4)
2728 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2729 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2730 if (!is_valid_cache(val))
2733 if (get_user(newval, uval))
2736 /* This is also invariant: you can't change it. */
2737 if (newval != get_ccsidr(val))
2745 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
2746 const struct sys_reg_desc table[], unsigned int num)
2748 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
2749 const struct sys_reg_desc *r;
2753 r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
2758 ret = (r->get_user)(vcpu, r, &val);
2760 val = __vcpu_sys_reg(vcpu, r->reg);
2765 ret = put_user(val, uaddr);
2770 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2772 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2775 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2776 return demux_c15_get(reg->id, uaddr);
2778 err = get_invariant_sys_reg(reg->id, uaddr);
2782 return kvm_sys_reg_get_user(vcpu, reg,
2783 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2786 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
2787 const struct sys_reg_desc table[], unsigned int num)
2789 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
2790 const struct sys_reg_desc *r;
2794 if (get_user(val, uaddr))
2797 r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
2801 if (sysreg_user_write_ignore(vcpu, r))
2805 ret = (r->set_user)(vcpu, r, val);
2807 __vcpu_sys_reg(vcpu, r->reg) = val;
2814 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2816 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2819 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2820 return demux_c15_set(reg->id, uaddr);
2822 err = set_invariant_sys_reg(reg->id, uaddr);
2826 return kvm_sys_reg_set_user(vcpu, reg,
2827 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2830 static unsigned int num_demux_regs(void)
2832 unsigned int i, count = 0;
2834 for (i = 0; i < CSSELR_MAX; i++)
2835 if (is_valid_cache(i))
2841 static int write_demux_regids(u64 __user *uindices)
2843 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2846 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2847 for (i = 0; i < CSSELR_MAX; i++) {
2848 if (!is_valid_cache(i))
2850 if (put_user(val | i, uindices))
2857 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2859 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2860 KVM_REG_ARM64_SYSREG |
2861 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2862 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2863 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2864 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2865 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2868 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2873 if (put_user(sys_reg_to_index(reg), *uind))
2880 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2881 const struct sys_reg_desc *rd,
2883 unsigned int *total)
2886 * Ignore registers we trap but don't save,
2887 * and for which no custom user accessor is provided.
2889 if (!(rd->reg || rd->get_user))
2892 if (sysreg_hidden(vcpu, rd))
2895 if (!copy_reg_to_user(rd, uind))
2902 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2903 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2905 const struct sys_reg_desc *i2, *end2;
2906 unsigned int total = 0;
2910 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2912 while (i2 != end2) {
2913 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
2920 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2922 return ARRAY_SIZE(invariant_sys_regs)
2924 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2927 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2932 /* Then give them all the invariant registers' indices. */
2933 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2934 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2939 err = walk_sys_regs(vcpu, uindices);
2944 return write_demux_regids(uindices);
2947 int kvm_sys_reg_table_init(void)
2951 struct sys_reg_desc clidr;
2953 /* Make sure tables are unique and in order. */
2954 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false);
2955 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true);
2956 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true);
2957 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true);
2958 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true);
2959 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false);
2964 /* We abuse the reset function to overwrite the table itself. */
2965 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2966 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2969 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2971 * If software reads the Cache Type fields from Ctype1
2972 * upwards, once it has seen a value of 0b000, no caches
2973 * exist at further-out levels of the hierarchy. So, for
2974 * example, if Ctype3 is the first Cache Type field with a
2975 * value of 0b000, the values of Ctype4 to Ctype7 must be
2978 get_clidr_el1(NULL, &clidr); /* Ugly... */
2979 cache_levels = clidr.val;
2980 for (i = 0; i < 7; i++)
2981 if (((cache_levels >> (i*3)) & 7) == 0)
2983 /* Clear all higher bits. */
2984 cache_levels &= (1 << (i*3))-1;