arch/arm64/kvm/sys_regs.c

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Derived from arch/arm/kvm/coproc.c:
   6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   7  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   8  *          Christoffer Dall <c.dall@virtualopensystems.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License, version 2, as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/bsearch.h>
  24 #include <linux/kvm_host.h>
  25 #include <linux/mm.h>
  26 #include <linux/printk.h>
  27 #include <linux/uaccess.h>
  28
  29 #include <asm/cacheflush.h>
  30 #include <asm/cputype.h>
  31 #include <asm/debug-monitors.h>
  32 #include <asm/esr.h>
  33 #include <asm/kvm_arm.h>
  34 #include <asm/kvm_coproc.h>
  35 #include <asm/kvm_emulate.h>
  36 #include <asm/kvm_host.h>
  37 #include <asm/kvm_hyp.h>
  38 #include <asm/kvm_mmu.h>
  39 #include <asm/perf_event.h>
  40 #include <asm/sysreg.h>
  41
  42 #include <trace/events/kvm.h>
  43
  44 #include "sys_regs.h"
  45
  46 #include "trace.h"
  47
  48 /*
  49  * All of this file is extremly similar to the ARM coproc.c, but the
  50  * types are different. My gut feeling is that it should be pretty
  51  * easy to merge, but that would be an ABI breakage -- again. VFP
  52  * would also need to be abstracted.
  53  *
  54  * For AArch32, we only take care of what is being trapped. Anything
  55  * that has to do with init and userspace access has to go via the
  56  * 64bit interface.
  57  */
  58
  59 static bool read_from_write_only(struct kvm_vcpu *vcpu,
  60                                  struct sys_reg_params *params,
  61                                  const struct sys_reg_desc *r)
  62 {
  63         WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
  64         print_sys_reg_instr(params);
  65         kvm_inject_undefined(vcpu);
  66         return false;
  67 }
  68
  69 static bool write_to_read_only(struct kvm_vcpu *vcpu,
  70                                struct sys_reg_params *params,
  71                                const struct sys_reg_desc *r)
  72 {
  73         WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
  74         print_sys_reg_instr(params);
  75         kvm_inject_undefined(vcpu);
  76         return false;
  77 }
  78
  79 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
  80 {
  81         if (!vcpu->arch.sysregs_loaded_on_cpu)
  82                 goto immediate_read;
  83
  84         /*
  85          * System registers listed in the switch are not saved on every
  86          * exit from the guest but are only saved on vcpu_put.
  87          *
  88          * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
  89          * should never be listed below, because the guest cannot modify its
  90          * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
  91          * thread when emulating cross-VCPU communication.
  92          */
  93         switch (reg) {
  94         case CSSELR_EL1:        return read_sysreg_s(SYS_CSSELR_EL1);
  95         case SCTLR_EL1:         return read_sysreg_s(sctlr_EL12);
  96         case ACTLR_EL1:         return read_sysreg_s(SYS_ACTLR_EL1);
  97         case CPACR_EL1:         return read_sysreg_s(cpacr_EL12);
  98         case TTBR0_EL1:         return read_sysreg_s(ttbr0_EL12);
  99         case TTBR1_EL1:         return read_sysreg_s(ttbr1_EL12);
 100         case TCR_EL1:           return read_sysreg_s(tcr_EL12);
 101         case ESR_EL1:           return read_sysreg_s(esr_EL12);
 102         case AFSR0_EL1:         return read_sysreg_s(afsr0_EL12);
 103         case AFSR1_EL1:         return read_sysreg_s(afsr1_EL12);
 104         case FAR_EL1:           return read_sysreg_s(far_EL12);
 105         case MAIR_EL1:          return read_sysreg_s(mair_EL12);
 106         case VBAR_EL1:          return read_sysreg_s(vbar_EL12);
 107         case CONTEXTIDR_EL1:    return read_sysreg_s(contextidr_EL12);
 108         case TPIDR_EL0:         return read_sysreg_s(SYS_TPIDR_EL0);
 109         case TPIDRRO_EL0:       return read_sysreg_s(SYS_TPIDRRO_EL0);
 110         case TPIDR_EL1:         return read_sysreg_s(SYS_TPIDR_EL1);
 111         case AMAIR_EL1:         return read_sysreg_s(amair_EL12);
 112         case CNTKCTL_EL1:       return read_sysreg_s(cntkctl_EL12);
 113         case PAR_EL1:           return read_sysreg_s(SYS_PAR_EL1);
 114         case DACR32_EL2:        return read_sysreg_s(SYS_DACR32_EL2);
 115         case IFSR32_EL2:        return read_sysreg_s(SYS_IFSR32_EL2);
 116         case DBGVCR32_EL2:      return read_sysreg_s(SYS_DBGVCR32_EL2);
 117         }
 118
 119 immediate_read:
 120         return __vcpu_sys_reg(vcpu, reg);
 121 }
 122
 123 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
 124 {
 125         if (!vcpu->arch.sysregs_loaded_on_cpu)
 126                 goto immediate_write;
 127
 128         /*
 129          * System registers listed in the switch are not restored on every
 130          * entry to the guest but are only restored on vcpu_load.
 131          *
 132          * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
 133          * should never be listed below, because the the MPIDR should only be
 134          * set once, before running the VCPU, and never changed later.
 135          */
 136         switch (reg) {
 137         case CSSELR_EL1:        write_sysreg_s(val, SYS_CSSELR_EL1);    return;
 138         case SCTLR_EL1:         write_sysreg_s(val, sctlr_EL12);        return;
 139         case ACTLR_EL1:         write_sysreg_s(val, SYS_ACTLR_EL1);     return;
 140         case CPACR_EL1:         write_sysreg_s(val, cpacr_EL12);        return;
 141         case TTBR0_EL1:         write_sysreg_s(val, ttbr0_EL12);        return;
 142         case TTBR1_EL1:         write_sysreg_s(val, ttbr1_EL12);        return;
 143         case TCR_EL1:           write_sysreg_s(val, tcr_EL12);          return;
 144         case ESR_EL1:           write_sysreg_s(val, esr_EL12);          return;
 145         case AFSR0_EL1:         write_sysreg_s(val, afsr0_EL12);        return;
 146         case AFSR1_EL1:         write_sysreg_s(val, afsr1_EL12);        return;
 147         case FAR_EL1:           write_sysreg_s(val, far_EL12);          return;
 148         case MAIR_EL1:          write_sysreg_s(val, mair_EL12);         return;
 149         case VBAR_EL1:          write_sysreg_s(val, vbar_EL12);         return;
 150         case CONTEXTIDR_EL1:    write_sysreg_s(val, contextidr_EL12);   return;
 151         case TPIDR_EL0:         write_sysreg_s(val, SYS_TPIDR_EL0);     return;
 152         case TPIDRRO_EL0:       write_sysreg_s(val, SYS_TPIDRRO_EL0);   return;
 153         case TPIDR_EL1:         write_sysreg_s(val, SYS_TPIDR_EL1);     return;
 154         case AMAIR_EL1:         write_sysreg_s(val, amair_EL12);        return;
 155         case CNTKCTL_EL1:       write_sysreg_s(val, cntkctl_EL12);      return;
 156         case PAR_EL1:           write_sysreg_s(val, SYS_PAR_EL1);       return;
 157         case DACR32_EL2:        write_sysreg_s(val, SYS_DACR32_EL2);    return;
 158         case IFSR32_EL2:        write_sysreg_s(val, SYS_IFSR32_EL2);    return;
 159         case DBGVCR32_EL2:      write_sysreg_s(val, SYS_DBGVCR32_EL2);  return;
 160         }
 161
 162 immediate_write:
 163          __vcpu_sys_reg(vcpu, reg) = val;
 164 }
 165
 166 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
 167 static u32 cache_levels;
 168
 169 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
 170 #define CSSELR_MAX 12
 171
 172 /* Which cache CCSIDR represents depends on CSSELR value. */
 173 static u32 get_ccsidr(u32 csselr)
 174 {
 175         u32 ccsidr;
 176
 177         /* Make sure noone else changes CSSELR during this! */
 178         local_irq_disable();
 179         write_sysreg(csselr, csselr_el1);
 180         isb();
 181         ccsidr = read_sysreg(ccsidr_el1);
 182         local_irq_enable();
 183
 184         return ccsidr;
 185 }
 186
 187 /*
 188  * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
 189  */
 190 static bool access_dcsw(struct kvm_vcpu *vcpu,
 191                         struct sys_reg_params *p,
 192                         const struct sys_reg_desc *r)
 193 {
 194         if (!p->is_write)
 195                 return read_from_write_only(vcpu, p, r);
 196
 197         /*
 198          * Only track S/W ops if we don't have FWB. It still indicates
 199          * that the guest is a bit broken (S/W operations should only
 200          * be done by firmware, knowing that there is only a single
 201          * CPU left in the system, and certainly not from non-secure
 202          * software).
 203          */
 204         if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
 205                 kvm_set_way_flush(vcpu);
 206
 207         return true;
 208 }
 209
 210 /*
 211  * Generic accessor for VM registers. Only called as long as HCR_TVM
 212  * is set. If the guest enables the MMU, we stop trapping the VM
 213  * sys_regs and leave it in complete control of the caches.
 214  */
 215 static bool access_vm_reg(struct kvm_vcpu *vcpu,
 216                           struct sys_reg_params *p,
 217                           const struct sys_reg_desc *r)
 218 {
 219         bool was_enabled = vcpu_has_cache_enabled(vcpu);
 220         u64 val;
 221         int reg = r->reg;
 222
 223         BUG_ON(!p->is_write);
 224
 225         /* See the 32bit mapping in kvm_host.h */
 226         if (p->is_aarch32)
 227                 reg = r->reg / 2;
 228
 229         if (!p->is_aarch32 || !p->is_32bit) {
 230                 val = p->regval;
 231         } else {
 232                 val = vcpu_read_sys_reg(vcpu, reg);
 233                 if (r->reg % 2)
 234                         val = (p->regval << 32) | (u64)lower_32_bits(val);
 235                 else
 236                         val = ((u64)upper_32_bits(val) << 32) |
 237                                 lower_32_bits(p->regval);
 238         }
 239         vcpu_write_sys_reg(vcpu, val, reg);
 240
 241         kvm_toggle_cache(vcpu, was_enabled);
 242         return true;
 243 }
 244
 245 /*
 246  * Trap handler for the GICv3 SGI generation system register.
 247  * Forward the request to the VGIC emulation.
 248  * The cp15_64 code makes sure this automatically works
 249  * for both AArch64 and AArch32 accesses.
 250  */
 251 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
 252                            struct sys_reg_params *p,
 253                            const struct sys_reg_desc *r)
 254 {
 255         bool g1;
 256
 257         if (!p->is_write)
 258                 return read_from_write_only(vcpu, p, r);
 259
 260         /*
 261          * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
 262          * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
 263          * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
 264          * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
 265          * group.
 266          */
 267         if (p->is_aarch32) {
 268                 switch (p->Op1) {
 269                 default:                /* Keep GCC quiet */
 270                 case 0:                 /* ICC_SGI1R */
 271                         g1 = true;
 272                         break;
 273                 case 1:                 /* ICC_ASGI1R */
 274                 case 2:                 /* ICC_SGI0R */
 275                         g1 = false;
 276                         break;
 277                 }
 278         } else {
 279                 switch (p->Op2) {
 280                 default:                /* Keep GCC quiet */
 281                 case 5:                 /* ICC_SGI1R_EL1 */
 282                         g1 = true;
 283                         break;
 284                 case 6:                 /* ICC_ASGI1R_EL1 */
 285                 case 7:                 /* ICC_SGI0R_EL1 */
 286                         g1 = false;
 287                         break;
 288                 }
 289         }
 290
 291         vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
 292
 293         return true;
 294 }
 295
 296 static bool access_gic_sre(struct kvm_vcpu *vcpu,
 297                            struct sys_reg_params *p,
 298                            const struct sys_reg_desc *r)
 299 {
 300         if (p->is_write)
 301                 return ignore_write(vcpu, p);
 302
 303         p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
 304         return true;
 305 }
 306
 307 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
 308                         struct sys_reg_params *p,
 309                         const struct sys_reg_desc *r)
 310 {
 311         if (p->is_write)
 312                 return ignore_write(vcpu, p);
 313         else
 314                 return read_zero(vcpu, p);
 315 }
 316
 317 /*
 318  * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
 319  * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
 320  * system, these registers should UNDEF. LORID_EL1 being a RO register, we
 321  * treat it separately.
 322  */
 323 static bool trap_loregion(struct kvm_vcpu *vcpu,
 324                           struct sys_reg_params *p,
 325                           const struct sys_reg_desc *r)
 326 {
 327         u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
 328         u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1,
 329                          (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
 330
 331         if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
 332                 kvm_inject_undefined(vcpu);
 333                 return false;
 334         }
 335
 336         if (p->is_write && sr == SYS_LORID_EL1)
 337                 return write_to_read_only(vcpu, p, r);
 338
 339         return trap_raz_wi(vcpu, p, r);
 340 }
 341
 342 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
 343                            struct sys_reg_params *p,
 344                            const struct sys_reg_desc *r)
 345 {
 346         if (p->is_write) {
 347                 return ignore_write(vcpu, p);
 348         } else {
 349                 p->regval = (1 << 3);
 350                 return true;
 351         }
 352 }
 353
 354 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
 355                                    struct sys_reg_params *p,
 356                                    const struct sys_reg_desc *r)
 357 {
 358         if (p->is_write) {
 359                 return ignore_write(vcpu, p);
 360         } else {
 361                 p->regval = read_sysreg(dbgauthstatus_el1);
 362                 return true;
 363         }
 364 }
 365
 366 /*
 367  * We want to avoid world-switching all the DBG registers all the
 368  * time:
 369  *
 370  * - If we've touched any debug register, it is likely that we're
 371  *   going to touch more of them. It then makes sense to disable the
 372  *   traps and start doing the save/restore dance
 373  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
 374  *   then mandatory to save/restore the registers, as the guest
 375  *   depends on them.
 376  *
 377  * For this, we use a DIRTY bit, indicating the guest has modified the
 378  * debug registers, used as follow:
 379  *
 380  * On guest entry:
 381  * - If the dirty bit is set (because we're coming back from trapping),
 382  *   disable the traps, save host registers, restore guest registers.
 383  * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
 384  *   set the dirty bit, disable the traps, save host registers,
 385  *   restore guest registers.
 386  * - Otherwise, enable the traps
 387  *
 388  * On guest exit:
 389  * - If the dirty bit is set, save guest registers, restore host
 390  *   registers and clear the dirty bit. This ensure that the host can
 391  *   now use the debug registers.
 392  */
 393 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
 394                             struct sys_reg_params *p,
 395                             const struct sys_reg_desc *r)
 396 {
 397         if (p->is_write) {
 398                 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
 399                 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
 400         } else {
 401                 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
 402         }
 403
 404         trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
 405
 406         return true;
 407 }
 408
 409 /*
 410  * reg_to_dbg/dbg_to_reg
 411  *
 412  * A 32 bit write to a debug register leave top bits alone
 413  * A 32 bit read from a debug register only returns the bottom bits
 414  *
 415  * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
 416  * hyp.S code switches between host and guest values in future.
 417  */
 418 static void reg_to_dbg(struct kvm_vcpu *vcpu,
 419                        struct sys_reg_params *p,
 420                        u64 *dbg_reg)
 421 {
 422         u64 val = p->regval;
 423
 424         if (p->is_32bit) {
 425                 val &= 0xffffffffUL;
 426                 val |= ((*dbg_reg >> 32) << 32);
 427         }
 428
 429         *dbg_reg = val;
 430         vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
 431 }
 432
 433 static void dbg_to_reg(struct kvm_vcpu *vcpu,
 434                        struct sys_reg_params *p,
 435                        u64 *dbg_reg)
 436 {
 437         p->regval = *dbg_reg;
 438         if (p->is_32bit)
 439                 p->regval &= 0xffffffffUL;
 440 }
 441
 442 static bool trap_bvr(struct kvm_vcpu *vcpu,
 443                      struct sys_reg_params *p,
 444                      const struct sys_reg_desc *rd)
 445 {
 446         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 447
 448         if (p->is_write)
 449                 reg_to_dbg(vcpu, p, dbg_reg);
 450         else
 451                 dbg_to_reg(vcpu, p, dbg_reg);
 452
 453         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 454
 455         return true;
 456 }
 457
 458 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 459                 const struct kvm_one_reg *reg, void __user *uaddr)
 460 {
 461         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 462
 463         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 464                 return -EFAULT;
 465         return 0;
 466 }
 467
 468 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 469         const struct kvm_one_reg *reg, void __user *uaddr)
 470 {
 471         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 472
 473         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 474                 return -EFAULT;
 475         return 0;
 476 }
 477
 478 static void reset_bvr(struct kvm_vcpu *vcpu,
 479                       const struct sys_reg_desc *rd)
 480 {
 481         vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
 482 }
 483
 484 static bool trap_bcr(struct kvm_vcpu *vcpu,
 485                      struct sys_reg_params *p,
 486                      const struct sys_reg_desc *rd)
 487 {
 488         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 489
 490         if (p->is_write)
 491                 reg_to_dbg(vcpu, p, dbg_reg);
 492         else
 493                 dbg_to_reg(vcpu, p, dbg_reg);
 494
 495         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 496
 497         return true;
 498 }
 499
 500 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 501                 const struct kvm_one_reg *reg, void __user *uaddr)
 502 {
 503         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 504
 505         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 506                 return -EFAULT;
 507
 508         return 0;
 509 }
 510
 511 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 512         const struct kvm_one_reg *reg, void __user *uaddr)
 513 {
 514         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 515
 516         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 517                 return -EFAULT;
 518         return 0;
 519 }
 520
 521 static void reset_bcr(struct kvm_vcpu *vcpu,
 522                       const struct sys_reg_desc *rd)
 523 {
 524         vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
 525 }
 526
 527 static bool trap_wvr(struct kvm_vcpu *vcpu,
 528                      struct sys_reg_params *p,
 529                      const struct sys_reg_desc *rd)
 530 {
 531         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 532
 533         if (p->is_write)
 534                 reg_to_dbg(vcpu, p, dbg_reg);
 535         else
 536                 dbg_to_reg(vcpu, p, dbg_reg);
 537
 538         trace_trap_reg(__func__, rd->reg, p->is_write,
 539                 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
 540
 541         return true;
 542 }
 543
 544 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 545                 const struct kvm_one_reg *reg, void __user *uaddr)
 546 {
 547         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 548
 549         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 550                 return -EFAULT;
 551         return 0;
 552 }
 553
 554 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 555         const struct kvm_one_reg *reg, void __user *uaddr)
 556 {
 557         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 558
 559         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 560                 return -EFAULT;
 561         return 0;
 562 }
 563
 564 static void reset_wvr(struct kvm_vcpu *vcpu,
 565                       const struct sys_reg_desc *rd)
 566 {
 567         vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
 568 }
 569
 570 static bool trap_wcr(struct kvm_vcpu *vcpu,
 571                      struct sys_reg_params *p,
 572                      const struct sys_reg_desc *rd)
 573 {
 574         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 575
 576         if (p->is_write)
 577                 reg_to_dbg(vcpu, p, dbg_reg);
 578         else
 579                 dbg_to_reg(vcpu, p, dbg_reg);
 580
 581         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 582
 583         return true;
 584 }
 585
 586 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 587                 const struct kvm_one_reg *reg, void __user *uaddr)
 588 {
 589         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 590
 591         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 592                 return -EFAULT;
 593         return 0;
 594 }
 595
 596 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 597         const struct kvm_one_reg *reg, void __user *uaddr)
 598 {
 599         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 600
 601         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 602                 return -EFAULT;
 603         return 0;
 604 }
 605
 606 static void reset_wcr(struct kvm_vcpu *vcpu,
 607                       const struct sys_reg_desc *rd)
 608 {
 609         vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
 610 }
 611
 612 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 613 {
 614         u64 amair = read_sysreg(amair_el1);
 615         vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
 616 }
 617
 618 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 619 {
 620         u64 mpidr;
 621
 622         /*
 623          * Map the vcpu_id into the first three affinity level fields of
 624          * the MPIDR. We limit the number of VCPUs in level 0 due to a
 625          * limitation to 16 CPUs in that level in the ICC_SGIxR registers
 626          * of the GICv3 to be able to address each CPU directly when
 627          * sending IPIs.
 628          */
 629         mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
 630         mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
 631         mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
 632         vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
 633 }
 634
 635 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 636 {
 637         u64 pmcr, val;
 638
 639         pmcr = read_sysreg(pmcr_el0);
 640         /*
 641          * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
 642          * except PMCR.E resetting to zero.
 643          */
 644         val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
 645                | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
 646         __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
 647 }
 648
 649 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
 650 {
 651         u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 652         bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
 653
 654         if (!enabled)
 655                 kvm_inject_undefined(vcpu);
 656
 657         return !enabled;
 658 }
 659
 660 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
 661 {
 662         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
 663 }
 664
 665 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
 666 {
 667         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
 668 }
 669
 670 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
 671 {
 672         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
 673 }
 674
 675 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
 676 {
 677         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
 678 }
 679
 680 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 681                         const struct sys_reg_desc *r)
 682 {
 683         u64 val;
 684
 685         if (!kvm_arm_pmu_v3_ready(vcpu))
 686                 return trap_raz_wi(vcpu, p, r);
 687
 688         if (pmu_access_el0_disabled(vcpu))
 689                 return false;
 690
 691         if (p->is_write) {
 692                 /* Only update writeable bits of PMCR */
 693                 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
 694                 val &= ~ARMV8_PMU_PMCR_MASK;
 695                 val |= p->regval & ARMV8_PMU_PMCR_MASK;
 696                 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
 697                 kvm_pmu_handle_pmcr(vcpu, val);
 698         } else {
 699                 /* PMCR.P & PMCR.C are RAZ */
 700                 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
 701                       & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
 702                 p->regval = val;
 703         }
 704
 705         return true;
 706 }
 707
 708 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 709                           const struct sys_reg_desc *r)
 710 {
 711         if (!kvm_arm_pmu_v3_ready(vcpu))
 712                 return trap_raz_wi(vcpu, p, r);
 713
 714         if (pmu_access_event_counter_el0_disabled(vcpu))
 715                 return false;
 716
 717         if (p->is_write)
 718                 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
 719         else
 720                 /* return PMSELR.SEL field */
 721                 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
 722                             & ARMV8_PMU_COUNTER_MASK;
 723
 724         return true;
 725 }
 726
 727 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 728                           const struct sys_reg_desc *r)
 729 {
 730         u64 pmceid;
 731
 732         if (!kvm_arm_pmu_v3_ready(vcpu))
 733                 return trap_raz_wi(vcpu, p, r);
 734
 735         BUG_ON(p->is_write);
 736
 737         if (pmu_access_el0_disabled(vcpu))
 738                 return false;
 739
 740         if (!(p->Op2 & 1))
 741                 pmceid = read_sysreg(pmceid0_el0);
 742         else
 743                 pmceid = read_sysreg(pmceid1_el0);
 744
 745         p->regval = pmceid;
 746
 747         return true;
 748 }
 749
 750 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
 751 {
 752         u64 pmcr, val;
 753
 754         pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
 755         val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
 756         if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
 757                 kvm_inject_undefined(vcpu);
 758                 return false;
 759         }
 760
 761         return true;
 762 }
 763
 764 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
 765                               struct sys_reg_params *p,
 766                               const struct sys_reg_desc *r)
 767 {
 768         u64 idx;
 769
 770         if (!kvm_arm_pmu_v3_ready(vcpu))
 771                 return trap_raz_wi(vcpu, p, r);
 772
 773         if (r->CRn == 9 && r->CRm == 13) {
 774                 if (r->Op2 == 2) {
 775                         /* PMXEVCNTR_EL0 */
 776                         if (pmu_access_event_counter_el0_disabled(vcpu))
 777                                 return false;
 778
 779                         idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
 780                               & ARMV8_PMU_COUNTER_MASK;
 781                 } else if (r->Op2 == 0) {
 782                         /* PMCCNTR_EL0 */
 783                         if (pmu_access_cycle_counter_el0_disabled(vcpu))
 784                                 return false;
 785
 786                         idx = ARMV8_PMU_CYCLE_IDX;
 787                 } else {
 788                         return false;
 789                 }
 790         } else if (r->CRn == 0 && r->CRm == 9) {
 791                 /* PMCCNTR */
 792                 if (pmu_access_event_counter_el0_disabled(vcpu))
 793                         return false;
 794
 795                 idx = ARMV8_PMU_CYCLE_IDX;
 796         } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
 797                 /* PMEVCNTRn_EL0 */
 798                 if (pmu_access_event_counter_el0_disabled(vcpu))
 799                         return false;
 800
 801                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 802         } else {
 803                 return false;
 804         }
 805
 806         if (!pmu_counter_idx_valid(vcpu, idx))
 807                 return false;
 808
 809         if (p->is_write) {
 810                 if (pmu_access_el0_disabled(vcpu))
 811                         return false;
 812
 813                 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
 814         } else {
 815                 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
 816         }
 817
 818         return true;
 819 }
 820
 821 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 822                                const struct sys_reg_desc *r)
 823 {
 824         u64 idx, reg;
 825
 826         if (!kvm_arm_pmu_v3_ready(vcpu))
 827                 return trap_raz_wi(vcpu, p, r);
 828
 829         if (pmu_access_el0_disabled(vcpu))
 830                 return false;
 831
 832         if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
 833                 /* PMXEVTYPER_EL0 */
 834                 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
 835                 reg = PMEVTYPER0_EL0 + idx;
 836         } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
 837                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 838                 if (idx == ARMV8_PMU_CYCLE_IDX)
 839                         reg = PMCCFILTR_EL0;
 840                 else
 841                         /* PMEVTYPERn_EL0 */
 842                         reg = PMEVTYPER0_EL0 + idx;
 843         } else {
 844                 BUG();
 845         }
 846
 847         if (!pmu_counter_idx_valid(vcpu, idx))
 848                 return false;
 849
 850         if (p->is_write) {
 851                 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
 852                 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
 853         } else {
 854                 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
 855         }
 856
 857         return true;
 858 }
 859
 860 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 861                            const struct sys_reg_desc *r)
 862 {
 863         u64 val, mask;
 864
 865         if (!kvm_arm_pmu_v3_ready(vcpu))
 866                 return trap_raz_wi(vcpu, p, r);
 867
 868         if (pmu_access_el0_disabled(vcpu))
 869                 return false;
 870
 871         mask = kvm_pmu_valid_counter_mask(vcpu);
 872         if (p->is_write) {
 873                 val = p->regval & mask;
 874                 if (r->Op2 & 0x1) {
 875                         /* accessing PMCNTENSET_EL0 */
 876                         __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
 877                         kvm_pmu_enable_counter(vcpu, val);
 878                 } else {
 879                         /* accessing PMCNTENCLR_EL0 */
 880                         __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
 881                         kvm_pmu_disable_counter(vcpu, val);
 882                 }
 883         } else {
 884                 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
 885         }
 886
 887         return true;
 888 }
 889
 890 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 891                            const struct sys_reg_desc *r)
 892 {
 893         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 894
 895         if (!kvm_arm_pmu_v3_ready(vcpu))
 896                 return trap_raz_wi(vcpu, p, r);
 897
 898         if (!vcpu_mode_priv(vcpu)) {
 899                 kvm_inject_undefined(vcpu);
 900                 return false;
 901         }
 902
 903         if (p->is_write) {
 904                 u64 val = p->regval & mask;
 905
 906                 if (r->Op2 & 0x1)
 907                         /* accessing PMINTENSET_EL1 */
 908                         __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
 909                 else
 910                         /* accessing PMINTENCLR_EL1 */
 911                         __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
 912         } else {
 913                 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
 914         }
 915
 916         return true;
 917 }
 918
 919 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 920                          const struct sys_reg_desc *r)
 921 {
 922         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 923
 924         if (!kvm_arm_pmu_v3_ready(vcpu))
 925                 return trap_raz_wi(vcpu, p, r);
 926
 927         if (pmu_access_el0_disabled(vcpu))
 928                 return false;
 929
 930         if (p->is_write) {
 931                 if (r->CRm & 0x2)
 932                         /* accessing PMOVSSET_EL0 */
 933                         __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
 934                 else
 935                         /* accessing PMOVSCLR_EL0 */
 936                         __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
 937         } else {
 938                 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
 939         }
 940
 941         return true;
 942 }
 943
 944 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 945                            const struct sys_reg_desc *r)
 946 {
 947         u64 mask;
 948
 949         if (!kvm_arm_pmu_v3_ready(vcpu))
 950                 return trap_raz_wi(vcpu, p, r);
 951
 952         if (!p->is_write)
 953                 return read_from_write_only(vcpu, p, r);
 954
 955         if (pmu_write_swinc_el0_disabled(vcpu))
 956                 return false;
 957
 958         mask = kvm_pmu_valid_counter_mask(vcpu);
 959         kvm_pmu_software_increment(vcpu, p->regval & mask);
 960         return true;
 961 }
 962
 963 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 964                              const struct sys_reg_desc *r)
 965 {
 966         if (!kvm_arm_pmu_v3_ready(vcpu))
 967                 return trap_raz_wi(vcpu, p, r);
 968
 969         if (p->is_write) {
 970                 if (!vcpu_mode_priv(vcpu)) {
 971                         kvm_inject_undefined(vcpu);
 972                         return false;
 973                 }
 974
 975                 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
 976                                p->regval & ARMV8_PMU_USERENR_MASK;
 977         } else {
 978                 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
 979                             & ARMV8_PMU_USERENR_MASK;
 980         }
 981
 982         return true;
 983 }
 984
 985 #define reg_to_encoding(x)                                              \
 986         sys_reg((u32)(x)->Op0, (u32)(x)->Op1,                           \
 987                 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2);
 988
 989 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 990 #define DBG_BCR_BVR_WCR_WVR_EL1(n)                                      \
 991         { SYS_DESC(SYS_DBGBVRn_EL1(n)),                                 \
 992           trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr },                \
 993         { SYS_DESC(SYS_DBGBCRn_EL1(n)),                                 \
 994           trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr },                \
 995         { SYS_DESC(SYS_DBGWVRn_EL1(n)),                                 \
 996           trap_wvr, reset_wvr, n, 0,  get_wvr, set_wvr },               \
 997         { SYS_DESC(SYS_DBGWCRn_EL1(n)),                                 \
 998           trap_wcr, reset_wcr, n, 0,  get_wcr, set_wcr }
 999
1000 /* Macro to expand the PMEVCNTRn_EL0 register */
1001 #define PMU_PMEVCNTR_EL0(n)                                             \
1002         { SYS_DESC(SYS_PMEVCNTRn_EL0(n)),                                       \
1003           access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
1004
1005 /* Macro to expand the PMEVTYPERn_EL0 register */
1006 #define PMU_PMEVTYPER_EL0(n)                                            \
1007         { SYS_DESC(SYS_PMEVTYPERn_EL0(n)),                                      \
1008           access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
1009
1010 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1011                               struct sys_reg_params *p,
1012                               const struct sys_reg_desc *r)
1013 {
1014         enum kvm_arch_timers tmr;
1015         enum kvm_arch_timer_regs treg;
1016         u64 reg = reg_to_encoding(r);
1017
1018         switch (reg) {
1019         case SYS_CNTP_TVAL_EL0:
1020         case SYS_AARCH32_CNTP_TVAL:
1021                 tmr = TIMER_PTIMER;
1022                 treg = TIMER_REG_TVAL;
1023                 break;
1024         case SYS_CNTP_CTL_EL0:
1025         case SYS_AARCH32_CNTP_CTL:
1026                 tmr = TIMER_PTIMER;
1027                 treg = TIMER_REG_CTL;
1028                 break;
1029         case SYS_CNTP_CVAL_EL0:
1030         case SYS_AARCH32_CNTP_CVAL:
1031                 tmr = TIMER_PTIMER;
1032                 treg = TIMER_REG_CVAL;
1033                 break;
1034         default:
1035                 BUG();
1036         }
1037
1038         if (p->is_write)
1039                 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1040         else
1041                 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1042
1043         return true;
1044 }
1045
1046 /* Read a sanitised cpufeature ID register by sys_reg_desc */
1047 static u64 read_id_reg(struct sys_reg_desc const *r, bool raz)
1048 {
1049         u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
1050                          (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
1051         u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
1052
1053         if (id == SYS_ID_AA64PFR0_EL1) {
1054                 if (val & (0xfUL << ID_AA64PFR0_SVE_SHIFT))
1055                         kvm_debug("SVE unsupported for guests, suppressing\n");
1056
1057                 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
1058         } else if (id == SYS_ID_AA64ISAR1_EL1) {
1059                 const u64 ptrauth_mask = (0xfUL << ID_AA64ISAR1_APA_SHIFT) |
1060                                          (0xfUL << ID_AA64ISAR1_API_SHIFT) |
1061                                          (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
1062                                          (0xfUL << ID_AA64ISAR1_GPI_SHIFT);
1063                 if (val & ptrauth_mask)
1064                         kvm_debug("ptrauth unsupported for guests, suppressing\n");
1065                 val &= ~ptrauth_mask;
1066         }
1067
1068         return val;
1069 }
1070
1071 /* cpufeature ID register access trap handlers */
1072
1073 static bool __access_id_reg(struct kvm_vcpu *vcpu,
1074                             struct sys_reg_params *p,
1075                             const struct sys_reg_desc *r,
1076                             bool raz)
1077 {
1078         if (p->is_write)
1079                 return write_to_read_only(vcpu, p, r);
1080
1081         p->regval = read_id_reg(r, raz);
1082         return true;
1083 }
1084
1085 static bool access_id_reg(struct kvm_vcpu *vcpu,
1086                           struct sys_reg_params *p,
1087                           const struct sys_reg_desc *r)
1088 {
1089         return __access_id_reg(vcpu, p, r, false);
1090 }
1091
1092 static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1093                               struct sys_reg_params *p,
1094                               const struct sys_reg_desc *r)
1095 {
1096         return __access_id_reg(vcpu, p, r, true);
1097 }
1098
1099 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1100 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1101 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1102
1103 /*
1104  * cpufeature ID register user accessors
1105  *
1106  * For now, these registers are immutable for userspace, so no values
1107  * are stored, and for set_id_reg() we don't allow the effective value
1108  * to be changed.
1109  */
1110 static int __get_id_reg(const struct sys_reg_desc *rd, void __user *uaddr,
1111                         bool raz)
1112 {
1113         const u64 id = sys_reg_to_index(rd);
1114         const u64 val = read_id_reg(rd, raz);
1115
1116         return reg_to_user(uaddr, &val, id);
1117 }
1118
1119 static int __set_id_reg(const struct sys_reg_desc *rd, void __user *uaddr,
1120                         bool raz)
1121 {
1122         const u64 id = sys_reg_to_index(rd);
1123         int err;
1124         u64 val;
1125
1126         err = reg_from_user(&val, uaddr, id);
1127         if (err)
1128                 return err;
1129
1130         /* This is what we mean by invariant: you can't change it. */
1131         if (val != read_id_reg(rd, raz))
1132                 return -EINVAL;
1133
1134         return 0;
1135 }
1136
1137 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1138                       const struct kvm_one_reg *reg, void __user *uaddr)
1139 {
1140         return __get_id_reg(rd, uaddr, false);
1141 }
1142
1143 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1144                       const struct kvm_one_reg *reg, void __user *uaddr)
1145 {
1146         return __set_id_reg(rd, uaddr, false);
1147 }
1148
1149 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1150                           const struct kvm_one_reg *reg, void __user *uaddr)
1151 {
1152         return __get_id_reg(rd, uaddr, true);
1153 }
1154
1155 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1156                           const struct kvm_one_reg *reg, void __user *uaddr)
1157 {
1158         return __set_id_reg(rd, uaddr, true);
1159 }
1160
1161 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1162                        const struct sys_reg_desc *r)
1163 {
1164         if (p->is_write)
1165                 return write_to_read_only(vcpu, p, r);
1166
1167         p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1168         return true;
1169 }
1170
1171 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1172                          const struct sys_reg_desc *r)
1173 {
1174         if (p->is_write)
1175                 return write_to_read_only(vcpu, p, r);
1176
1177         p->regval = read_sysreg(clidr_el1);
1178         return true;
1179 }
1180
1181 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1182                           const struct sys_reg_desc *r)
1183 {
1184         if (p->is_write)
1185                 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
1186         else
1187                 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
1188         return true;
1189 }
1190
1191 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1192                           const struct sys_reg_desc *r)
1193 {
1194         u32 csselr;
1195
1196         if (p->is_write)
1197                 return write_to_read_only(vcpu, p, r);
1198
1199         csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1200         p->regval = get_ccsidr(csselr);
1201
1202         /*
1203          * Guests should not be doing cache operations by set/way at all, and
1204          * for this reason, we trap them and attempt to infer the intent, so
1205          * that we can flush the entire guest's address space at the appropriate
1206          * time.
1207          * To prevent this trapping from causing performance problems, let's
1208          * expose the geometry of all data and unified caches (which are
1209          * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1210          * [If guests should attempt to infer aliasing properties from the
1211          * geometry (which is not permitted by the architecture), they would
1212          * only do so for virtually indexed caches.]
1213          */
1214         if (!(csselr & 1)) // data or unified cache
1215                 p->regval &= ~GENMASK(27, 3);
1216         return true;
1217 }
1218
1219 /* sys_reg_desc initialiser for known cpufeature ID registers */
1220 #define ID_SANITISED(name) {                    \
1221         SYS_DESC(SYS_##name),                   \
1222         .access = access_id_reg,                \
1223         .get_user = get_id_reg,                 \
1224         .set_user = set_id_reg,                 \
1225 }
1226
1227 /*
1228  * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1229  * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1230  * (1 <= crm < 8, 0 <= Op2 < 8).
1231  */
1232 #define ID_UNALLOCATED(crm, op2) {                      \
1233         Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2),     \
1234         .access = access_raz_id_reg,                    \
1235         .get_user = get_raz_id_reg,                     \
1236         .set_user = set_raz_id_reg,                     \
1237 }
1238
1239 /*
1240  * sys_reg_desc initialiser for known ID registers that we hide from guests.
1241  * For now, these are exposed just like unallocated ID regs: they appear
1242  * RAZ for the guest.
1243  */
1244 #define ID_HIDDEN(name) {                       \
1245         SYS_DESC(SYS_##name),                   \
1246         .access = access_raz_id_reg,            \
1247         .get_user = get_raz_id_reg,             \
1248         .set_user = set_raz_id_reg,             \
1249 }
1250
1251 /*
1252  * Architected system registers.
1253  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1254  *
1255  * Debug handling: We do trap most, if not all debug related system
1256  * registers. The implementation is good enough to ensure that a guest
1257  * can use these with minimal performance degradation. The drawback is
1258  * that we don't implement any of the external debug, none of the
1259  * OSlock protocol. This should be revisited if we ever encounter a
1260  * more demanding guest...
1261  */
1262 static const struct sys_reg_desc sys_reg_descs[] = {
1263         { SYS_DESC(SYS_DC_ISW), access_dcsw },
1264         { SYS_DESC(SYS_DC_CSW), access_dcsw },
1265         { SYS_DESC(SYS_DC_CISW), access_dcsw },
1266
1267         DBG_BCR_BVR_WCR_WVR_EL1(0),
1268         DBG_BCR_BVR_WCR_WVR_EL1(1),
1269         { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1270         { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1271         DBG_BCR_BVR_WCR_WVR_EL1(2),
1272         DBG_BCR_BVR_WCR_WVR_EL1(3),
1273         DBG_BCR_BVR_WCR_WVR_EL1(4),
1274         DBG_BCR_BVR_WCR_WVR_EL1(5),
1275         DBG_BCR_BVR_WCR_WVR_EL1(6),
1276         DBG_BCR_BVR_WCR_WVR_EL1(7),
1277         DBG_BCR_BVR_WCR_WVR_EL1(8),
1278         DBG_BCR_BVR_WCR_WVR_EL1(9),
1279         DBG_BCR_BVR_WCR_WVR_EL1(10),
1280         DBG_BCR_BVR_WCR_WVR_EL1(11),
1281         DBG_BCR_BVR_WCR_WVR_EL1(12),
1282         DBG_BCR_BVR_WCR_WVR_EL1(13),
1283         DBG_BCR_BVR_WCR_WVR_EL1(14),
1284         DBG_BCR_BVR_WCR_WVR_EL1(15),
1285
1286         { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1287         { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1288         { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1289         { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1290         { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1291         { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1292         { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1293         { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1294
1295         { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1296         { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1297         // DBGDTR[TR]X_EL0 share the same encoding
1298         { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1299
1300         { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1301
1302         { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1303
1304         /*
1305          * ID regs: all ID_SANITISED() entries here must have corresponding
1306          * entries in arm64_ftr_regs[].
1307          */
1308
1309         /* AArch64 mappings of the AArch32 ID registers */
1310         /* CRm=1 */
1311         ID_SANITISED(ID_PFR0_EL1),
1312         ID_SANITISED(ID_PFR1_EL1),
1313         ID_SANITISED(ID_DFR0_EL1),
1314         ID_HIDDEN(ID_AFR0_EL1),
1315         ID_SANITISED(ID_MMFR0_EL1),
1316         ID_SANITISED(ID_MMFR1_EL1),
1317         ID_SANITISED(ID_MMFR2_EL1),
1318         ID_SANITISED(ID_MMFR3_EL1),
1319
1320         /* CRm=2 */
1321         ID_SANITISED(ID_ISAR0_EL1),
1322         ID_SANITISED(ID_ISAR1_EL1),
1323         ID_SANITISED(ID_ISAR2_EL1),
1324         ID_SANITISED(ID_ISAR3_EL1),
1325         ID_SANITISED(ID_ISAR4_EL1),
1326         ID_SANITISED(ID_ISAR5_EL1),
1327         ID_SANITISED(ID_MMFR4_EL1),
1328         ID_UNALLOCATED(2,7),
1329
1330         /* CRm=3 */
1331         ID_SANITISED(MVFR0_EL1),
1332         ID_SANITISED(MVFR1_EL1),
1333         ID_SANITISED(MVFR2_EL1),
1334         ID_UNALLOCATED(3,3),
1335         ID_UNALLOCATED(3,4),
1336         ID_UNALLOCATED(3,5),
1337         ID_UNALLOCATED(3,6),
1338         ID_UNALLOCATED(3,7),
1339
1340         /* AArch64 ID registers */
1341         /* CRm=4 */
1342         ID_SANITISED(ID_AA64PFR0_EL1),
1343         ID_SANITISED(ID_AA64PFR1_EL1),
1344         ID_UNALLOCATED(4,2),
1345         ID_UNALLOCATED(4,3),
1346         ID_UNALLOCATED(4,4),
1347         ID_UNALLOCATED(4,5),
1348         ID_UNALLOCATED(4,6),
1349         ID_UNALLOCATED(4,7),
1350
1351         /* CRm=5 */
1352         ID_SANITISED(ID_AA64DFR0_EL1),
1353         ID_SANITISED(ID_AA64DFR1_EL1),
1354         ID_UNALLOCATED(5,2),
1355         ID_UNALLOCATED(5,3),
1356         ID_HIDDEN(ID_AA64AFR0_EL1),
1357         ID_HIDDEN(ID_AA64AFR1_EL1),
1358         ID_UNALLOCATED(5,6),
1359         ID_UNALLOCATED(5,7),
1360
1361         /* CRm=6 */
1362         ID_SANITISED(ID_AA64ISAR0_EL1),
1363         ID_SANITISED(ID_AA64ISAR1_EL1),
1364         ID_UNALLOCATED(6,2),
1365         ID_UNALLOCATED(6,3),
1366         ID_UNALLOCATED(6,4),
1367         ID_UNALLOCATED(6,5),
1368         ID_UNALLOCATED(6,6),
1369         ID_UNALLOCATED(6,7),
1370
1371         /* CRm=7 */
1372         ID_SANITISED(ID_AA64MMFR0_EL1),
1373         ID_SANITISED(ID_AA64MMFR1_EL1),
1374         ID_SANITISED(ID_AA64MMFR2_EL1),
1375         ID_UNALLOCATED(7,3),
1376         ID_UNALLOCATED(7,4),
1377         ID_UNALLOCATED(7,5),
1378         ID_UNALLOCATED(7,6),
1379         ID_UNALLOCATED(7,7),
1380
1381         { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1382         { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
1383         { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1384         { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1385         { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1386
1387         { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1388         { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1389         { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
1390
1391         { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1392         { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1393         { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1394         { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1395         { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1396         { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1397         { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1398         { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1399
1400         { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1401         { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
1402
1403         { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
1404         { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, NULL, PMINTENSET_EL1 },
1405
1406         { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1407         { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1408
1409         { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1410         { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1411         { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1412         { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1413         { SYS_DESC(SYS_LORID_EL1), trap_loregion },
1414
1415         { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1416         { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
1417
1418         { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
1419         { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
1420         { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
1421         { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
1422         { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
1423         { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
1424         { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1425         { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
1426         { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
1427         { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
1428         { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
1429         { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
1430
1431         { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1432         { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
1433
1434         { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
1435
1436         { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1437         { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1438         { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1439         { SYS_DESC(SYS_CTR_EL0), access_ctr },
1440
1441         { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, },
1442         { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1443         { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, NULL, PMCNTENSET_EL0 },
1444         { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, NULL, PMOVSSET_EL0 },
1445         { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 },
1446         { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 },
1447         { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid },
1448         { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid },
1449         { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1450         { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper },
1451         { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr },
1452         /*
1453          * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1454          * in 32bit mode. Here we choose to reset it as zero for consistency.
1455          */
1456         { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1457         { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
1458
1459         { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1460         { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1461
1462         { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1463         { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1464         { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
1465
1466         /* PMEVCNTRn_EL0 */
1467         PMU_PMEVCNTR_EL0(0),
1468         PMU_PMEVCNTR_EL0(1),
1469         PMU_PMEVCNTR_EL0(2),
1470         PMU_PMEVCNTR_EL0(3),
1471         PMU_PMEVCNTR_EL0(4),
1472         PMU_PMEVCNTR_EL0(5),
1473         PMU_PMEVCNTR_EL0(6),
1474         PMU_PMEVCNTR_EL0(7),
1475         PMU_PMEVCNTR_EL0(8),
1476         PMU_PMEVCNTR_EL0(9),
1477         PMU_PMEVCNTR_EL0(10),
1478         PMU_PMEVCNTR_EL0(11),
1479         PMU_PMEVCNTR_EL0(12),
1480         PMU_PMEVCNTR_EL0(13),
1481         PMU_PMEVCNTR_EL0(14),
1482         PMU_PMEVCNTR_EL0(15),
1483         PMU_PMEVCNTR_EL0(16),
1484         PMU_PMEVCNTR_EL0(17),
1485         PMU_PMEVCNTR_EL0(18),
1486         PMU_PMEVCNTR_EL0(19),
1487         PMU_PMEVCNTR_EL0(20),
1488         PMU_PMEVCNTR_EL0(21),
1489         PMU_PMEVCNTR_EL0(22),
1490         PMU_PMEVCNTR_EL0(23),
1491         PMU_PMEVCNTR_EL0(24),
1492         PMU_PMEVCNTR_EL0(25),
1493         PMU_PMEVCNTR_EL0(26),
1494         PMU_PMEVCNTR_EL0(27),
1495         PMU_PMEVCNTR_EL0(28),
1496         PMU_PMEVCNTR_EL0(29),
1497         PMU_PMEVCNTR_EL0(30),
1498         /* PMEVTYPERn_EL0 */
1499         PMU_PMEVTYPER_EL0(0),
1500         PMU_PMEVTYPER_EL0(1),
1501         PMU_PMEVTYPER_EL0(2),
1502         PMU_PMEVTYPER_EL0(3),
1503         PMU_PMEVTYPER_EL0(4),
1504         PMU_PMEVTYPER_EL0(5),
1505         PMU_PMEVTYPER_EL0(6),
1506         PMU_PMEVTYPER_EL0(7),
1507         PMU_PMEVTYPER_EL0(8),
1508         PMU_PMEVTYPER_EL0(9),
1509         PMU_PMEVTYPER_EL0(10),
1510         PMU_PMEVTYPER_EL0(11),
1511         PMU_PMEVTYPER_EL0(12),
1512         PMU_PMEVTYPER_EL0(13),
1513         PMU_PMEVTYPER_EL0(14),
1514         PMU_PMEVTYPER_EL0(15),
1515         PMU_PMEVTYPER_EL0(16),
1516         PMU_PMEVTYPER_EL0(17),
1517         PMU_PMEVTYPER_EL0(18),
1518         PMU_PMEVTYPER_EL0(19),
1519         PMU_PMEVTYPER_EL0(20),
1520         PMU_PMEVTYPER_EL0(21),
1521         PMU_PMEVTYPER_EL0(22),
1522         PMU_PMEVTYPER_EL0(23),
1523         PMU_PMEVTYPER_EL0(24),
1524         PMU_PMEVTYPER_EL0(25),
1525         PMU_PMEVTYPER_EL0(26),
1526         PMU_PMEVTYPER_EL0(27),
1527         PMU_PMEVTYPER_EL0(28),
1528         PMU_PMEVTYPER_EL0(29),
1529         PMU_PMEVTYPER_EL0(30),
1530         /*
1531          * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1532          * in 32bit mode. Here we choose to reset it as zero for consistency.
1533          */
1534         { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1535
1536         { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1537         { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1538         { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1539 };
1540
1541 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
1542                         struct sys_reg_params *p,
1543                         const struct sys_reg_desc *r)
1544 {
1545         if (p->is_write) {
1546                 return ignore_write(vcpu, p);
1547         } else {
1548                 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1549                 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1550                 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1551
1552                 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1553                              (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1554                              (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1555                              | (6 << 16) | (el3 << 14) | (el3 << 12));
1556                 return true;
1557         }
1558 }
1559
1560 static bool trap_debug32(struct kvm_vcpu *vcpu,
1561                          struct sys_reg_params *p,
1562                          const struct sys_reg_desc *r)
1563 {
1564         if (p->is_write) {
1565                 vcpu_cp14(vcpu, r->reg) = p->regval;
1566                 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
1567         } else {
1568                 p->regval = vcpu_cp14(vcpu, r->reg);
1569         }
1570
1571         return true;
1572 }
1573
1574 /* AArch32 debug register mappings
1575  *
1576  * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1577  * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1578  *
1579  * All control registers and watchpoint value registers are mapped to
1580  * the lower 32 bits of their AArch64 equivalents. We share the trap
1581  * handlers with the above AArch64 code which checks what mode the
1582  * system is in.
1583  */
1584
1585 static bool trap_xvr(struct kvm_vcpu *vcpu,
1586                      struct sys_reg_params *p,
1587                      const struct sys_reg_desc *rd)
1588 {
1589         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1590
1591         if (p->is_write) {
1592                 u64 val = *dbg_reg;
1593
1594                 val &= 0xffffffffUL;
1595                 val |= p->regval << 32;
1596                 *dbg_reg = val;
1597
1598                 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
1599         } else {
1600                 p->regval = *dbg_reg >> 32;
1601         }
1602
1603         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1604
1605         return true;
1606 }
1607
1608 #define DBG_BCR_BVR_WCR_WVR(n)                                          \
1609         /* DBGBVRn */                                                   \
1610         { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n },     \
1611         /* DBGBCRn */                                                   \
1612         { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n },     \
1613         /* DBGWVRn */                                                   \
1614         { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n },     \
1615         /* DBGWCRn */                                                   \
1616         { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1617
1618 #define DBGBXVR(n)                                                      \
1619         { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1620
1621 /*
1622  * Trapped cp14 registers. We generally ignore most of the external
1623  * debug, on the principle that they don't really make sense to a
1624  * guest. Revisit this one day, would this principle change.
1625  */
1626 static const struct sys_reg_desc cp14_regs[] = {
1627         /* DBGIDR */
1628         { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1629         /* DBGDTRRXext */
1630         { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1631
1632         DBG_BCR_BVR_WCR_WVR(0),
1633         /* DBGDSCRint */
1634         { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1635         DBG_BCR_BVR_WCR_WVR(1),
1636         /* DBGDCCINT */
1637         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
1638         /* DBGDSCRext */
1639         { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
1640         DBG_BCR_BVR_WCR_WVR(2),
1641         /* DBGDTR[RT]Xint */
1642         { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1643         /* DBGDTR[RT]Xext */
1644         { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1645         DBG_BCR_BVR_WCR_WVR(3),
1646         DBG_BCR_BVR_WCR_WVR(4),
1647         DBG_BCR_BVR_WCR_WVR(5),
1648         /* DBGWFAR */
1649         { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1650         /* DBGOSECCR */
1651         { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1652         DBG_BCR_BVR_WCR_WVR(6),
1653         /* DBGVCR */
1654         { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
1655         DBG_BCR_BVR_WCR_WVR(7),
1656         DBG_BCR_BVR_WCR_WVR(8),
1657         DBG_BCR_BVR_WCR_WVR(9),
1658         DBG_BCR_BVR_WCR_WVR(10),
1659         DBG_BCR_BVR_WCR_WVR(11),
1660         DBG_BCR_BVR_WCR_WVR(12),
1661         DBG_BCR_BVR_WCR_WVR(13),
1662         DBG_BCR_BVR_WCR_WVR(14),
1663         DBG_BCR_BVR_WCR_WVR(15),
1664
1665         /* DBGDRAR (32bit) */
1666         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1667
1668         DBGBXVR(0),
1669         /* DBGOSLAR */
1670         { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1671         DBGBXVR(1),
1672         /* DBGOSLSR */
1673         { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1674         DBGBXVR(2),
1675         DBGBXVR(3),
1676         /* DBGOSDLR */
1677         { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1678         DBGBXVR(4),
1679         /* DBGPRCR */
1680         { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1681         DBGBXVR(5),
1682         DBGBXVR(6),
1683         DBGBXVR(7),
1684         DBGBXVR(8),
1685         DBGBXVR(9),
1686         DBGBXVR(10),
1687         DBGBXVR(11),
1688         DBGBXVR(12),
1689         DBGBXVR(13),
1690         DBGBXVR(14),
1691         DBGBXVR(15),
1692
1693         /* DBGDSAR (32bit) */
1694         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1695
1696         /* DBGDEVID2 */
1697         { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1698         /* DBGDEVID1 */
1699         { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1700         /* DBGDEVID */
1701         { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1702         /* DBGCLAIMSET */
1703         { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1704         /* DBGCLAIMCLR */
1705         { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1706         /* DBGAUTHSTATUS */
1707         { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1708 };
1709
1710 /* Trapped cp14 64bit registers */
1711 static const struct sys_reg_desc cp14_64_regs[] = {
1712         /* DBGDRAR (64bit) */
1713         { Op1( 0), CRm( 1), .access = trap_raz_wi },
1714
1715         /* DBGDSAR (64bit) */
1716         { Op1( 0), CRm( 2), .access = trap_raz_wi },
1717 };
1718
1719 /* Macro to expand the PMEVCNTRn register */
1720 #define PMU_PMEVCNTR(n)                                                 \
1721         /* PMEVCNTRn */                                                 \
1722         { Op1(0), CRn(0b1110),                                          \
1723           CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1724           access_pmu_evcntr }
1725
1726 /* Macro to expand the PMEVTYPERn register */
1727 #define PMU_PMEVTYPER(n)                                                \
1728         /* PMEVTYPERn */                                                \
1729         { Op1(0), CRn(0b1110),                                          \
1730           CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1731           access_pmu_evtyper }
1732
1733 /*
1734  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1735  * depending on the way they are accessed (as a 32bit or a 64bit
1736  * register).
1737  */
1738 static const struct sys_reg_desc cp15_regs[] = {
1739         { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
1740         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1741         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1742         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1743         { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1744         { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1745         { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1746         { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1747         { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1748         { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1749         { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1750         { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1751
1752         /*
1753          * DC{C,I,CI}SW operations:
1754          */
1755         { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1756         { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1757         { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1758
1759         /* PMU */
1760         { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1761         { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1762         { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1763         { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1764         { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1765         { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1766         { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1767         { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1768         { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
1769         { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
1770         { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
1771         { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
1772         { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1773         { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
1774         { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
1775
1776         { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1777         { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1778         { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1779         { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
1780
1781         /* ICC_SRE */
1782         { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
1783
1784         { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
1785
1786         /* Arch Tmers */
1787         { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
1788         { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
1789
1790         /* PMEVCNTRn */
1791         PMU_PMEVCNTR(0),
1792         PMU_PMEVCNTR(1),
1793         PMU_PMEVCNTR(2),
1794         PMU_PMEVCNTR(3),
1795         PMU_PMEVCNTR(4),
1796         PMU_PMEVCNTR(5),
1797         PMU_PMEVCNTR(6),
1798         PMU_PMEVCNTR(7),
1799         PMU_PMEVCNTR(8),
1800         PMU_PMEVCNTR(9),
1801         PMU_PMEVCNTR(10),
1802         PMU_PMEVCNTR(11),
1803         PMU_PMEVCNTR(12),
1804         PMU_PMEVCNTR(13),
1805         PMU_PMEVCNTR(14),
1806         PMU_PMEVCNTR(15),
1807         PMU_PMEVCNTR(16),
1808         PMU_PMEVCNTR(17),
1809         PMU_PMEVCNTR(18),
1810         PMU_PMEVCNTR(19),
1811         PMU_PMEVCNTR(20),
1812         PMU_PMEVCNTR(21),
1813         PMU_PMEVCNTR(22),
1814         PMU_PMEVCNTR(23),
1815         PMU_PMEVCNTR(24),
1816         PMU_PMEVCNTR(25),
1817         PMU_PMEVCNTR(26),
1818         PMU_PMEVCNTR(27),
1819         PMU_PMEVCNTR(28),
1820         PMU_PMEVCNTR(29),
1821         PMU_PMEVCNTR(30),
1822         /* PMEVTYPERn */
1823         PMU_PMEVTYPER(0),
1824         PMU_PMEVTYPER(1),
1825         PMU_PMEVTYPER(2),
1826         PMU_PMEVTYPER(3),
1827         PMU_PMEVTYPER(4),
1828         PMU_PMEVTYPER(5),
1829         PMU_PMEVTYPER(6),
1830         PMU_PMEVTYPER(7),
1831         PMU_PMEVTYPER(8),
1832         PMU_PMEVTYPER(9),
1833         PMU_PMEVTYPER(10),
1834         PMU_PMEVTYPER(11),
1835         PMU_PMEVTYPER(12),
1836         PMU_PMEVTYPER(13),
1837         PMU_PMEVTYPER(14),
1838         PMU_PMEVTYPER(15),
1839         PMU_PMEVTYPER(16),
1840         PMU_PMEVTYPER(17),
1841         PMU_PMEVTYPER(18),
1842         PMU_PMEVTYPER(19),
1843         PMU_PMEVTYPER(20),
1844         PMU_PMEVTYPER(21),
1845         PMU_PMEVTYPER(22),
1846         PMU_PMEVTYPER(23),
1847         PMU_PMEVTYPER(24),
1848         PMU_PMEVTYPER(25),
1849         PMU_PMEVTYPER(26),
1850         PMU_PMEVTYPER(27),
1851         PMU_PMEVTYPER(28),
1852         PMU_PMEVTYPER(29),
1853         PMU_PMEVTYPER(30),
1854         /* PMCCFILTR */
1855         { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
1856
1857         { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
1858         { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
1859         { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR },
1860 };
1861
1862 static const struct sys_reg_desc cp15_64_regs[] = {
1863         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1864         { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
1865         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
1866         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
1867         { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
1868         { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
1869         { SYS_DESC(SYS_AARCH32_CNTP_CVAL),    access_arch_timer },
1870 };
1871
1872 /* Target specific emulation tables */
1873 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
1874
1875 void kvm_register_target_sys_reg_table(unsigned int target,
1876                                        struct kvm_sys_reg_target_table *table)
1877 {
1878         target_tables[target] = table;
1879 }
1880
1881 /* Get specific register table for this target. */
1882 static const struct sys_reg_desc *get_target_table(unsigned target,
1883                                                    bool mode_is_64,
1884                                                    size_t *num)
1885 {
1886         struct kvm_sys_reg_target_table *table;
1887
1888         table = target_tables[target];
1889         if (mode_is_64) {
1890                 *num = table->table64.num;
1891                 return table->table64.table;
1892         } else {
1893                 *num = table->table32.num;
1894                 return table->table32.table;
1895         }
1896 }
1897
1898 static int match_sys_reg(const void *key, const void *elt)
1899 {
1900         const unsigned long pval = (unsigned long)key;
1901         const struct sys_reg_desc *r = elt;
1902
1903         return pval - reg_to_encoding(r);
1904 }
1905
1906 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
1907                                          const struct sys_reg_desc table[],
1908                                          unsigned int num)
1909 {
1910         unsigned long pval = reg_to_encoding(params);
1911
1912         return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
1913 }
1914
1915 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
1916 {
1917         kvm_inject_undefined(vcpu);
1918         return 1;
1919 }
1920
1921 static void perform_access(struct kvm_vcpu *vcpu,
1922                            struct sys_reg_params *params,
1923                            const struct sys_reg_desc *r)
1924 {
1925         trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
1926
1927         /*
1928          * Not having an accessor means that we have configured a trap
1929          * that we don't know how to handle. This certainly qualifies
1930          * as a gross bug that should be fixed right away.
1931          */
1932         BUG_ON(!r->access);
1933
1934         /* Skip instruction if instructed so */
1935         if (likely(r->access(vcpu, params, r)))
1936                 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1937 }
1938
1939 /*
1940  * emulate_cp --  tries to match a sys_reg access in a handling table, and
1941  *                call the corresponding trap handler.
1942  *
1943  * @params: pointer to the descriptor of the access
1944  * @table: array of trap descriptors
1945  * @num: size of the trap descriptor array
1946  *
1947  * Return 0 if the access has been handled, and -1 if not.
1948  */
1949 static int emulate_cp(struct kvm_vcpu *vcpu,
1950                       struct sys_reg_params *params,
1951                       const struct sys_reg_desc *table,
1952                       size_t num)
1953 {
1954         const struct sys_reg_desc *r;
1955
1956         if (!table)
1957                 return -1;      /* Not handled */
1958
1959         r = find_reg(params, table, num);
1960
1961         if (r) {
1962                 perform_access(vcpu, params, r);
1963                 return 0;
1964         }
1965
1966         /* Not handled */
1967         return -1;
1968 }
1969
1970 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
1971                                 struct sys_reg_params *params)
1972 {
1973         u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
1974         int cp = -1;
1975
1976         switch(hsr_ec) {
1977         case ESR_ELx_EC_CP15_32:
1978         case ESR_ELx_EC_CP15_64:
1979                 cp = 15;
1980                 break;
1981         case ESR_ELx_EC_CP14_MR:
1982         case ESR_ELx_EC_CP14_64:
1983                 cp = 14;
1984                 break;
1985         default:
1986                 WARN_ON(1);
1987         }
1988
1989         kvm_err("Unsupported guest CP%d access at: %08lx [%08lx]\n",
1990                 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
1991         print_sys_reg_instr(params);
1992         kvm_inject_undefined(vcpu);
1993 }
1994
1995 /**
1996  * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
1997  * @vcpu: The VCPU pointer
1998  * @run:  The kvm_run struct
1999  */
2000 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2001                             const struct sys_reg_desc *global,
2002                             size_t nr_global,
2003                             const struct sys_reg_desc *target_specific,
2004                             size_t nr_specific)
2005 {
2006         struct sys_reg_params params;
2007         u32 hsr = kvm_vcpu_get_hsr(vcpu);
2008         int Rt = kvm_vcpu_sys_get_rt(vcpu);
2009         int Rt2 = (hsr >> 10) & 0x1f;
2010
2011         params.is_aarch32 = true;
2012         params.is_32bit = false;
2013         params.CRm = (hsr >> 1) & 0xf;
2014         params.is_write = ((hsr & 1) == 0);
2015
2016         params.Op0 = 0;
2017         params.Op1 = (hsr >> 16) & 0xf;
2018         params.Op2 = 0;
2019         params.CRn = 0;
2020
2021         /*
2022          * Make a 64-bit value out of Rt and Rt2. As we use the same trap
2023          * backends between AArch32 and AArch64, we get away with it.
2024          */
2025         if (params.is_write) {
2026                 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2027                 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
2028         }
2029
2030         /*
2031          * Try to emulate the coprocessor access using the target
2032          * specific table first, and using the global table afterwards.
2033          * If either of the tables contains a handler, handle the
2034          * potential register operation in the case of a read and return
2035          * with success.
2036          */
2037         if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
2038             !emulate_cp(vcpu, &params, global, nr_global)) {
2039                 /* Split up the value between registers for the read side */
2040                 if (!params.is_write) {
2041                         vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2042                         vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2043                 }
2044
2045                 return 1;
2046         }
2047
2048         unhandled_cp_access(vcpu, &params);
2049         return 1;
2050 }
2051
2052 /**
2053  * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
2054  * @vcpu: The VCPU pointer
2055  * @run:  The kvm_run struct
2056  */
2057 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2058                             const struct sys_reg_desc *global,
2059                             size_t nr_global,
2060                             const struct sys_reg_desc *target_specific,
2061                             size_t nr_specific)
2062 {
2063         struct sys_reg_params params;
2064         u32 hsr = kvm_vcpu_get_hsr(vcpu);
2065         int Rt  = kvm_vcpu_sys_get_rt(vcpu);
2066
2067         params.is_aarch32 = true;
2068         params.is_32bit = true;
2069         params.CRm = (hsr >> 1) & 0xf;
2070         params.regval = vcpu_get_reg(vcpu, Rt);
2071         params.is_write = ((hsr & 1) == 0);
2072         params.CRn = (hsr >> 10) & 0xf;
2073         params.Op0 = 0;
2074         params.Op1 = (hsr >> 14) & 0x7;
2075         params.Op2 = (hsr >> 17) & 0x7;
2076
2077         if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
2078             !emulate_cp(vcpu, &params, global, nr_global)) {
2079                 if (!params.is_write)
2080                         vcpu_set_reg(vcpu, Rt, params.regval);
2081                 return 1;
2082         }
2083
2084         unhandled_cp_access(vcpu, &params);
2085         return 1;
2086 }
2087
2088 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
2089 {
2090         const struct sys_reg_desc *target_specific;
2091         size_t num;
2092
2093         target_specific = get_target_table(vcpu->arch.target, false, &num);
2094         return kvm_handle_cp_64(vcpu,
2095                                 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
2096                                 target_specific, num);
2097 }
2098
2099 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
2100 {
2101         const struct sys_reg_desc *target_specific;
2102         size_t num;
2103
2104         target_specific = get_target_table(vcpu->arch.target, false, &num);
2105         return kvm_handle_cp_32(vcpu,
2106                                 cp15_regs, ARRAY_SIZE(cp15_regs),
2107                                 target_specific, num);
2108 }
2109
2110 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
2111 {
2112         return kvm_handle_cp_64(vcpu,
2113                                 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
2114                                 NULL, 0);
2115 }
2116
2117 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
2118 {
2119         return kvm_handle_cp_32(vcpu,
2120                                 cp14_regs, ARRAY_SIZE(cp14_regs),
2121                                 NULL, 0);
2122 }
2123
2124 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
2125                            struct sys_reg_params *params)
2126 {
2127         size_t num;
2128         const struct sys_reg_desc *table, *r;
2129
2130         table = get_target_table(vcpu->arch.target, true, &num);
2131
2132         /* Search target-specific then generic table. */
2133         r = find_reg(params, table, num);
2134         if (!r)
2135                 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2136
2137         if (likely(r)) {
2138                 perform_access(vcpu, params, r);
2139         } else {
2140                 kvm_err("Unsupported guest sys_reg access at: %lx [%08lx]\n",
2141                         *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2142                 print_sys_reg_instr(params);
2143                 kvm_inject_undefined(vcpu);
2144         }
2145         return 1;
2146 }
2147
2148 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
2149                               const struct sys_reg_desc *table, size_t num)
2150 {
2151         unsigned long i;
2152
2153         for (i = 0; i < num; i++)
2154                 if (table[i].reset)
2155                         table[i].reset(vcpu, &table[i]);
2156 }
2157
2158 /**
2159  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2160  * @vcpu: The VCPU pointer
2161  * @run:  The kvm_run struct
2162  */
2163 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
2164 {
2165         struct sys_reg_params params;
2166         unsigned long esr = kvm_vcpu_get_hsr(vcpu);
2167         int Rt = kvm_vcpu_sys_get_rt(vcpu);
2168         int ret;
2169
2170         trace_kvm_handle_sys_reg(esr);
2171
2172         params.is_aarch32 = false;
2173         params.is_32bit = false;
2174         params.Op0 = (esr >> 20) & 3;
2175         params.Op1 = (esr >> 14) & 0x7;
2176         params.CRn = (esr >> 10) & 0xf;
2177         params.CRm = (esr >> 1) & 0xf;
2178         params.Op2 = (esr >> 17) & 0x7;
2179         params.regval = vcpu_get_reg(vcpu, Rt);
2180         params.is_write = !(esr & 1);
2181
2182         ret = emulate_sys_reg(vcpu, &params);
2183
2184         if (!params.is_write)
2185                 vcpu_set_reg(vcpu, Rt, params.regval);
2186         return ret;
2187 }
2188
2189 /******************************************************************************
2190  * Userspace API
2191  *****************************************************************************/
2192
2193 static bool index_to_params(u64 id, struct sys_reg_params *params)
2194 {
2195         switch (id & KVM_REG_SIZE_MASK) {
2196         case KVM_REG_SIZE_U64:
2197                 /* Any unused index bits means it's not valid. */
2198                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2199                               | KVM_REG_ARM_COPROC_MASK
2200                               | KVM_REG_ARM64_SYSREG_OP0_MASK
2201                               | KVM_REG_ARM64_SYSREG_OP1_MASK
2202                               | KVM_REG_ARM64_SYSREG_CRN_MASK
2203                               | KVM_REG_ARM64_SYSREG_CRM_MASK
2204                               | KVM_REG_ARM64_SYSREG_OP2_MASK))
2205                         return false;
2206                 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2207                                >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2208                 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2209                                >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2210                 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2211                                >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2212                 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2213                                >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2214                 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2215                                >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2216                 return true;
2217         default:
2218                 return false;
2219         }
2220 }
2221
2222 const struct sys_reg_desc *find_reg_by_id(u64 id,
2223                                           struct sys_reg_params *params,
2224                                           const struct sys_reg_desc table[],
2225                                           unsigned int num)
2226 {
2227         if (!index_to_params(id, params))
2228                 return NULL;
2229
2230         return find_reg(params, table, num);
2231 }
2232
2233 /* Decode an index value, and find the sys_reg_desc entry. */
2234 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2235                                                     u64 id)
2236 {
2237         size_t num;
2238         const struct sys_reg_desc *table, *r;
2239         struct sys_reg_params params;
2240
2241         /* We only do sys_reg for now. */
2242         if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2243                 return NULL;
2244
2245         table = get_target_table(vcpu->arch.target, true, &num);
2246         r = find_reg_by_id(id, &params, table, num);
2247         if (!r)
2248                 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2249
2250         /* Not saved in the sys_reg array and not otherwise accessible? */
2251         if (r && !(r->reg || r->get_user))
2252                 r = NULL;
2253
2254         return r;
2255 }
2256
2257 /*
2258  * These are the invariant sys_reg registers: we let the guest see the
2259  * host versions of these, so they're part of the guest state.
2260  *
2261  * A future CPU may provide a mechanism to present different values to
2262  * the guest, or a future kvm may trap them.
2263  */
2264
2265 #define FUNCTION_INVARIANT(reg)                                         \
2266         static void get_##reg(struct kvm_vcpu *v,                       \
2267                               const struct sys_reg_desc *r)             \
2268         {                                                               \
2269                 ((struct sys_reg_desc *)r)->val = read_sysreg(reg);     \
2270         }
2271
2272 FUNCTION_INVARIANT(midr_el1)
2273 FUNCTION_INVARIANT(revidr_el1)
2274 FUNCTION_INVARIANT(clidr_el1)
2275 FUNCTION_INVARIANT(aidr_el1)
2276
2277 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2278 {
2279         ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2280 }
2281
2282 /* ->val is filled in by kvm_sys_reg_table_init() */
2283 static struct sys_reg_desc invariant_sys_regs[] = {
2284         { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2285         { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
2286         { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2287         { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2288         { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
2289 };
2290
2291 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
2292 {
2293         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2294                 return -EFAULT;
2295         return 0;
2296 }
2297
2298 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
2299 {
2300         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2301                 return -EFAULT;
2302         return 0;
2303 }
2304
2305 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2306 {
2307         struct sys_reg_params params;
2308         const struct sys_reg_desc *r;
2309
2310         r = find_reg_by_id(id, &params, invariant_sys_regs,
2311                            ARRAY_SIZE(invariant_sys_regs));
2312         if (!r)
2313                 return -ENOENT;
2314
2315         return reg_to_user(uaddr, &r->val, id);
2316 }
2317
2318 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2319 {
2320         struct sys_reg_params params;
2321         const struct sys_reg_desc *r;
2322         int err;
2323         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2324
2325         r = find_reg_by_id(id, &params, invariant_sys_regs,
2326                            ARRAY_SIZE(invariant_sys_regs));
2327         if (!r)
2328                 return -ENOENT;
2329
2330         err = reg_from_user(&val, uaddr, id);
2331         if (err)
2332                 return err;
2333
2334         /* This is what we mean by invariant: you can't change it. */
2335         if (r->val != val)
2336                 return -EINVAL;
2337
2338         return 0;
2339 }
2340
2341 static bool is_valid_cache(u32 val)
2342 {
2343         u32 level, ctype;
2344
2345         if (val >= CSSELR_MAX)
2346                 return false;
2347
2348         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
2349         level = (val >> 1);
2350         ctype = (cache_levels >> (level * 3)) & 7;
2351
2352         switch (ctype) {
2353         case 0: /* No cache */
2354                 return false;
2355         case 1: /* Instruction cache only */
2356                 return (val & 1);
2357         case 2: /* Data cache only */
2358         case 4: /* Unified cache */
2359                 return !(val & 1);
2360         case 3: /* Separate instruction and data caches */
2361                 return true;
2362         default: /* Reserved: we can't know instruction or data. */
2363                 return false;
2364         }
2365 }
2366
2367 static int demux_c15_get(u64 id, void __user *uaddr)
2368 {
2369         u32 val;
2370         u32 __user *uval = uaddr;
2371
2372         /* Fail if we have unknown bits set. */
2373         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2374                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2375                 return -ENOENT;
2376
2377         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2378         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2379                 if (KVM_REG_SIZE(id) != 4)
2380                         return -ENOENT;
2381                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2382                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2383                 if (!is_valid_cache(val))
2384                         return -ENOENT;
2385
2386                 return put_user(get_ccsidr(val), uval);
2387         default:
2388                 return -ENOENT;
2389         }
2390 }
2391
2392 static int demux_c15_set(u64 id, void __user *uaddr)
2393 {
2394         u32 val, newval;
2395         u32 __user *uval = uaddr;
2396
2397         /* Fail if we have unknown bits set. */
2398         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2399                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2400                 return -ENOENT;
2401
2402         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2403         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2404                 if (KVM_REG_SIZE(id) != 4)
2405                         return -ENOENT;
2406                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2407                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2408                 if (!is_valid_cache(val))
2409                         return -ENOENT;
2410
2411                 if (get_user(newval, uval))
2412                         return -EFAULT;
2413
2414                 /* This is also invariant: you can't change it. */
2415                 if (newval != get_ccsidr(val))
2416                         return -EINVAL;
2417                 return 0;
2418         default:
2419                 return -ENOENT;
2420         }
2421 }
2422
2423 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2424 {
2425         const struct sys_reg_desc *r;
2426         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2427
2428         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2429                 return demux_c15_get(reg->id, uaddr);
2430
2431         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2432                 return -ENOENT;
2433
2434         r = index_to_sys_reg_desc(vcpu, reg->id);
2435         if (!r)
2436                 return get_invariant_sys_reg(reg->id, uaddr);
2437
2438         if (r->get_user)
2439                 return (r->get_user)(vcpu, r, reg, uaddr);
2440
2441         return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
2442 }
2443
2444 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2445 {
2446         const struct sys_reg_desc *r;
2447         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2448
2449         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2450                 return demux_c15_set(reg->id, uaddr);
2451
2452         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2453                 return -ENOENT;
2454
2455         r = index_to_sys_reg_desc(vcpu, reg->id);
2456         if (!r)
2457                 return set_invariant_sys_reg(reg->id, uaddr);
2458
2459         if (r->set_user)
2460                 return (r->set_user)(vcpu, r, reg, uaddr);
2461
2462         return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2463 }
2464
2465 static unsigned int num_demux_regs(void)
2466 {
2467         unsigned int i, count = 0;
2468
2469         for (i = 0; i < CSSELR_MAX; i++)
2470                 if (is_valid_cache(i))
2471                         count++;
2472
2473         return count;
2474 }
2475
2476 static int write_demux_regids(u64 __user *uindices)
2477 {
2478         u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2479         unsigned int i;
2480
2481         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2482         for (i = 0; i < CSSELR_MAX; i++) {
2483                 if (!is_valid_cache(i))
2484                         continue;
2485                 if (put_user(val | i, uindices))
2486                         return -EFAULT;
2487                 uindices++;
2488         }
2489         return 0;
2490 }
2491
2492 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2493 {
2494         return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2495                 KVM_REG_ARM64_SYSREG |
2496                 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2497                 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2498                 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2499                 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2500                 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2501 }
2502
2503 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2504 {
2505         if (!*uind)
2506                 return true;
2507
2508         if (put_user(sys_reg_to_index(reg), *uind))
2509                 return false;
2510
2511         (*uind)++;
2512         return true;
2513 }
2514
2515 static int walk_one_sys_reg(const struct sys_reg_desc *rd,
2516                             u64 __user **uind,
2517                             unsigned int *total)
2518 {
2519         /*
2520          * Ignore registers we trap but don't save,
2521          * and for which no custom user accessor is provided.
2522          */
2523         if (!(rd->reg || rd->get_user))
2524                 return 0;
2525
2526         if (!copy_reg_to_user(rd, uind))
2527                 return -EFAULT;
2528
2529         (*total)++;
2530         return 0;
2531 }
2532
2533 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2534 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2535 {
2536         const struct sys_reg_desc *i1, *i2, *end1, *end2;
2537         unsigned int total = 0;
2538         size_t num;
2539         int err;
2540
2541         /* We check for duplicates here, to allow arch-specific overrides. */
2542         i1 = get_target_table(vcpu->arch.target, true, &num);
2543         end1 = i1 + num;
2544         i2 = sys_reg_descs;
2545         end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2546
2547         BUG_ON(i1 == end1 || i2 == end2);
2548
2549         /* Walk carefully, as both tables may refer to the same register. */
2550         while (i1 || i2) {
2551                 int cmp = cmp_sys_reg(i1, i2);
2552                 /* target-specific overrides generic entry. */
2553                 if (cmp <= 0)
2554                         err = walk_one_sys_reg(i1, &uind, &total);
2555                 else
2556                         err = walk_one_sys_reg(i2, &uind, &total);
2557
2558                 if (err)
2559                         return err;
2560
2561                 if (cmp <= 0 && ++i1 == end1)
2562                         i1 = NULL;
2563                 if (cmp >= 0 && ++i2 == end2)
2564                         i2 = NULL;
2565         }
2566         return total;
2567 }
2568
2569 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2570 {
2571         return ARRAY_SIZE(invariant_sys_regs)
2572                 + num_demux_regs()
2573                 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2574 }
2575
2576 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2577 {
2578         unsigned int i;
2579         int err;
2580
2581         /* Then give them all the invariant registers' indices. */
2582         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2583                 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2584                         return -EFAULT;
2585                 uindices++;
2586         }
2587
2588         err = walk_sys_regs(vcpu, uindices);
2589         if (err < 0)
2590                 return err;
2591         uindices += err;
2592
2593         return write_demux_regids(uindices);
2594 }
2595
2596 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2597 {
2598         unsigned int i;
2599
2600         for (i = 1; i < n; i++) {
2601                 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2602                         kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2603                         return 1;
2604                 }
2605         }
2606
2607         return 0;
2608 }
2609
2610 void kvm_sys_reg_table_init(void)
2611 {
2612         unsigned int i;
2613         struct sys_reg_desc clidr;
2614
2615         /* Make sure tables are unique and in order. */
2616         BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2617         BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2618         BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2619         BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2620         BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2621         BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
2622
2623         /* We abuse the reset function to overwrite the table itself. */
2624         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2625                 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2626
2627         /*
2628          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
2629          *
2630          *   If software reads the Cache Type fields from Ctype1
2631          *   upwards, once it has seen a value of 0b000, no caches
2632          *   exist at further-out levels of the hierarchy. So, for
2633          *   example, if Ctype3 is the first Cache Type field with a
2634          *   value of 0b000, the values of Ctype4 to Ctype7 must be
2635          *   ignored.
2636          */
2637         get_clidr_el1(NULL, &clidr); /* Ugly... */
2638         cache_levels = clidr.val;
2639         for (i = 0; i < 7; i++)
2640                 if (((cache_levels >> (i*3)) & 7) == 0)
2641                         break;
2642         /* Clear all higher bits. */
2643         cache_levels &= (1 << (i*3))-1;
2644 }
2645
2646 /**
2647  * kvm_reset_sys_regs - sets system registers to reset value
2648  * @vcpu: The VCPU pointer
2649  *
2650  * This function finds the right table above and sets the registers on the
2651  * virtual CPU struct to their architecturally defined reset values.
2652  */
2653 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2654 {
2655         size_t num;
2656         const struct sys_reg_desc *table;
2657
2658         /* Catch someone adding a register without putting in reset entry. */
2659         memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
2660
2661         /* Generic chip reset first (so target could override). */
2662         reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2663
2664         table = get_target_table(vcpu->arch.target, true, &num);
2665         reset_sys_reg_descs(vcpu, table, num);
2666
2667         for (num = 1; num < NR_SYS_REGS; num++) {
2668                 if (WARN(__vcpu_sys_reg(vcpu, num) == 0x4242424242424242,
2669                          "Didn't reset __vcpu_sys_reg(%zi)\n", num))
2670                         break;
2671         }
2672 }