1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/process.c
5 * Original Copyright (C) 1995 Linus Torvalds
6 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
7 * Copyright (C) 2012 ARM Ltd.
9 #include <linux/compat.h>
10 #include <linux/efi.h>
11 #include <linux/elf.h>
12 #include <linux/export.h>
13 #include <linux/sched.h>
14 #include <linux/sched/debug.h>
15 #include <linux/sched/task.h>
16 #include <linux/sched/task_stack.h>
17 #include <linux/kernel.h>
18 #include <linux/mman.h>
20 #include <linux/nospec.h>
21 #include <linux/stddef.h>
22 #include <linux/sysctl.h>
23 #include <linux/unistd.h>
24 #include <linux/user.h>
25 #include <linux/delay.h>
26 #include <linux/reboot.h>
27 #include <linux/interrupt.h>
28 #include <linux/init.h>
29 #include <linux/cpu.h>
30 #include <linux/elfcore.h>
32 #include <linux/tick.h>
33 #include <linux/utsname.h>
34 #include <linux/uaccess.h>
35 #include <linux/random.h>
36 #include <linux/hw_breakpoint.h>
37 #include <linux/personality.h>
38 #include <linux/notifier.h>
39 #include <trace/events/power.h>
40 #include <linux/percpu.h>
41 #include <linux/thread_info.h>
42 #include <linux/prctl.h>
43 #include <linux/stacktrace.h>
45 #include <asm/alternative.h>
46 #include <asm/compat.h>
47 #include <asm/cpufeature.h>
48 #include <asm/cacheflush.h>
50 #include <asm/fpsimd.h>
51 #include <asm/mmu_context.h>
53 #include <asm/processor.h>
54 #include <asm/pointer_auth.h>
55 #include <asm/stacktrace.h>
56 #include <asm/switch_to.h>
57 #include <asm/system_misc.h>
59 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
60 #include <linux/stackprotector.h>
61 unsigned long __stack_chk_guard __ro_after_init;
62 EXPORT_SYMBOL(__stack_chk_guard);
66 * Function pointers to optional machine specific functions
68 void (*pm_power_off)(void);
69 EXPORT_SYMBOL_GPL(pm_power_off);
71 #ifdef CONFIG_HOTPLUG_CPU
72 void arch_cpu_idle_dead(void)
79 * Called by kexec, immediately prior to machine_kexec().
81 * This must completely disable all secondary CPUs; simply causing those CPUs
82 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
83 * kexec'd kernel to use any and all RAM as it sees fit, without having to
84 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
85 * functionality embodied in smpt_shutdown_nonboot_cpus() to achieve this.
87 void machine_shutdown(void)
89 smp_shutdown_nonboot_cpus(reboot_cpu);
93 * Halting simply requires that the secondary CPUs stop performing any
94 * activity (executing tasks, handling interrupts). smp_send_stop()
97 void machine_halt(void)
105 * Power-off simply requires that the secondary CPUs stop performing any
106 * activity (executing tasks, handling interrupts). smp_send_stop()
107 * achieves this. When the system power is turned off, it will take all CPUs
110 void machine_power_off(void)
114 do_kernel_power_off();
118 * Restart requires that the secondary CPUs stop performing any activity
119 * while the primary CPU resets the system. Systems with multiple CPUs must
120 * provide a HW restart implementation, to ensure that all CPUs reset at once.
121 * This is required so that any code running after reset on the primary CPU
122 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
123 * executing pre-reset code, and using RAM that the primary CPU's code wishes
124 * to use. Implementing such co-ordination would be essentially impossible.
126 void machine_restart(char *cmd)
128 /* Disable interrupts first */
133 * UpdateCapsule() depends on the system being reset via
136 if (efi_enabled(EFI_RUNTIME_SERVICES))
137 efi_reboot(reboot_mode, NULL);
139 /* Now call the architecture specific reboot code. */
140 do_kernel_restart(cmd);
143 * Whoops - the architecture was unable to reboot.
145 printk("Reboot failed -- System halted\n");
149 #define bstr(suffix, str) [PSR_BTYPE_ ## suffix >> PSR_BTYPE_SHIFT] = str
150 static const char *const btypes[] = {
158 static void print_pstate(struct pt_regs *regs)
160 u64 pstate = regs->pstate;
162 if (compat_user_mode(regs)) {
163 printk("pstate: %08llx (%c%c%c%c %c %s %s %c%c%c %cDIT %cSSBS)\n",
165 pstate & PSR_AA32_N_BIT ? 'N' : 'n',
166 pstate & PSR_AA32_Z_BIT ? 'Z' : 'z',
167 pstate & PSR_AA32_C_BIT ? 'C' : 'c',
168 pstate & PSR_AA32_V_BIT ? 'V' : 'v',
169 pstate & PSR_AA32_Q_BIT ? 'Q' : 'q',
170 pstate & PSR_AA32_T_BIT ? "T32" : "A32",
171 pstate & PSR_AA32_E_BIT ? "BE" : "LE",
172 pstate & PSR_AA32_A_BIT ? 'A' : 'a',
173 pstate & PSR_AA32_I_BIT ? 'I' : 'i',
174 pstate & PSR_AA32_F_BIT ? 'F' : 'f',
175 pstate & PSR_AA32_DIT_BIT ? '+' : '-',
176 pstate & PSR_AA32_SSBS_BIT ? '+' : '-');
178 const char *btype_str = btypes[(pstate & PSR_BTYPE_MASK) >>
181 printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO %cTCO %cDIT %cSSBS BTYPE=%s)\n",
183 pstate & PSR_N_BIT ? 'N' : 'n',
184 pstate & PSR_Z_BIT ? 'Z' : 'z',
185 pstate & PSR_C_BIT ? 'C' : 'c',
186 pstate & PSR_V_BIT ? 'V' : 'v',
187 pstate & PSR_D_BIT ? 'D' : 'd',
188 pstate & PSR_A_BIT ? 'A' : 'a',
189 pstate & PSR_I_BIT ? 'I' : 'i',
190 pstate & PSR_F_BIT ? 'F' : 'f',
191 pstate & PSR_PAN_BIT ? '+' : '-',
192 pstate & PSR_UAO_BIT ? '+' : '-',
193 pstate & PSR_TCO_BIT ? '+' : '-',
194 pstate & PSR_DIT_BIT ? '+' : '-',
195 pstate & PSR_SSBS_BIT ? '+' : '-',
200 void __show_regs(struct pt_regs *regs)
205 if (compat_user_mode(regs)) {
206 lr = regs->compat_lr;
207 sp = regs->compat_sp;
215 show_regs_print_info(KERN_DEFAULT);
218 if (!user_mode(regs)) {
219 printk("pc : %pS\n", (void *)regs->pc);
220 printk("lr : %pS\n", (void *)ptrauth_strip_insn_pac(lr));
222 printk("pc : %016llx\n", regs->pc);
223 printk("lr : %016llx\n", lr);
226 printk("sp : %016llx\n", sp);
228 if (system_uses_irq_prio_masking())
229 printk("pmr_save: %08llx\n", regs->pmr_save);
234 printk("x%-2d: %016llx", i, regs->regs[i]);
237 pr_cont(" x%-2d: %016llx", i, regs->regs[i]);
243 void show_regs(struct pt_regs *regs)
246 dump_backtrace(regs, NULL, KERN_DEFAULT);
249 static void tls_thread_flush(void)
251 write_sysreg(0, tpidr_el0);
252 if (system_supports_tpidr2())
253 write_sysreg_s(0, SYS_TPIDR2_EL0);
255 if (is_compat_task()) {
256 current->thread.uw.tp_value = 0;
259 * We need to ensure ordering between the shadow state and the
260 * hardware state, so that we don't corrupt the hardware state
261 * with a stale shadow state during context switch.
264 write_sysreg(0, tpidrro_el0);
268 static void flush_tagged_addr_state(void)
270 if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI))
271 clear_thread_flag(TIF_TAGGED_ADDR);
274 void flush_thread(void)
276 fpsimd_flush_thread();
278 flush_ptrace_hw_breakpoint(current);
279 flush_tagged_addr_state();
282 void arch_release_task_struct(struct task_struct *tsk)
284 fpsimd_release_task(tsk);
287 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
290 fpsimd_preserve_current_state();
293 /* We rely on the above assignment to initialize dst's thread_flags: */
294 BUILD_BUG_ON(!IS_ENABLED(CONFIG_THREAD_INFO_IN_TASK));
297 * Detach src's sve_state (if any) from dst so that it does not
298 * get erroneously used or freed prematurely. dst's copies
299 * will be allocated on demand later on if dst uses SVE.
300 * For consistency, also clear TIF_SVE here: this could be done
301 * later in copy_process(), but to avoid tripping up future
302 * maintainers it is best not to leave TIF flags and buffers in
303 * an inconsistent state, even temporarily.
305 dst->thread.sve_state = NULL;
306 clear_tsk_thread_flag(dst, TIF_SVE);
309 * In the unlikely event that we create a new thread with ZA
310 * enabled we should retain the ZA state so duplicate it here.
311 * This may be shortly freed if we exec() or if CLONE_SETTLS
312 * but it's simpler to do it here. To avoid confusing the rest
313 * of the code ensure that we have a sve_state allocated
314 * whenever za_state is allocated.
316 if (thread_za_enabled(&src->thread)) {
317 dst->thread.sve_state = kzalloc(sve_state_size(src),
319 if (!dst->thread.sve_state)
321 dst->thread.za_state = kmemdup(src->thread.za_state,
324 if (!dst->thread.za_state) {
325 kfree(dst->thread.sve_state);
326 dst->thread.sve_state = NULL;
330 dst->thread.za_state = NULL;
331 clear_tsk_thread_flag(dst, TIF_SME);
334 /* clear any pending asynchronous tag fault raised by the parent */
335 clear_tsk_thread_flag(dst, TIF_MTE_ASYNC_FAULT);
340 asmlinkage void ret_from_fork(void) asm("ret_from_fork");
342 int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
344 unsigned long clone_flags = args->flags;
345 unsigned long stack_start = args->stack;
346 unsigned long tls = args->tls;
347 struct pt_regs *childregs = task_pt_regs(p);
349 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
352 * In case p was allocated the same task_struct pointer as some
353 * other recently-exited task, make sure p is disassociated from
354 * any cpu that may have run that now-exited task recently.
355 * Otherwise we could erroneously skip reloading the FPSIMD
358 fpsimd_flush_task_state(p);
360 ptrauth_thread_init_kernel(p);
362 if (likely(!args->fn)) {
363 *childregs = *current_pt_regs();
364 childregs->regs[0] = 0;
367 * Read the current TLS pointer from tpidr_el0 as it may be
368 * out-of-sync with the saved value.
370 *task_user_tls(p) = read_sysreg(tpidr_el0);
371 if (system_supports_tpidr2())
372 p->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
375 if (is_compat_thread(task_thread_info(p)))
376 childregs->compat_sp = stack_start;
378 childregs->sp = stack_start;
382 * If a TLS pointer was passed to clone, use it for the new
383 * thread. We also reset TPIDR2 if it's in use.
385 if (clone_flags & CLONE_SETTLS) {
386 p->thread.uw.tp_value = tls;
387 p->thread.tpidr2_el0 = 0;
391 * A kthread has no context to ERET to, so ensure any buggy
392 * ERET is treated as an illegal exception return.
394 * When a user task is created from a kthread, childregs will
395 * be initialized by start_thread() or start_compat_thread().
397 memset(childregs, 0, sizeof(struct pt_regs));
398 childregs->pstate = PSR_MODE_EL1h | PSR_IL_BIT;
400 p->thread.cpu_context.x19 = (unsigned long)args->fn;
401 p->thread.cpu_context.x20 = (unsigned long)args->fn_arg;
403 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
404 p->thread.cpu_context.sp = (unsigned long)childregs;
406 * For the benefit of the unwinder, set up childregs->stackframe
407 * as the final frame for the new task.
409 p->thread.cpu_context.fp = (unsigned long)childregs->stackframe;
411 ptrace_hw_copy_thread(p);
416 void tls_preserve_current_state(void)
418 *task_user_tls(current) = read_sysreg(tpidr_el0);
419 if (system_supports_tpidr2() && !is_compat_task())
420 current->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
423 static void tls_thread_switch(struct task_struct *next)
425 tls_preserve_current_state();
427 if (is_compat_thread(task_thread_info(next)))
428 write_sysreg(next->thread.uw.tp_value, tpidrro_el0);
429 else if (!arm64_kernel_unmapped_at_el0())
430 write_sysreg(0, tpidrro_el0);
432 write_sysreg(*task_user_tls(next), tpidr_el0);
433 if (system_supports_tpidr2())
434 write_sysreg_s(next->thread.tpidr2_el0, SYS_TPIDR2_EL0);
438 * Force SSBS state on context-switch, since it may be lost after migrating
439 * from a CPU which treats the bit as RES0 in a heterogeneous system.
441 static void ssbs_thread_switch(struct task_struct *next)
444 * Nothing to do for kernel threads, but 'regs' may be junk
445 * (e.g. idle task) so check the flags and bail early.
447 if (unlikely(next->flags & PF_KTHREAD))
451 * If all CPUs implement the SSBS extension, then we just need to
452 * context-switch the PSTATE field.
454 if (cpus_have_const_cap(ARM64_SSBS))
457 spectre_v4_enable_task_mitigation(next);
461 * We store our current task in sp_el0, which is clobbered by userspace. Keep a
462 * shadow copy so that we can restore this upon entry from userspace.
464 * This is *only* for exception entry from EL0, and is not valid until we
465 * __switch_to() a user task.
467 DEFINE_PER_CPU(struct task_struct *, __entry_task);
469 static void entry_task_switch(struct task_struct *next)
471 __this_cpu_write(__entry_task, next);
475 * ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT.
476 * Ensure access is disabled when switching to a 32bit task, ensure
477 * access is enabled when switching to a 64bit task.
479 static void erratum_1418040_thread_switch(struct task_struct *next)
481 if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040) ||
482 !this_cpu_has_cap(ARM64_WORKAROUND_1418040))
485 if (is_compat_thread(task_thread_info(next)))
486 sysreg_clear_set(cntkctl_el1, ARCH_TIMER_USR_VCT_ACCESS_EN, 0);
488 sysreg_clear_set(cntkctl_el1, 0, ARCH_TIMER_USR_VCT_ACCESS_EN);
491 static void erratum_1418040_new_exec(void)
494 erratum_1418040_thread_switch(current);
499 * __switch_to() checks current->thread.sctlr_user as an optimisation. Therefore
500 * this function must be called with preemption disabled and the update to
501 * sctlr_user must be made in the same preemption disabled block so that
502 * __switch_to() does not see the variable update before the SCTLR_EL1 one.
504 void update_sctlr_el1(u64 sctlr)
507 * EnIA must not be cleared while in the kernel as this is necessary for
508 * in-kernel PAC. It will be cleared on kernel exit if needed.
510 sysreg_clear_set(sctlr_el1, SCTLR_USER_MASK & ~SCTLR_ELx_ENIA, sctlr);
512 /* ISB required for the kernel uaccess routines when setting TCF0. */
519 __notrace_funcgraph __sched
520 struct task_struct *__switch_to(struct task_struct *prev,
521 struct task_struct *next)
523 struct task_struct *last;
525 fpsimd_thread_switch(next);
526 tls_thread_switch(next);
527 hw_breakpoint_thread_switch(next);
528 contextidr_thread_switch(next);
529 entry_task_switch(next);
530 ssbs_thread_switch(next);
531 erratum_1418040_thread_switch(next);
532 ptrauth_thread_switch_user(next);
535 * Complete any pending TLB or cache maintenance on this CPU in case
536 * the thread migrates to a different CPU.
537 * This full barrier is also required by the membarrier system
543 * MTE thread switching must happen after the DSB above to ensure that
544 * any asynchronous tag check faults have been logged in the TFSR*_EL1
547 mte_thread_switch(next);
548 /* avoid expensive SCTLR_EL1 accesses if no change */
549 if (prev->thread.sctlr_user != next->thread.sctlr_user)
550 update_sctlr_el1(next->thread.sctlr_user);
552 /* the actual thread switch */
553 last = cpu_switch_to(prev, next);
563 static bool get_wchan_cb(void *arg, unsigned long pc)
565 struct wchan_info *wchan_info = arg;
567 if (!in_sched_functions(pc)) {
571 return wchan_info->count++ < 16;
574 unsigned long __get_wchan(struct task_struct *p)
576 struct wchan_info wchan_info = {
581 if (!try_get_task_stack(p))
584 arch_stack_walk(get_wchan_cb, &wchan_info, p, NULL);
588 return wchan_info.pc;
591 unsigned long arch_align_stack(unsigned long sp)
593 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
594 sp -= prandom_u32_max(PAGE_SIZE);
599 int compat_elf_check_arch(const struct elf32_hdr *hdr)
601 if (!system_supports_32bit_el0())
604 if ((hdr)->e_machine != EM_ARM)
607 if (!((hdr)->e_flags & EF_ARM_EABI_MASK))
611 * Prevent execve() of a 32-bit program from a deadline task
612 * if the restricted affinity mask would be inadmissible on an
615 return !static_branch_unlikely(&arm64_mismatched_32bit_el0) ||
616 !dl_task_check_affinity(current, system_32bit_el0_cpumask());
621 * Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY.
623 void arch_setup_new_exec(void)
625 unsigned long mmflags = 0;
627 if (is_compat_task()) {
628 mmflags = MMCF_AARCH32;
631 * Restrict the CPU affinity mask for a 32-bit task so that
632 * it contains only 32-bit-capable CPUs.
634 * From the perspective of the task, this looks similar to
635 * what would happen if the 64-bit-only CPUs were hot-unplugged
636 * at the point of execve(), although we try a bit harder to
637 * honour the cpuset hierarchy.
639 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
640 force_compatible_cpus_allowed_ptr(current);
641 } else if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) {
642 relax_compatible_cpus_allowed_ptr(current);
645 current->mm->context.flags = mmflags;
646 ptrauth_thread_init_user();
647 mte_thread_init_user();
648 erratum_1418040_new_exec();
650 if (task_spec_ssb_noexec(current)) {
651 arch_prctl_spec_ctrl_set(current, PR_SPEC_STORE_BYPASS,
656 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
658 * Control the relaxed ABI allowing tagged user addresses into the kernel.
660 static unsigned int tagged_addr_disabled;
662 long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg)
664 unsigned long valid_mask = PR_TAGGED_ADDR_ENABLE;
665 struct thread_info *ti = task_thread_info(task);
667 if (is_compat_thread(ti))
670 if (system_supports_mte())
671 valid_mask |= PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC \
674 if (arg & ~valid_mask)
678 * Do not allow the enabling of the tagged address ABI if globally
679 * disabled via sysctl abi.tagged_addr_disabled.
681 if (arg & PR_TAGGED_ADDR_ENABLE && tagged_addr_disabled)
684 if (set_mte_ctrl(task, arg) != 0)
687 update_ti_thread_flag(ti, TIF_TAGGED_ADDR, arg & PR_TAGGED_ADDR_ENABLE);
692 long get_tagged_addr_ctrl(struct task_struct *task)
695 struct thread_info *ti = task_thread_info(task);
697 if (is_compat_thread(ti))
700 if (test_ti_thread_flag(ti, TIF_TAGGED_ADDR))
701 ret = PR_TAGGED_ADDR_ENABLE;
703 ret |= get_mte_ctrl(task);
709 * Global sysctl to disable the tagged user addresses support. This control
710 * only prevents the tagged address ABI enabling via prctl() and does not
711 * disable it for tasks that already opted in to the relaxed ABI.
714 static struct ctl_table tagged_addr_sysctl_table[] = {
716 .procname = "tagged_addr_disabled",
718 .data = &tagged_addr_disabled,
719 .maxlen = sizeof(int),
720 .proc_handler = proc_dointvec_minmax,
721 .extra1 = SYSCTL_ZERO,
722 .extra2 = SYSCTL_ONE,
727 static int __init tagged_addr_init(void)
729 if (!register_sysctl("abi", tagged_addr_sysctl_table))
734 core_initcall(tagged_addr_init);
735 #endif /* CONFIG_ARM64_TAGGED_ADDR_ABI */
737 #ifdef CONFIG_BINFMT_ELF
738 int arch_elf_adjust_prot(int prot, const struct arch_elf_state *state,
739 bool has_interp, bool is_interp)
742 * For dynamically linked executables the interpreter is
743 * responsible for setting PROT_BTI on everything except
746 if (is_interp != has_interp)
749 if (!(state->flags & ARM64_ELF_BTI))
752 if (prot & PROT_EXEC)