2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/linkage.h>
24 #include <linux/init.h>
26 #include <asm/assembler.h>
27 #include <asm/ptrace.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cache.h>
30 #include <asm/cputype.h>
31 #include <asm/memory.h>
32 #include <asm/thread_info.h>
33 #include <asm/pgtable-hwdef.h>
34 #include <asm/pgtable.h>
38 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
40 #if (TEXT_OFFSET & 0xf) != 0
41 #error TEXT_OFFSET must be at least 16B aligned
42 #elif (PAGE_OFFSET & 0xfffff) != 0
43 #error PAGE_OFFSET must be at least 2MB aligned
44 #elif TEXT_OFFSET > 0xfffff
45 #error TEXT_OFFSET must be less than 2MB
48 .macro pgtbl, ttb0, ttb1, virt_to_phys
49 ldr \ttb1, =swapper_pg_dir
50 ldr \ttb0, =idmap_pg_dir
51 add \ttb1, \ttb1, \virt_to_phys
52 add \ttb0, \ttb0, \virt_to_phys
55 #ifdef CONFIG_ARM64_64K_PAGES
56 #define BLOCK_SHIFT PAGE_SHIFT
57 #define BLOCK_SIZE PAGE_SIZE
59 #define BLOCK_SHIFT SECTION_SHIFT
60 #define BLOCK_SIZE SECTION_SIZE
63 #define KERNEL_START KERNEL_RAM_VADDR
64 #define KERNEL_END _end
67 * Initial memory map attributes.
70 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF
71 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF
73 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
74 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
77 #ifdef CONFIG_ARM64_64K_PAGES
78 #define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
80 #define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
84 * Kernel startup entry point.
85 * ---------------------------
87 * The requirements are:
88 * MMU = off, D-cache = off, I-cache = on or off,
89 * x0 = physical address to the FDT blob.
91 * This code is mostly position independent so you call this at
92 * __pa(PAGE_OFFSET + TEXT_OFFSET).
94 * Note that the callee-saved registers are used for storing variables
95 * that are useful before the MMU is enabled. The allocations are described
96 * in the entry routines.
101 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
106 * This add instruction has no meaningful effect except that
107 * its opcode forms the magic "MZ" signature required by UEFI.
112 b stext // branch to kernel start, magic
115 .quad _kernel_offset_le // Image load offset from start of RAM, little-endian
116 .quad _kernel_size_le // Effective size of kernel image, little-endian
117 .quad _kernel_flags_le // Informative flags, little-endian
121 .byte 0x41 // Magic number, "ARM\x64"
126 .long pe_header - efi_head // Offset to the PE header.
137 .short 0xaa64 // AArch64
138 .short 2 // nr_sections
139 .long 0 // TimeDateStamp
140 .long 0 // PointerToSymbolTable
141 .long 1 // NumberOfSymbols
142 .short section_table - optional_header // SizeOfOptionalHeader
143 .short 0x206 // Characteristics.
144 // IMAGE_FILE_DEBUG_STRIPPED |
145 // IMAGE_FILE_EXECUTABLE_IMAGE |
146 // IMAGE_FILE_LINE_NUMS_STRIPPED
148 .short 0x20b // PE32+ format
149 .byte 0x02 // MajorLinkerVersion
150 .byte 0x14 // MinorLinkerVersion
151 .long _edata - stext // SizeOfCode
152 .long 0 // SizeOfInitializedData
153 .long 0 // SizeOfUninitializedData
154 .long efi_stub_entry - efi_head // AddressOfEntryPoint
155 .long stext - efi_head // BaseOfCode
159 .long 0x20 // SectionAlignment
160 .long 0x8 // FileAlignment
161 .short 0 // MajorOperatingSystemVersion
162 .short 0 // MinorOperatingSystemVersion
163 .short 0 // MajorImageVersion
164 .short 0 // MinorImageVersion
165 .short 0 // MajorSubsystemVersion
166 .short 0 // MinorSubsystemVersion
167 .long 0 // Win32VersionValue
169 .long _edata - efi_head // SizeOfImage
171 // Everything before the kernel image is considered part of the header
172 .long stext - efi_head // SizeOfHeaders
174 .short 0xa // Subsystem (EFI application)
175 .short 0 // DllCharacteristics
176 .quad 0 // SizeOfStackReserve
177 .quad 0 // SizeOfStackCommit
178 .quad 0 // SizeOfHeapReserve
179 .quad 0 // SizeOfHeapCommit
180 .long 0 // LoaderFlags
181 .long 0x6 // NumberOfRvaAndSizes
183 .quad 0 // ExportTable
184 .quad 0 // ImportTable
185 .quad 0 // ResourceTable
186 .quad 0 // ExceptionTable
187 .quad 0 // CertificationTable
188 .quad 0 // BaseRelocationTable
194 * The EFI application loader requires a relocation section
195 * because EFI applications must be relocatable. This is a
196 * dummy section as far as we are concerned.
200 .byte 0 // end of 0 padding of section name
203 .long 0 // SizeOfRawData
204 .long 0 // PointerToRawData
205 .long 0 // PointerToRelocations
206 .long 0 // PointerToLineNumbers
207 .short 0 // NumberOfRelocations
208 .short 0 // NumberOfLineNumbers
209 .long 0x42100040 // Characteristics (section flags)
215 .byte 0 // end of 0 padding of section name
216 .long _edata - stext // VirtualSize
217 .long stext - efi_head // VirtualAddress
218 .long _edata - stext // SizeOfRawData
219 .long stext - efi_head // PointerToRawData
221 .long 0 // PointerToRelocations (0 for executables)
222 .long 0 // PointerToLineNumbers (0 for executables)
223 .short 0 // NumberOfRelocations (0 for executables)
224 .short 0 // NumberOfLineNumbers (0 for executables)
225 .long 0xe0500020 // Characteristics (section flags)
230 mov x21, x0 // x21=FDT
231 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
232 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
233 bl set_cpu_boot_mode_flag
234 mrs x22, midr_el1 // x22=cpuid
236 bl lookup_processor_type
237 mov x23, x0 // x23=current cpu_table
238 cbz x23, __error_p // invalid processor (x23=0)?
240 bl __create_page_tables // x25=TTBR0, x26=TTBR1
242 * The following calls CPU specific code in a position independent
243 * manner. See arch/arm64/mm/proc.S for details. x23 = base of
244 * cpu_info structure selected by lookup_processor_type above.
245 * On return, the CPU will be ready for the MMU to be turned on and
246 * the TCR will have been set.
248 ldr x27, __switch_data // address to jump to after
249 // MMU has been enabled
250 adr lr, __enable_mmu // return (PIC) address
251 ldr x12, [x23, #CPU_INFO_SETUP]
252 add x12, x12, x28 // __virt_to_phys
253 br x12 // initialise processor
257 * If we're fortunate enough to boot at EL2, ensure that the world is
258 * sane before dropping to EL1.
260 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
261 * booted in EL1 or EL2 respectively.
265 cmp x0, #CurrentEL_EL2
268 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
269 CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
273 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
274 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
276 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
280 /* Hyp configuration. */
281 2: mov x0, #(1 << 31) // 64-bit EL1
284 /* Generic timers. */
286 orr x0, x0, #3 // Enable EL1 physical timers
288 msr cntvoff_el2, xzr // Clear virtual offset
290 /* Populate ID registers. */
297 mov x0, #0x0800 // Set/clear RES{1,0} bits
298 CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
299 CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
302 /* Coprocessor traps. */
304 msr cptr_el2, x0 // Disable copro. traps to EL2
307 msr hstr_el2, xzr // Disable CP15 traps to EL2
310 /* Stage-2 translation */
313 /* Hypervisor stub */
314 adr x0, __hyp_stub_vectors
318 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
322 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
327 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
328 * in x20. See arch/arm64/include/asm/virt.h for more info.
330 ENTRY(set_cpu_boot_mode_flag)
331 ldr x1, =__boot_cpu_mode // Compute __boot_cpu_mode
333 cmp w20, #BOOT_CPU_MODE_EL2
336 1: str w20, [x1] // This CPU has booted in EL1
338 dc ivac, x1 // Invalidate potentially stale cache line
340 ENDPROC(set_cpu_boot_mode_flag)
343 * We need to find out the CPU boot mode long after boot, so we need to
344 * store it in a writable variable.
346 * This is not in .bss, because we set it sufficiently early that the boot-time
347 * zeroing of .bss would clobber it.
349 .pushsection .data..cacheline_aligned
350 ENTRY(__boot_cpu_mode)
351 .align L1_CACHE_SHIFT
352 .long BOOT_CPU_MODE_EL2
363 .quad secondary_holding_pen_release
366 * This provides a "holding pen" for platforms to hold all secondary
367 * cores are held until we're ready for them to initialise.
369 ENTRY(secondary_holding_pen)
370 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
371 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
372 bl set_cpu_boot_mode_flag
374 ldr x1, =MPIDR_HWID_BITMASK
382 b.eq secondary_startup
385 ENDPROC(secondary_holding_pen)
388 * Secondary entry point that jumps straight into the kernel. Only to
389 * be used where CPUs are brought online dynamically by the kernel.
391 ENTRY(secondary_entry)
392 bl el2_setup // Drop to EL1
393 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
394 bl set_cpu_boot_mode_flag
396 ENDPROC(secondary_entry)
398 ENTRY(secondary_startup)
400 * Common entry point for secondary CPUs.
402 mrs x22, midr_el1 // x22=cpuid
404 bl lookup_processor_type
405 mov x23, x0 // x23=current cpu_table
406 cbz x23, __error_p // invalid processor (x23=0)?
408 pgtbl x25, x26, x28 // x25=TTBR0, x26=TTBR1
409 ldr x12, [x23, #CPU_INFO_SETUP]
410 add x12, x12, x28 // __virt_to_phys
411 blr x12 // initialise processor
413 ldr x21, =secondary_data
414 ldr x27, =__secondary_switched // address to jump to after enabling the MMU
416 ENDPROC(secondary_startup)
418 ENTRY(__secondary_switched)
419 ldr x0, [x21] // get secondary_data.stack
422 b secondary_start_kernel
423 ENDPROC(__secondary_switched)
424 #endif /* CONFIG_SMP */
427 * Setup common bits before finally enabling the MMU. Essentially this is just
428 * loading the page table pointer and vector base registers.
430 * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
436 msr ttbr0_el1, x25 // load TTBR0
437 msr ttbr1_el1, x26 // load TTBR1
440 ENDPROC(__enable_mmu)
443 * Enable the MMU. This completely changes the structure of the visible memory
444 * space. You will not be able to trace execution through this.
446 * x0 = system control register
447 * x27 = *virtual* address to jump to upon completion
449 * other registers depend on the function called upon completion
451 * We align the entire function to the smallest power of two larger than it to
452 * ensure it fits within a single block map entry. Otherwise were PHYS_OFFSET
453 * close to the end of a 512MB or 1GB block we might require an additional
454 * table to map the entire function.
461 ENDPROC(__turn_mmu_on)
464 * Calculate the start of physical memory.
469 sub x28, x0, x1 // x28 = PHYS_OFFSET - PAGE_OFFSET
470 add x24, x2, x28 // x24 = PHYS_OFFSET
472 ENDPROC(__calc_phys_offset)
479 * Macro to populate the PUD for the corresponding block entry in the next
480 * level (tbl) for the given virtual address in case of 4 levels.
482 * Preserves: pgd, virt
483 * Corrupts: tbl, tmp1, tmp2
486 .macro create_pud_entry, pgd, tbl, virt, pud, tmp1, tmp2
487 #ifdef CONFIG_ARM64_4_LEVELS
488 add \tbl, \tbl, #PAGE_SIZE // bump tbl 1 page up.
489 // to make room for pud
490 add \pud, \pgd, #PAGE_SIZE // pgd points to pud which
492 lsr \tmp1, \virt, #PUD_SHIFT
493 and \tmp1, \tmp1, #PTRS_PER_PUD - 1 // PUD index
494 orr \tmp2, \tbl, #3 // PUD entry table type
495 str \tmp2, [\pud, \tmp1, lsl #3]
502 * Macro to populate the PGD (and possibily PUD) for the corresponding
503 * block entry in the next level (tbl) for the given virtual address.
505 * Preserves: pgd, virt
506 * Corrupts: tmp1, tmp2, tmp3
507 * Returns: tbl -> page where block mappings can be placed
508 * (changed to make room for pud with 4 levels, preserved otherwise)
510 .macro create_pgd_entry, pgd, tbl, virt, tmp1, tmp2, tmp3
511 create_pud_entry \pgd, \tbl, \virt, \tmp3, \tmp1, \tmp2
512 lsr \tmp1, \virt, #PGDIR_SHIFT
513 and \tmp1, \tmp1, #PTRS_PER_PGD - 1 // PGD index
514 orr \tmp2, \tmp3, #3 // PGD entry table type
515 str \tmp2, [\pgd, \tmp1, lsl #3]
519 * Macro to populate block entries in the page table for the start..end
520 * virtual range (inclusive).
522 * Preserves: tbl, flags
523 * Corrupts: phys, start, end, pstate
525 .macro create_block_map, tbl, flags, phys, start, end
526 lsr \phys, \phys, #BLOCK_SHIFT
527 lsr \start, \start, #BLOCK_SHIFT
528 and \start, \start, #PTRS_PER_PTE - 1 // table index
529 orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry
530 lsr \end, \end, #BLOCK_SHIFT
531 and \end, \end, #PTRS_PER_PTE - 1 // table end index
532 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
533 add \start, \start, #1 // next entry
534 add \phys, \phys, #BLOCK_SIZE // next block
540 * Setup the initial page tables. We only setup the barest amount which is
541 * required to get the kernel running. The following sections are required:
542 * - identity mapping to enable the MMU (low address, TTBR0)
543 * - first few MB of the kernel linear mapping to jump to once the MMU has
544 * been enabled, including the FDT blob (TTBR1)
545 * - pgd entry for fixed mappings (TTBR1)
547 __create_page_tables:
548 pgtbl x25, x26, x28 // idmap_pg_dir and swapper_pg_dir addresses
552 * Invalidate the idmap and swapper page tables to avoid potential
553 * dirty cache lines being evicted.
556 add x1, x26, #SWAPPER_DIR_SIZE
557 bl __inval_cache_range
560 * Clear the idmap and swapper page tables.
563 add x6, x26, #SWAPPER_DIR_SIZE
564 1: stp xzr, xzr, [x0], #16
565 stp xzr, xzr, [x0], #16
566 stp xzr, xzr, [x0], #16
567 stp xzr, xzr, [x0], #16
574 * Create the identity mapping.
576 add x0, x25, #PAGE_SIZE // section table address
577 ldr x3, =KERNEL_START
578 add x3, x3, x28 // __pa(KERNEL_START)
579 create_pgd_entry x25, x0, x3, x1, x5, x6
581 mov x5, x3 // __pa(KERNEL_START)
582 add x6, x6, x28 // __pa(KERNEL_END)
583 create_block_map x0, x7, x3, x5, x6
586 * Map the kernel image (starting with PHYS_OFFSET).
588 add x0, x26, #PAGE_SIZE // section table address
590 create_pgd_entry x26, x0, x5, x1, x3, x6
592 mov x3, x24 // phys offset
593 create_block_map x0, x7, x3, x5, x6
596 * Map the FDT blob (maximum 2MB; must be within 512MB of
599 mov x3, x21 // FDT phys address
600 and x3, x3, #~((1 << 21) - 1) // 2MB aligned
602 sub x5, x3, x24 // subtract PHYS_OFFSET
603 tst x5, #~((1 << 29) - 1) // within 512MB?
604 csel x21, xzr, x21, ne // zero the FDT pointer
606 add x5, x5, x6 // __va(FDT blob)
607 add x6, x5, #1 << 21 // 2MB for the FDT blob
608 sub x6, x6, #1 // inclusive range
609 create_block_map x0, x7, x3, x5, x6
612 * Since the page tables have been populated with non-cacheable
613 * accesses (MMU disabled), invalidate the idmap and swapper page
614 * tables again to remove any speculatively loaded cache lines.
617 add x1, x26, #SWAPPER_DIR_SIZE
618 bl __inval_cache_range
622 ENDPROC(__create_page_tables)
626 .type __switch_data, %object
628 .quad __mmap_switched
629 .quad __bss_start // x6
630 .quad __bss_stop // x7
631 .quad processor_id // x4
632 .quad __fdt_pointer // x5
633 .quad memstart_addr // x6
634 .quad init_thread_union + THREAD_START_SP // sp
637 * The following fragment of code is executed with the MMU on in MMU mode, and
638 * uses absolute addresses; this is not position independent.
641 adr x3, __switch_data + 8
643 ldp x6, x7, [x3], #16
646 str xzr, [x6], #8 // Clear BSS
649 ldp x4, x5, [x3], #16
653 str x22, [x4] // Save processor ID
654 str x21, [x5] // Save FDT pointer
655 str x24, [x6] // Save PHYS_OFFSET
658 ENDPROC(__mmap_switched)
661 * Exception handling. Something went wrong and we can't proceed. We ought to
662 * tell the user, but since we don't have any guarantee that we're even
663 * running on the right architecture, we do virtually nothing.
674 * This function gets the processor ID in w0 and searches the cpu_table[] for
675 * a match. It returns a pointer to the struct cpu_info it found. The
676 * cpu_table[] must end with an empty (all zeros) structure.
678 * This routine can be called via C code and it needs to work with the MMU
679 * both disabled and enabled (the offset is calculated automatically).
681 ENTRY(lookup_processor_type)
682 adr x1, __lookup_processor_type_data
684 sub x1, x1, x2 // get offset between VA and PA
685 add x3, x3, x1 // convert VA to PA
687 ldp w5, w6, [x3] // load cpu_id_val and cpu_id_mask
688 cbz w5, 2f // end of list?
692 add x3, x3, #CPU_INFO_SZ
695 mov x3, #0 // unknown processor
699 ENDPROC(lookup_processor_type)
702 .type __lookup_processor_type_data, %object
703 __lookup_processor_type_data:
706 .size __lookup_processor_type_data, . - __lookup_processor_type_data
709 * Determine validity of the x21 FDT pointer.
710 * The dtb must be 8-byte aligned and live in the first 512M of memory.