arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/crash_dump.h>
  24 #include <linux/sort.h>
  25 #include <linux/stop_machine.h>
  26 #include <linux/types.h>
  27 #include <linux/mm.h>
  28 #include <asm/cpu.h>
  29 #include <asm/cpufeature.h>
  30 #include <asm/cpu_ops.h>
  31 #include <asm/fpsimd.h>
  32 #include <asm/mmu_context.h>
  33 #include <asm/processor.h>
  34 #include <asm/sysreg.h>
  35 #include <asm/traps.h>
  36 #include <asm/virt.h>
  37
  38 unsigned long elf_hwcap __read_mostly;
  39 EXPORT_SYMBOL_GPL(elf_hwcap);
  40
  41 #ifdef CONFIG_COMPAT
  42 #define COMPAT_ELF_HWCAP_DEFAULT        \
  43                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  44                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  45                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  46                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  47                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  48                                  COMPAT_HWCAP_LPAE)
  49 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  50 unsigned int compat_elf_hwcap2 __read_mostly;
  51 #endif
  52
  53 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  54 EXPORT_SYMBOL(cpu_hwcaps);
  55 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
  56
  57 /* Need also bit for ARM64_CB_PATCH */
  58 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
  59
  60 /*
  61  * Flag to indicate if we have computed the system wide
  62  * capabilities based on the boot time active CPUs. This
  63  * will be used to determine if a new booting CPU should
  64  * go through the verification process to make sure that it
  65  * supports the system capabilities, without using a hotplug
  66  * notifier.
  67  */
  68 static bool sys_caps_initialised;
  69
  70 static inline void set_sys_caps_initialised(void)
  71 {
  72         sys_caps_initialised = true;
  73 }
  74
  75 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  76 {
  77         /* file-wide pr_fmt adds "CPU features: " prefix */
  78         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  79         return 0;
  80 }
  81
  82 static struct notifier_block cpu_hwcaps_notifier = {
  83         .notifier_call = dump_cpu_hwcaps
  84 };
  85
  86 static int __init register_cpu_hwcaps_dumper(void)
  87 {
  88         atomic_notifier_chain_register(&panic_notifier_list,
  89                                        &cpu_hwcaps_notifier);
  90         return 0;
  91 }
  92 __initcall(register_cpu_hwcaps_dumper);
  93
  94 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  95 EXPORT_SYMBOL(cpu_hwcap_keys);
  96
  97 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  98         {                                               \
  99                 .sign = SIGNED,                         \
 100                 .visible = VISIBLE,                     \
 101                 .strict = STRICT,                       \
 102                 .type = TYPE,                           \
 103                 .shift = SHIFT,                         \
 104                 .width = WIDTH,                         \
 105                 .safe_val = SAFE_VAL,                   \
 106         }
 107
 108 /* Define a feature with unsigned values */
 109 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 110         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 111
 112 /* Define a feature with a signed value */
 113 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 114         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 115
 116 #define ARM64_FTR_END                                   \
 117         {                                               \
 118                 .width = 0,                             \
 119         }
 120
 121 /* meta feature for alternatives */
 122 static bool __maybe_unused
 123 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 124
 125 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
 126
 127 /*
 128  * NOTE: Any changes to the visibility of features should be kept in
 129  * sync with the documentation of the CPU feature register ABI.
 130  */
 131 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 132         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 133         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 134         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 135         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 136         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 137         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 138         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 139         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 140         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 141         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 142         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 143         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 144         ARM64_FTR_END,
 145 };
 146
 147 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 148         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
 149         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 150                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
 151         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 152                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
 153         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 154         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 155         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 156         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 157                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
 158         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 159                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
 160         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 161         ARM64_FTR_END,
 162 };
 163
 164 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 165         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 166         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 167         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 168         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 169                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 170         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 171         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 172         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 173         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 174         /* Linux doesn't care about the EL3 */
 175         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 176         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 177         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 178         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 179         ARM64_FTR_END,
 180 };
 181
 182 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 183         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 184         ARM64_FTR_END,
 185 };
 186
 187 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 188         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 189         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 190         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 191         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 192         /* Linux shouldn't care about secure memory */
 193         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 194         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 195         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 196         /*
 197          * Differing PARange is fine as long as all peripherals and memory are mapped
 198          * within the minimum PARange of all CPUs
 199          */
 200         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 201         ARM64_FTR_END,
 202 };
 203
 204 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 205         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 206         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 207         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 208         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 209         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 210         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 211         ARM64_FTR_END,
 212 };
 213
 214 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 215         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 216         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 217         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 218         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 219         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 221         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 222         ARM64_FTR_END,
 223 };
 224
 225 static const struct arm64_ftr_bits ftr_ctr[] = {
 226         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 227         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
 228         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
 229         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0),
 230         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0),
 231         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 232         /*
 233          * Linux can handle differing I-cache policies. Userspace JITs will
 234          * make use of *minLine.
 235          * If we have differing I-cache policies, report it as the weakest - VIPT.
 236          */
 237         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 238         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 239         ARM64_FTR_END,
 240 };
 241
 242 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 243         .name           = "SYS_CTR_EL0",
 244         .ftr_bits       = ftr_ctr
 245 };
 246
 247 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 248         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 249         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 250         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 251         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 252         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 253         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 254         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 255         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 256         ARM64_FTR_END,
 257 };
 258
 259 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 260         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 261         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 262         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 263         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 264         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 265         /*
 266          * We can instantiate multiple PMU instances with different levels
 267          * of support.
 268          */
 269         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 270         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 271         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 272         ARM64_FTR_END,
 273 };
 274
 275 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 276         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 277         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 278         ARM64_FTR_END,
 279 };
 280
 281 static const struct arm64_ftr_bits ftr_dczid[] = {
 282         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 283         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 284         ARM64_FTR_END,
 285 };
 286
 287
 288 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 289         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 290         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 291         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 292         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 293         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 294         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 295         ARM64_FTR_END,
 296 };
 297
 298 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 299         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 300         ARM64_FTR_END,
 301 };
 302
 303 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 304         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 305         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 306         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 307         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 308         ARM64_FTR_END,
 309 };
 310
 311 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 312         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 313         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 314         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 315         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 316         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 317         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 318         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 319         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 320         ARM64_FTR_END,
 321 };
 322
 323 static const struct arm64_ftr_bits ftr_zcr[] = {
 324         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 325                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 326         ARM64_FTR_END,
 327 };
 328
 329 /*
 330  * Common ftr bits for a 32bit register with all hidden, strict
 331  * attributes, with 4bit feature fields and a default safe value of
 332  * 0. Covers the following 32bit registers:
 333  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 334  */
 335 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 336         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 337         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 338         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 339         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 340         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 341         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 342         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 343         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 344         ARM64_FTR_END,
 345 };
 346
 347 /* Table for a single 32bit feature value */
 348 static const struct arm64_ftr_bits ftr_single32[] = {
 349         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 350         ARM64_FTR_END,
 351 };
 352
 353 static const struct arm64_ftr_bits ftr_raz[] = {
 354         ARM64_FTR_END,
 355 };
 356
 357 #define ARM64_FTR_REG(id, table) {              \
 358         .sys_id = id,                           \
 359         .reg =  &(struct arm64_ftr_reg){        \
 360                 .name = #id,                    \
 361                 .ftr_bits = &((table)[0]),      \
 362         }}
 363
 364 static const struct __ftr_reg_entry {
 365         u32                     sys_id;
 366         struct arm64_ftr_reg    *reg;
 367 } arm64_ftr_regs[] = {
 368
 369         /* Op1 = 0, CRn = 0, CRm = 1 */
 370         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 371         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 372         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 373         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 374         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 375         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 376         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 377
 378         /* Op1 = 0, CRn = 0, CRm = 2 */
 379         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 380         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 381         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 382         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 383         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 384         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 385         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 386
 387         /* Op1 = 0, CRn = 0, CRm = 3 */
 388         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 389         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 390         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 391
 392         /* Op1 = 0, CRn = 0, CRm = 4 */
 393         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 394         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 395         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz),
 396
 397         /* Op1 = 0, CRn = 0, CRm = 5 */
 398         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 399         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 400
 401         /* Op1 = 0, CRn = 0, CRm = 6 */
 402         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 403         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 404
 405         /* Op1 = 0, CRn = 0, CRm = 7 */
 406         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 407         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 408         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 409
 410         /* Op1 = 0, CRn = 1, CRm = 2 */
 411         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 412
 413         /* Op1 = 3, CRn = 0, CRm = 0 */
 414         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 415         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 416
 417         /* Op1 = 3, CRn = 14, CRm = 0 */
 418         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 419 };
 420
 421 static int search_cmp_ftr_reg(const void *id, const void *regp)
 422 {
 423         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 424 }
 425
 426 /*
 427  * get_arm64_ftr_reg - Lookup a feature register entry using its
 428  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 429  * ascending order of sys_id , we use binary search to find a matching
 430  * entry.
 431  *
 432  * returns - Upon success,  matching ftr_reg entry for id.
 433  *         - NULL on failure. It is upto the caller to decide
 434  *           the impact of a failure.
 435  */
 436 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 437 {
 438         const struct __ftr_reg_entry *ret;
 439
 440         ret = bsearch((const void *)(unsigned long)sys_id,
 441                         arm64_ftr_regs,
 442                         ARRAY_SIZE(arm64_ftr_regs),
 443                         sizeof(arm64_ftr_regs[0]),
 444                         search_cmp_ftr_reg);
 445         if (ret)
 446                 return ret->reg;
 447         return NULL;
 448 }
 449
 450 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 451                                s64 ftr_val)
 452 {
 453         u64 mask = arm64_ftr_mask(ftrp);
 454
 455         reg &= ~mask;
 456         reg |= (ftr_val << ftrp->shift) & mask;
 457         return reg;
 458 }
 459
 460 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 461                                 s64 cur)
 462 {
 463         s64 ret = 0;
 464
 465         switch (ftrp->type) {
 466         case FTR_EXACT:
 467                 ret = ftrp->safe_val;
 468                 break;
 469         case FTR_LOWER_SAFE:
 470                 ret = new < cur ? new : cur;
 471                 break;
 472         case FTR_HIGHER_SAFE:
 473                 ret = new > cur ? new : cur;
 474                 break;
 475         default:
 476                 BUG();
 477         }
 478
 479         return ret;
 480 }
 481
 482 static void __init sort_ftr_regs(void)
 483 {
 484         int i;
 485
 486         /* Check that the array is sorted so that we can do the binary search */
 487         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 488                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 489 }
 490
 491 /*
 492  * Initialise the CPU feature register from Boot CPU values.
 493  * Also initiliases the strict_mask for the register.
 494  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 495  * RES0 for the system-wide value, and must strictly match.
 496  */
 497 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 498 {
 499         u64 val = 0;
 500         u64 strict_mask = ~0x0ULL;
 501         u64 user_mask = 0;
 502         u64 valid_mask = 0;
 503
 504         const struct arm64_ftr_bits *ftrp;
 505         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 506
 507         BUG_ON(!reg);
 508
 509         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 510                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 511                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 512
 513                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 514
 515                 valid_mask |= ftr_mask;
 516                 if (!ftrp->strict)
 517                         strict_mask &= ~ftr_mask;
 518                 if (ftrp->visible)
 519                         user_mask |= ftr_mask;
 520                 else
 521                         reg->user_val = arm64_ftr_set_value(ftrp,
 522                                                             reg->user_val,
 523                                                             ftrp->safe_val);
 524         }
 525
 526         val &= valid_mask;
 527
 528         reg->sys_val = val;
 529         reg->strict_mask = strict_mask;
 530         reg->user_mask = user_mask;
 531 }
 532
 533 extern const struct arm64_cpu_capabilities arm64_errata[];
 534 static const struct arm64_cpu_capabilities arm64_features[];
 535
 536 static void __init
 537 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
 538 {
 539         for (; caps->matches; caps++) {
 540                 if (WARN(caps->capability >= ARM64_NCAPS,
 541                         "Invalid capability %d\n", caps->capability))
 542                         continue;
 543                 if (WARN(cpu_hwcaps_ptrs[caps->capability],
 544                         "Duplicate entry for capability %d\n",
 545                         caps->capability))
 546                         continue;
 547                 cpu_hwcaps_ptrs[caps->capability] = caps;
 548         }
 549 }
 550
 551 static void __init init_cpu_hwcaps_indirect_list(void)
 552 {
 553         init_cpu_hwcaps_indirect_list_from_array(arm64_features);
 554         init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
 555 }
 556
 557 static void __init setup_boot_cpu_capabilities(void);
 558
 559 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 560 {
 561         /* Before we start using the tables, make sure it is sorted */
 562         sort_ftr_regs();
 563
 564         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 565         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 566         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 567         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 568         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 569         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 570         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 571         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 572         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 573         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 574         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 575         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 576         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 577
 578         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 579                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 580                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 581                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 582                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 583                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 584                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 585                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 586                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 587                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 588                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 589                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 590                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 591                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 592                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 593                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 594                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 595         }
 596
 597         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 598                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 599                 sve_init_vq_map();
 600         }
 601
 602         /*
 603          * Initialize the indirect array of CPU hwcaps capabilities pointers
 604          * before we handle the boot CPU below.
 605          */
 606         init_cpu_hwcaps_indirect_list();
 607
 608         /*
 609          * Detect and enable early CPU capabilities based on the boot CPU,
 610          * after we have initialised the CPU feature infrastructure.
 611          */
 612         setup_boot_cpu_capabilities();
 613 }
 614
 615 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 616 {
 617         const struct arm64_ftr_bits *ftrp;
 618
 619         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 620                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 621                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 622
 623                 if (ftr_cur == ftr_new)
 624                         continue;
 625                 /* Find a safe value */
 626                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 627                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 628         }
 629
 630 }
 631
 632 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 633 {
 634         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 635
 636         BUG_ON(!regp);
 637         update_cpu_ftr_reg(regp, val);
 638         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 639                 return 0;
 640         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 641                         regp->name, boot, cpu, val);
 642         return 1;
 643 }
 644
 645 /*
 646  * Update system wide CPU feature registers with the values from a
 647  * non-boot CPU. Also performs SANITY checks to make sure that there
 648  * aren't any insane variations from that of the boot CPU.
 649  */
 650 void update_cpu_features(int cpu,
 651                          struct cpuinfo_arm64 *info,
 652                          struct cpuinfo_arm64 *boot)
 653 {
 654         int taint = 0;
 655
 656         /*
 657          * The kernel can handle differing I-cache policies, but otherwise
 658          * caches should look identical. Userspace JITs will make use of
 659          * *minLine.
 660          */
 661         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 662                                       info->reg_ctr, boot->reg_ctr);
 663
 664         /*
 665          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 666          * could result in too much or too little memory being zeroed if a
 667          * process is preempted and migrated between CPUs.
 668          */
 669         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 670                                       info->reg_dczid, boot->reg_dczid);
 671
 672         /* If different, timekeeping will be broken (especially with KVM) */
 673         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 674                                       info->reg_cntfrq, boot->reg_cntfrq);
 675
 676         /*
 677          * The kernel uses self-hosted debug features and expects CPUs to
 678          * support identical debug features. We presently need CTX_CMPs, WRPs,
 679          * and BRPs to be identical.
 680          * ID_AA64DFR1 is currently RES0.
 681          */
 682         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 683                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 684         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 685                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 686         /*
 687          * Even in big.LITTLE, processors should be identical instruction-set
 688          * wise.
 689          */
 690         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 691                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 692         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 693                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 694
 695         /*
 696          * Differing PARange support is fine as long as all peripherals and
 697          * memory are mapped within the minimum PARange of all CPUs.
 698          * Linux should not care about secure memory.
 699          */
 700         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 701                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 702         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 703                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 704         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 705                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 706
 707         /*
 708          * EL3 is not our concern.
 709          */
 710         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 711                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 712         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 713                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 714
 715         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 716                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 717
 718         /*
 719          * If we have AArch32, we care about 32-bit features for compat.
 720          * If the system doesn't support AArch32, don't update them.
 721          */
 722         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 723                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 724
 725                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 726                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 727                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 728                                         info->reg_id_isar0, boot->reg_id_isar0);
 729                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 730                                         info->reg_id_isar1, boot->reg_id_isar1);
 731                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 732                                         info->reg_id_isar2, boot->reg_id_isar2);
 733                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 734                                         info->reg_id_isar3, boot->reg_id_isar3);
 735                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 736                                         info->reg_id_isar4, boot->reg_id_isar4);
 737                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 738                                         info->reg_id_isar5, boot->reg_id_isar5);
 739
 740                 /*
 741                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 742                  * ACTLR formats could differ across CPUs and therefore would have to
 743                  * be trapped for virtualization anyway.
 744                  */
 745                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 746                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 747                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 748                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 749                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 750                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 751                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 752                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 753                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 754                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 755                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 756                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 757                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 758                                         info->reg_mvfr0, boot->reg_mvfr0);
 759                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 760                                         info->reg_mvfr1, boot->reg_mvfr1);
 761                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 762                                         info->reg_mvfr2, boot->reg_mvfr2);
 763         }
 764
 765         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 766                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 767                                         info->reg_zcr, boot->reg_zcr);
 768
 769                 /* Probe vector lengths, unless we already gave up on SVE */
 770                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 771                     !sys_caps_initialised)
 772                         sve_update_vq_map();
 773         }
 774
 775         /*
 776          * Mismatched CPU features are a recipe for disaster. Don't even
 777          * pretend to support them.
 778          */
 779         if (taint) {
 780                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 781                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 782         }
 783 }
 784
 785 u64 read_sanitised_ftr_reg(u32 id)
 786 {
 787         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 788
 789         /* We shouldn't get a request for an unsupported register */
 790         BUG_ON(!regp);
 791         return regp->sys_val;
 792 }
 793
 794 #define read_sysreg_case(r)     \
 795         case r:         return read_sysreg_s(r)
 796
 797 /*
 798  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 799  * Read the system register on the current CPU
 800  */
 801 static u64 __read_sysreg_by_encoding(u32 sys_id)
 802 {
 803         switch (sys_id) {
 804         read_sysreg_case(SYS_ID_PFR0_EL1);
 805         read_sysreg_case(SYS_ID_PFR1_EL1);
 806         read_sysreg_case(SYS_ID_DFR0_EL1);
 807         read_sysreg_case(SYS_ID_MMFR0_EL1);
 808         read_sysreg_case(SYS_ID_MMFR1_EL1);
 809         read_sysreg_case(SYS_ID_MMFR2_EL1);
 810         read_sysreg_case(SYS_ID_MMFR3_EL1);
 811         read_sysreg_case(SYS_ID_ISAR0_EL1);
 812         read_sysreg_case(SYS_ID_ISAR1_EL1);
 813         read_sysreg_case(SYS_ID_ISAR2_EL1);
 814         read_sysreg_case(SYS_ID_ISAR3_EL1);
 815         read_sysreg_case(SYS_ID_ISAR4_EL1);
 816         read_sysreg_case(SYS_ID_ISAR5_EL1);
 817         read_sysreg_case(SYS_MVFR0_EL1);
 818         read_sysreg_case(SYS_MVFR1_EL1);
 819         read_sysreg_case(SYS_MVFR2_EL1);
 820
 821         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 822         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 823         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 824         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 825         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 826         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 827         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 828         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 829         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 830
 831         read_sysreg_case(SYS_CNTFRQ_EL0);
 832         read_sysreg_case(SYS_CTR_EL0);
 833         read_sysreg_case(SYS_DCZID_EL0);
 834
 835         default:
 836                 BUG();
 837                 return 0;
 838         }
 839 }
 840
 841 #include <linux/irqchip/arm-gic-v3.h>
 842
 843 static bool
 844 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 845 {
 846         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 847
 848         return val >= entry->min_field_value;
 849 }
 850
 851 static bool
 852 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 853 {
 854         u64 val;
 855
 856         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 857         if (scope == SCOPE_SYSTEM)
 858                 val = read_sanitised_ftr_reg(entry->sys_reg);
 859         else
 860                 val = __read_sysreg_by_encoding(entry->sys_reg);
 861
 862         return feature_matches(val, entry);
 863 }
 864
 865 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 866 {
 867         bool has_sre;
 868
 869         if (!has_cpuid_feature(entry, scope))
 870                 return false;
 871
 872         has_sre = gic_enable_sre();
 873         if (!has_sre)
 874                 pr_warn_once("%s present but disabled by higher exception level\n",
 875                              entry->desc);
 876
 877         return has_sre;
 878 }
 879
 880 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 881 {
 882         u32 midr = read_cpuid_id();
 883
 884         /* Cavium ThunderX pass 1.x and 2.x */
 885         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
 886                 MIDR_CPU_VAR_REV(0, 0),
 887                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 888 }
 889
 890 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 891 {
 892         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 893
 894         return cpuid_feature_extract_signed_field(pfr0,
 895                                         ID_AA64PFR0_FP_SHIFT) < 0;
 896 }
 897
 898 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
 899                           int scope)
 900 {
 901         u64 ctr;
 902
 903         if (scope == SCOPE_SYSTEM)
 904                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 905         else
 906                 ctr = read_cpuid_effective_cachetype();
 907
 908         return ctr & BIT(CTR_IDC_SHIFT);
 909 }
 910
 911 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
 912 {
 913         /*
 914          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
 915          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
 916          * to the CTR_EL0 on this CPU and emulate it with the real/safe
 917          * value.
 918          */
 919         if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
 920                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
 921 }
 922
 923 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
 924                           int scope)
 925 {
 926         u64 ctr;
 927
 928         if (scope == SCOPE_SYSTEM)
 929                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 930         else
 931                 ctr = read_cpuid_cachetype();
 932
 933         return ctr & BIT(CTR_DIC_SHIFT);
 934 }
 935
 936 static bool __maybe_unused
 937 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
 938 {
 939         /*
 940          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
 941          * may share TLB entries with a CPU stuck in the crashed
 942          * kernel.
 943          */
 944          if (is_kdump_kernel())
 945                 return false;
 946
 947         return has_cpuid_feature(entry, scope);
 948 }
 949
 950 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 951 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 952
 953 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 954                                 int scope)
 955 {
 956         /* List of CPUs that are not vulnerable and don't need KPTI */
 957         static const struct midr_range kpti_safe_list[] = {
 958                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 959                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 960                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 961                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 962                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 963                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 964                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 965                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 966                 { /* sentinel */ }
 967         };
 968         char const *str = "command line option";
 969
 970         /*
 971          * For reasons that aren't entirely clear, enabling KPTI on Cavium
 972          * ThunderX leads to apparent I-cache corruption of kernel text, which
 973          * ends as well as you might imagine. Don't even try.
 974          */
 975         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
 976                 str = "ARM64_WORKAROUND_CAVIUM_27456";
 977                 __kpti_forced = -1;
 978         }
 979
 980         /* Forced? */
 981         if (__kpti_forced) {
 982                 pr_info_once("kernel page table isolation forced %s by %s\n",
 983                              __kpti_forced > 0 ? "ON" : "OFF", str);
 984                 return __kpti_forced > 0;
 985         }
 986
 987         /* Useful for KASLR robustness */
 988         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
 989                 return kaslr_offset() > 0;
 990
 991         /* Don't force KPTI for CPUs that are not vulnerable */
 992         if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list))
 993                 return false;
 994
 995         /* Defer to CPU feature registers */
 996         return !has_cpuid_feature(entry, scope);
 997 }
 998
 999 static void
1000 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1001 {
1002         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1003         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1004         kpti_remap_fn *remap_fn;
1005
1006         static bool kpti_applied = false;
1007         int cpu = smp_processor_id();
1008
1009         /*
1010          * We don't need to rewrite the page-tables if either we've done
1011          * it already or we have KASLR enabled and therefore have not
1012          * created any global mappings at all.
1013          */
1014         if (kpti_applied || kaslr_offset() > 0)
1015                 return;
1016
1017         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1018
1019         cpu_install_idmap();
1020         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1021         cpu_uninstall_idmap();
1022
1023         if (!cpu)
1024                 kpti_applied = true;
1025
1026         return;
1027 }
1028
1029 static int __init parse_kpti(char *str)
1030 {
1031         bool enabled;
1032         int ret = strtobool(str, &enabled);
1033
1034         if (ret)
1035                 return ret;
1036
1037         __kpti_forced = enabled ? 1 : -1;
1038         return 0;
1039 }
1040 early_param("kpti", parse_kpti);
1041 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1042
1043 #ifdef CONFIG_ARM64_HW_AFDBM
1044 static inline void __cpu_enable_hw_dbm(void)
1045 {
1046         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1047
1048         write_sysreg(tcr, tcr_el1);
1049         isb();
1050 }
1051
1052 static bool cpu_has_broken_dbm(void)
1053 {
1054         /* List of CPUs which have broken DBM support. */
1055         static const struct midr_range cpus[] = {
1056 #ifdef CONFIG_ARM64_ERRATUM_1024718
1057                 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
1058 #endif
1059                 {},
1060         };
1061
1062         return is_midr_in_range_list(read_cpuid_id(), cpus);
1063 }
1064
1065 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1066 {
1067         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1068                !cpu_has_broken_dbm();
1069 }
1070
1071 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1072 {
1073         if (cpu_can_use_dbm(cap))
1074                 __cpu_enable_hw_dbm();
1075 }
1076
1077 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1078                        int __unused)
1079 {
1080         static bool detected = false;
1081         /*
1082          * DBM is a non-conflicting feature. i.e, the kernel can safely
1083          * run a mix of CPUs with and without the feature. So, we
1084          * unconditionally enable the capability to allow any late CPU
1085          * to use the feature. We only enable the control bits on the
1086          * CPU, if it actually supports.
1087          *
1088          * We have to make sure we print the "feature" detection only
1089          * when at least one CPU actually uses it. So check if this CPU
1090          * can actually use it and print the message exactly once.
1091          *
1092          * This is safe as all CPUs (including secondary CPUs - due to the
1093          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1094          * goes through the "matches" check exactly once. Also if a CPU
1095          * matches the criteria, it is guaranteed that the CPU will turn
1096          * the DBM on, as the capability is unconditionally enabled.
1097          */
1098         if (!detected && cpu_can_use_dbm(cap)) {
1099                 detected = true;
1100                 pr_info("detected: Hardware dirty bit management\n");
1101         }
1102
1103         return true;
1104 }
1105
1106 #endif
1107
1108 #ifdef CONFIG_ARM64_VHE
1109 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1110 {
1111         return is_kernel_in_hyp_mode();
1112 }
1113
1114 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1115 {
1116         /*
1117          * Copy register values that aren't redirected by hardware.
1118          *
1119          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1120          * this value to tpidr_el2 before we patch the code. Once we've done
1121          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1122          * do anything here.
1123          */
1124         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1125                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1126 }
1127 #endif
1128
1129 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1130 {
1131         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1132
1133         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1134         WARN_ON(val & (7 << 27 | 7 << 21));
1135 }
1136
1137 #ifdef CONFIG_ARM64_SSBD
1138 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1139 {
1140         if (user_mode(regs))
1141                 return 1;
1142
1143         if (instr & BIT(PSTATE_Imm_shift))
1144                 regs->pstate |= PSR_SSBS_BIT;
1145         else
1146                 regs->pstate &= ~PSR_SSBS_BIT;
1147
1148         arm64_skip_faulting_instruction(regs, 4);
1149         return 0;
1150 }
1151
1152 static struct undef_hook ssbs_emulation_hook = {
1153         .instr_mask     = ~(1U << PSTATE_Imm_shift),
1154         .instr_val      = 0xd500401f | PSTATE_SSBS,
1155         .fn             = ssbs_emulation_handler,
1156 };
1157
1158 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1159 {
1160         static bool undef_hook_registered = false;
1161         static DEFINE_SPINLOCK(hook_lock);
1162
1163         spin_lock(&hook_lock);
1164         if (!undef_hook_registered) {
1165                 register_undef_hook(&ssbs_emulation_hook);
1166                 undef_hook_registered = true;
1167         }
1168         spin_unlock(&hook_lock);
1169
1170         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1171                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1172                 arm64_set_ssbd_mitigation(false);
1173         } else {
1174                 arm64_set_ssbd_mitigation(true);
1175         }
1176 }
1177 #endif /* CONFIG_ARM64_SSBD */
1178
1179 #ifdef CONFIG_ARM64_PAN
1180 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1181 {
1182         /*
1183          * We modify PSTATE. This won't work from irq context as the PSTATE
1184          * is discarded once we return from the exception.
1185          */
1186         WARN_ON_ONCE(in_interrupt());
1187
1188         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1189         asm(SET_PSTATE_PAN(1));
1190 }
1191 #endif /* CONFIG_ARM64_PAN */
1192
1193 #ifdef CONFIG_ARM64_RAS_EXTN
1194 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1195 {
1196         /* Firmware may have left a deferred SError in this register. */
1197         write_sysreg_s(0, SYS_DISR_EL1);
1198 }
1199 #endif /* CONFIG_ARM64_RAS_EXTN */
1200
1201 #ifdef CONFIG_ARM64_PTR_AUTH
1202 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1203 {
1204         sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1205                                        SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1206 }
1207 #endif /* CONFIG_ARM64_PTR_AUTH */
1208
1209 #ifdef CONFIG_ARM64_PSEUDO_NMI
1210 static bool enable_pseudo_nmi;
1211
1212 static int __init early_enable_pseudo_nmi(char *p)
1213 {
1214         return strtobool(p, &enable_pseudo_nmi);
1215 }
1216 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1217
1218 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1219                                    int scope)
1220 {
1221         return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1222 }
1223 #endif
1224
1225 static const struct arm64_cpu_capabilities arm64_features[] = {
1226         {
1227                 .desc = "GIC system register CPU interface",
1228                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1229                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1230                 .matches = has_useable_gicv3_cpuif,
1231                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1232                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1233                 .sign = FTR_UNSIGNED,
1234                 .min_field_value = 1,
1235         },
1236 #ifdef CONFIG_ARM64_PAN
1237         {
1238                 .desc = "Privileged Access Never",
1239                 .capability = ARM64_HAS_PAN,
1240                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1241                 .matches = has_cpuid_feature,
1242                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1243                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1244                 .sign = FTR_UNSIGNED,
1245                 .min_field_value = 1,
1246                 .cpu_enable = cpu_enable_pan,
1247         },
1248 #endif /* CONFIG_ARM64_PAN */
1249 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1250         {
1251                 .desc = "LSE atomic instructions",
1252                 .capability = ARM64_HAS_LSE_ATOMICS,
1253                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1254                 .matches = has_cpuid_feature,
1255                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1256                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1257                 .sign = FTR_UNSIGNED,
1258                 .min_field_value = 2,
1259         },
1260 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1261         {
1262                 .desc = "Software prefetching using PRFM",
1263                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1264                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1265                 .matches = has_no_hw_prefetch,
1266         },
1267 #ifdef CONFIG_ARM64_UAO
1268         {
1269                 .desc = "User Access Override",
1270                 .capability = ARM64_HAS_UAO,
1271                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1272                 .matches = has_cpuid_feature,
1273                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1274                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1275                 .min_field_value = 1,
1276                 /*
1277                  * We rely on stop_machine() calling uao_thread_switch() to set
1278                  * UAO immediately after patching.
1279                  */
1280         },
1281 #endif /* CONFIG_ARM64_UAO */
1282 #ifdef CONFIG_ARM64_PAN
1283         {
1284                 .capability = ARM64_ALT_PAN_NOT_UAO,
1285                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1286                 .matches = cpufeature_pan_not_uao,
1287         },
1288 #endif /* CONFIG_ARM64_PAN */
1289 #ifdef CONFIG_ARM64_VHE
1290         {
1291                 .desc = "Virtualization Host Extensions",
1292                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1293                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1294                 .matches = runs_at_el2,
1295                 .cpu_enable = cpu_copy_el2regs,
1296         },
1297 #endif  /* CONFIG_ARM64_VHE */
1298         {
1299                 .desc = "32-bit EL0 Support",
1300                 .capability = ARM64_HAS_32BIT_EL0,
1301                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1302                 .matches = has_cpuid_feature,
1303                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1304                 .sign = FTR_UNSIGNED,
1305                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1306                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1307         },
1308 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1309         {
1310                 .desc = "Kernel page table isolation (KPTI)",
1311                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1312                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1313                 /*
1314                  * The ID feature fields below are used to indicate that
1315                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1316                  * more details.
1317                  */
1318                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1319                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1320                 .min_field_value = 1,
1321                 .matches = unmap_kernel_at_el0,
1322                 .cpu_enable = kpti_install_ng_mappings,
1323         },
1324 #endif
1325         {
1326                 /* FP/SIMD is not implemented */
1327                 .capability = ARM64_HAS_NO_FPSIMD,
1328                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1329                 .min_field_value = 0,
1330                 .matches = has_no_fpsimd,
1331         },
1332 #ifdef CONFIG_ARM64_PMEM
1333         {
1334                 .desc = "Data cache clean to Point of Persistence",
1335                 .capability = ARM64_HAS_DCPOP,
1336                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1337                 .matches = has_cpuid_feature,
1338                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1339                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1340                 .min_field_value = 1,
1341         },
1342 #endif
1343 #ifdef CONFIG_ARM64_SVE
1344         {
1345                 .desc = "Scalable Vector Extension",
1346                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1347                 .capability = ARM64_SVE,
1348                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1349                 .sign = FTR_UNSIGNED,
1350                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1351                 .min_field_value = ID_AA64PFR0_SVE,
1352                 .matches = has_cpuid_feature,
1353                 .cpu_enable = sve_kernel_enable,
1354         },
1355 #endif /* CONFIG_ARM64_SVE */
1356 #ifdef CONFIG_ARM64_RAS_EXTN
1357         {
1358                 .desc = "RAS Extension Support",
1359                 .capability = ARM64_HAS_RAS_EXTN,
1360                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1361                 .matches = has_cpuid_feature,
1362                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1363                 .sign = FTR_UNSIGNED,
1364                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1365                 .min_field_value = ID_AA64PFR0_RAS_V1,
1366                 .cpu_enable = cpu_clear_disr,
1367         },
1368 #endif /* CONFIG_ARM64_RAS_EXTN */
1369         {
1370                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1371                 .capability = ARM64_HAS_CACHE_IDC,
1372                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1373                 .matches = has_cache_idc,
1374                 .cpu_enable = cpu_emulate_effective_ctr,
1375         },
1376         {
1377                 .desc = "Instruction cache invalidation not required for I/D coherence",
1378                 .capability = ARM64_HAS_CACHE_DIC,
1379                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1380                 .matches = has_cache_dic,
1381         },
1382         {
1383                 .desc = "Stage-2 Force Write-Back",
1384                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1385                 .capability = ARM64_HAS_STAGE2_FWB,
1386                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1387                 .sign = FTR_UNSIGNED,
1388                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1389                 .min_field_value = 1,
1390                 .matches = has_cpuid_feature,
1391                 .cpu_enable = cpu_has_fwb,
1392         },
1393 #ifdef CONFIG_ARM64_HW_AFDBM
1394         {
1395                 /*
1396                  * Since we turn this on always, we don't want the user to
1397                  * think that the feature is available when it may not be.
1398                  * So hide the description.
1399                  *
1400                  * .desc = "Hardware pagetable Dirty Bit Management",
1401                  *
1402                  */
1403                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1404                 .capability = ARM64_HW_DBM,
1405                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1406                 .sign = FTR_UNSIGNED,
1407                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1408                 .min_field_value = 2,
1409                 .matches = has_hw_dbm,
1410                 .cpu_enable = cpu_enable_hw_dbm,
1411         },
1412 #endif
1413         {
1414                 .desc = "CRC32 instructions",
1415                 .capability = ARM64_HAS_CRC32,
1416                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1417                 .matches = has_cpuid_feature,
1418                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1419                 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1420                 .min_field_value = 1,
1421         },
1422 #ifdef CONFIG_ARM64_SSBD
1423         {
1424                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1425                 .capability = ARM64_SSBS,
1426                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1427                 .matches = has_cpuid_feature,
1428                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1429                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1430                 .sign = FTR_UNSIGNED,
1431                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1432                 .cpu_enable = cpu_enable_ssbs,
1433         },
1434 #endif
1435 #ifdef CONFIG_ARM64_CNP
1436         {
1437                 .desc = "Common not Private translations",
1438                 .capability = ARM64_HAS_CNP,
1439                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1440                 .matches = has_useable_cnp,
1441                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1442                 .sign = FTR_UNSIGNED,
1443                 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1444                 .min_field_value = 1,
1445                 .cpu_enable = cpu_enable_cnp,
1446         },
1447 #endif
1448         {
1449                 .desc = "Speculation barrier (SB)",
1450                 .capability = ARM64_HAS_SB,
1451                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1452                 .matches = has_cpuid_feature,
1453                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1454                 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1455                 .sign = FTR_UNSIGNED,
1456                 .min_field_value = 1,
1457         },
1458 #ifdef CONFIG_ARM64_PTR_AUTH
1459         {
1460                 .desc = "Address authentication (architected algorithm)",
1461                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1462                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1463                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1464                 .sign = FTR_UNSIGNED,
1465                 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1466                 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1467                 .matches = has_cpuid_feature,
1468                 .cpu_enable = cpu_enable_address_auth,
1469         },
1470         {
1471                 .desc = "Address authentication (IMP DEF algorithm)",
1472                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1473                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1474                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1475                 .sign = FTR_UNSIGNED,
1476                 .field_pos = ID_AA64ISAR1_API_SHIFT,
1477                 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1478                 .matches = has_cpuid_feature,
1479                 .cpu_enable = cpu_enable_address_auth,
1480         },
1481         {
1482                 .desc = "Generic authentication (architected algorithm)",
1483                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1484                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1485                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1486                 .sign = FTR_UNSIGNED,
1487                 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1488                 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1489                 .matches = has_cpuid_feature,
1490         },
1491         {
1492                 .desc = "Generic authentication (IMP DEF algorithm)",
1493                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1494                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1495                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1496                 .sign = FTR_UNSIGNED,
1497                 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1498                 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1499                 .matches = has_cpuid_feature,
1500         },
1501 #endif /* CONFIG_ARM64_PTR_AUTH */
1502 #ifdef CONFIG_ARM64_PSEUDO_NMI
1503         {
1504                 /*
1505                  * Depends on having GICv3
1506                  */
1507                 .desc = "IRQ priority masking",
1508                 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1509                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1510                 .matches = can_use_gic_priorities,
1511                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1512                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1513                 .sign = FTR_UNSIGNED,
1514                 .min_field_value = 1,
1515         },
1516 #endif
1517         {},
1518 };
1519
1520 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)                             \
1521                 .matches = has_cpuid_feature,                                   \
1522                 .sys_reg = reg,                                                 \
1523                 .field_pos = field,                                             \
1524                 .sign = s,                                                      \
1525                 .min_field_value = min_value,
1526
1527 #define __HWCAP_CAP(name, cap_type, cap)                                        \
1528                 .desc = name,                                                   \
1529                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
1530                 .hwcap_type = cap_type,                                         \
1531                 .hwcap = cap,                                                   \
1532
1533 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)                      \
1534         {                                                                       \
1535                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1536                 HWCAP_CPUID_MATCH(reg, field, s, min_value)                     \
1537         }
1538
1539 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
1540         {                                                                       \
1541                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1542                 .matches = cpucap_multi_entry_cap_matches,                      \
1543                 .match_list = list,                                             \
1544         }
1545
1546 #ifdef CONFIG_ARM64_PTR_AUTH
1547 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1548         {
1549                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1550                                   FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1551         },
1552         {
1553                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1554                                   FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1555         },
1556         {},
1557 };
1558
1559 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1560         {
1561                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1562                                   FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1563         },
1564         {
1565                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1566                                   FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1567         },
1568         {},
1569 };
1570 #endif
1571
1572 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1573         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1574         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1575         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1576         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
1577         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
1578         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1579         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
1580         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
1581         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1582         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1583         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1584         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
1585         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
1586         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM),
1587         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
1588         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
1589         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
1590         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
1591         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT),
1592         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
1593         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
1594         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
1595         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
1596         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC),
1597         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SB),
1598         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT),
1599 #ifdef CONFIG_ARM64_SVE
1600         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
1601 #endif
1602         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
1603 #ifdef CONFIG_ARM64_PTR_AUTH
1604         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, HWCAP_PACA),
1605         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, HWCAP_PACG),
1606 #endif
1607         {},
1608 };
1609
1610 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1611 #ifdef CONFIG_COMPAT
1612         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1613         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1614         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1615         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1616         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1617 #endif
1618         {},
1619 };
1620
1621 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1622 {
1623         switch (cap->hwcap_type) {
1624         case CAP_HWCAP:
1625                 elf_hwcap |= cap->hwcap;
1626                 break;
1627 #ifdef CONFIG_COMPAT
1628         case CAP_COMPAT_HWCAP:
1629                 compat_elf_hwcap |= (u32)cap->hwcap;
1630                 break;
1631         case CAP_COMPAT_HWCAP2:
1632                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1633                 break;
1634 #endif
1635         default:
1636                 WARN_ON(1);
1637                 break;
1638         }
1639 }
1640
1641 /* Check if we have a particular HWCAP enabled */
1642 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1643 {
1644         bool rc;
1645
1646         switch (cap->hwcap_type) {
1647         case CAP_HWCAP:
1648                 rc = (elf_hwcap & cap->hwcap) != 0;
1649                 break;
1650 #ifdef CONFIG_COMPAT
1651         case CAP_COMPAT_HWCAP:
1652                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1653                 break;
1654         case CAP_COMPAT_HWCAP2:
1655                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1656                 break;
1657 #endif
1658         default:
1659                 WARN_ON(1);
1660                 rc = false;
1661         }
1662
1663         return rc;
1664 }
1665
1666 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1667 {
1668         /* We support emulation of accesses to CPU ID feature registers */
1669         elf_hwcap |= HWCAP_CPUID;
1670         for (; hwcaps->matches; hwcaps++)
1671                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1672                         cap_set_elf_hwcap(hwcaps);
1673 }
1674
1675 static void update_cpu_capabilities(u16 scope_mask)
1676 {
1677         int i;
1678         const struct arm64_cpu_capabilities *caps;
1679
1680         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1681         for (i = 0; i < ARM64_NCAPS; i++) {
1682                 caps = cpu_hwcaps_ptrs[i];
1683                 if (!caps || !(caps->type & scope_mask) ||
1684                     cpus_have_cap(caps->capability) ||
1685                     !caps->matches(caps, cpucap_default_scope(caps)))
1686                         continue;
1687
1688                 if (caps->desc)
1689                         pr_info("detected: %s\n", caps->desc);
1690                 cpus_set_cap(caps->capability);
1691
1692                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
1693                         set_bit(caps->capability, boot_capabilities);
1694         }
1695 }
1696
1697 /*
1698  * Enable all the available capabilities on this CPU. The capabilities
1699  * with BOOT_CPU scope are handled separately and hence skipped here.
1700  */
1701 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
1702 {
1703         int i;
1704         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
1705
1706         for_each_available_cap(i) {
1707                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1708
1709                 if (WARN_ON(!cap))
1710                         continue;
1711
1712                 if (!(cap->type & non_boot_scope))
1713                         continue;
1714
1715                 if (cap->cpu_enable)
1716                         cap->cpu_enable(cap);
1717         }
1718         return 0;
1719 }
1720
1721 /*
1722  * Run through the enabled capabilities and enable() it on all active
1723  * CPUs
1724  */
1725 static void __init enable_cpu_capabilities(u16 scope_mask)
1726 {
1727         int i;
1728         const struct arm64_cpu_capabilities *caps;
1729         bool boot_scope;
1730
1731         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1732         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
1733
1734         for (i = 0; i < ARM64_NCAPS; i++) {
1735                 unsigned int num;
1736
1737                 caps = cpu_hwcaps_ptrs[i];
1738                 if (!caps || !(caps->type & scope_mask))
1739                         continue;
1740                 num = caps->capability;
1741                 if (!cpus_have_cap(num))
1742                         continue;
1743
1744                 /* Ensure cpus_have_const_cap(num) works */
1745                 static_branch_enable(&cpu_hwcap_keys[num]);
1746
1747                 if (boot_scope && caps->cpu_enable)
1748                         /*
1749                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
1750                          * before any secondary CPU boots. Thus, each secondary
1751                          * will enable the capability as appropriate via
1752                          * check_local_cpu_capabilities(). The only exception is
1753                          * the boot CPU, for which the capability must be
1754                          * enabled here. This approach avoids costly
1755                          * stop_machine() calls for this case.
1756                          */
1757                         caps->cpu_enable(caps);
1758         }
1759
1760         /*
1761          * For all non-boot scope capabilities, use stop_machine()
1762          * as it schedules the work allowing us to modify PSTATE,
1763          * instead of on_each_cpu() which uses an IPI, giving us a
1764          * PSTATE that disappears when we return.
1765          */
1766         if (!boot_scope)
1767                 stop_machine(cpu_enable_non_boot_scope_capabilities,
1768                              NULL, cpu_online_mask);
1769 }
1770
1771 /*
1772  * Run through the list of capabilities to check for conflicts.
1773  * If the system has already detected a capability, take necessary
1774  * action on this CPU.
1775  *
1776  * Returns "false" on conflicts.
1777  */
1778 static bool verify_local_cpu_caps(u16 scope_mask)
1779 {
1780         int i;
1781         bool cpu_has_cap, system_has_cap;
1782         const struct arm64_cpu_capabilities *caps;
1783
1784         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1785
1786         for (i = 0; i < ARM64_NCAPS; i++) {
1787                 caps = cpu_hwcaps_ptrs[i];
1788                 if (!caps || !(caps->type & scope_mask))
1789                         continue;
1790
1791                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1792                 system_has_cap = cpus_have_cap(caps->capability);
1793
1794                 if (system_has_cap) {
1795                         /*
1796                          * Check if the new CPU misses an advertised feature,
1797                          * which is not safe to miss.
1798                          */
1799                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1800                                 break;
1801                         /*
1802                          * We have to issue cpu_enable() irrespective of
1803                          * whether the CPU has it or not, as it is enabeld
1804                          * system wide. It is upto the call back to take
1805                          * appropriate action on this CPU.
1806                          */
1807                         if (caps->cpu_enable)
1808                                 caps->cpu_enable(caps);
1809                 } else {
1810                         /*
1811                          * Check if the CPU has this capability if it isn't
1812                          * safe to have when the system doesn't.
1813                          */
1814                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1815                                 break;
1816                 }
1817         }
1818
1819         if (i < ARM64_NCAPS) {
1820                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1821                         smp_processor_id(), caps->capability,
1822                         caps->desc, system_has_cap, cpu_has_cap);
1823                 return false;
1824         }
1825
1826         return true;
1827 }
1828
1829 /*
1830  * Check for CPU features that are used in early boot
1831  * based on the Boot CPU value.
1832  */
1833 static void check_early_cpu_features(void)
1834 {
1835         verify_cpu_asid_bits();
1836         /*
1837          * Early features are used by the kernel already. If there
1838          * is a conflict, we cannot proceed further.
1839          */
1840         if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1841                 cpu_panic_kernel();
1842 }
1843
1844 static void
1845 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1846 {
1847
1848         for (; caps->matches; caps++)
1849                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1850                         pr_crit("CPU%d: missing HWCAP: %s\n",
1851                                         smp_processor_id(), caps->desc);
1852                         cpu_die_early();
1853                 }
1854 }
1855
1856 static void verify_sve_features(void)
1857 {
1858         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1859         u64 zcr = read_zcr_features();
1860
1861         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1862         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1863
1864         if (len < safe_len || sve_verify_vq_map()) {
1865                 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1866                         smp_processor_id());
1867                 cpu_die_early();
1868         }
1869
1870         /* Add checks on other ZCR bits here if necessary */
1871 }
1872
1873
1874 /*
1875  * Run through the enabled system capabilities and enable() it on this CPU.
1876  * The capabilities were decided based on the available CPUs at the boot time.
1877  * Any new CPU should match the system wide status of the capability. If the
1878  * new CPU doesn't have a capability which the system now has enabled, we
1879  * cannot do anything to fix it up and could cause unexpected failures. So
1880  * we park the CPU.
1881  */
1882 static void verify_local_cpu_capabilities(void)
1883 {
1884         /*
1885          * The capabilities with SCOPE_BOOT_CPU are checked from
1886          * check_early_cpu_features(), as they need to be verified
1887          * on all secondary CPUs.
1888          */
1889         if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1890                 cpu_die_early();
1891
1892         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1893
1894         if (system_supports_32bit_el0())
1895                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1896
1897         if (system_supports_sve())
1898                 verify_sve_features();
1899 }
1900
1901 void check_local_cpu_capabilities(void)
1902 {
1903         /*
1904          * All secondary CPUs should conform to the early CPU features
1905          * in use by the kernel based on boot CPU.
1906          */
1907         check_early_cpu_features();
1908
1909         /*
1910          * If we haven't finalised the system capabilities, this CPU gets
1911          * a chance to update the errata work arounds and local features.
1912          * Otherwise, this CPU should verify that it has all the system
1913          * advertised capabilities.
1914          */
1915         if (!sys_caps_initialised)
1916                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1917         else
1918                 verify_local_cpu_capabilities();
1919 }
1920
1921 static void __init setup_boot_cpu_capabilities(void)
1922 {
1923         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1924         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1925         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1926         enable_cpu_capabilities(SCOPE_BOOT_CPU);
1927 }
1928
1929 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1930 EXPORT_SYMBOL(arm64_const_caps_ready);
1931
1932 static void __init mark_const_caps_ready(void)
1933 {
1934         static_branch_enable(&arm64_const_caps_ready);
1935 }
1936
1937 bool this_cpu_has_cap(unsigned int n)
1938 {
1939         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
1940                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
1941
1942                 if (cap)
1943                         return cap->matches(cap, SCOPE_LOCAL_CPU);
1944         }
1945
1946         return false;
1947 }
1948
1949 static void __init setup_system_capabilities(void)
1950 {
1951         /*
1952          * We have finalised the system-wide safe feature
1953          * registers, finalise the capabilities that depend
1954          * on it. Also enable all the available capabilities,
1955          * that are not enabled already.
1956          */
1957         update_cpu_capabilities(SCOPE_SYSTEM);
1958         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
1959 }
1960
1961 void __init setup_cpu_features(void)
1962 {
1963         u32 cwg;
1964
1965         setup_system_capabilities();
1966         mark_const_caps_ready();
1967         setup_elf_hwcaps(arm64_elf_hwcaps);
1968
1969         if (system_supports_32bit_el0())
1970                 setup_elf_hwcaps(compat_elf_hwcaps);
1971
1972         if (system_uses_ttbr0_pan())
1973                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
1974
1975         sve_setup();
1976         minsigstksz_setup();
1977
1978         /* Advertise that we have computed the system capabilities */
1979         set_sys_caps_initialised();
1980
1981         /*
1982          * Check for sane CTR_EL0.CWG value.
1983          */
1984         cwg = cache_type_cwg();
1985         if (!cwg)
1986                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
1987                         ARCH_DMA_MINALIGN);
1988 }
1989
1990 static bool __maybe_unused
1991 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1992 {
1993         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
1994 }
1995
1996 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
1997 {
1998         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
1999 }
2000
2001 /*
2002  * We emulate only the following system register space.
2003  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2004  * See Table C5-6 System instruction encodings for System register accesses,
2005  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2006  */
2007 static inline bool __attribute_const__ is_emulated(u32 id)
2008 {
2009         return (sys_reg_Op0(id) == 0x3 &&
2010                 sys_reg_CRn(id) == 0x0 &&
2011                 sys_reg_Op1(id) == 0x0 &&
2012                 (sys_reg_CRm(id) == 0 ||
2013                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2014 }
2015
2016 /*
2017  * With CRm == 0, reg should be one of :
2018  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2019  */
2020 static inline int emulate_id_reg(u32 id, u64 *valp)
2021 {
2022         switch (id) {
2023         case SYS_MIDR_EL1:
2024                 *valp = read_cpuid_id();
2025                 break;
2026         case SYS_MPIDR_EL1:
2027                 *valp = SYS_MPIDR_SAFE_VAL;
2028                 break;
2029         case SYS_REVIDR_EL1:
2030                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2031                 *valp = 0;
2032                 break;
2033         default:
2034                 return -EINVAL;
2035         }
2036
2037         return 0;
2038 }
2039
2040 static int emulate_sys_reg(u32 id, u64 *valp)
2041 {
2042         struct arm64_ftr_reg *regp;
2043
2044         if (!is_emulated(id))
2045                 return -EINVAL;
2046
2047         if (sys_reg_CRm(id) == 0)
2048                 return emulate_id_reg(id, valp);
2049
2050         regp = get_arm64_ftr_reg(id);
2051         if (regp)
2052                 *valp = arm64_ftr_reg_user_value(regp);
2053         else
2054                 /*
2055                  * The untracked registers are either IMPLEMENTATION DEFINED
2056                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
2057                  */
2058                 *valp = 0;
2059         return 0;
2060 }
2061
2062 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2063 {
2064         int rc;
2065         u64 val;
2066
2067         rc = emulate_sys_reg(sys_reg, &val);
2068         if (!rc) {
2069                 pt_regs_write_reg(regs, rt, val);
2070                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2071         }
2072         return rc;
2073 }
2074
2075 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2076 {
2077         u32 sys_reg, rt;
2078
2079         /*
2080          * sys_reg values are defined as used in mrs/msr instruction.
2081          * shift the imm value to get the encoding.
2082          */
2083         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2084         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2085         return do_emulate_mrs(regs, sys_reg, rt);
2086 }
2087
2088 static struct undef_hook mrs_hook = {
2089         .instr_mask = 0xfff00000,
2090         .instr_val  = 0xd5300000,
2091         .pstate_mask = PSR_AA32_MODE_MASK,
2092         .pstate_val = PSR_MODE_EL0t,
2093         .fn = emulate_mrs,
2094 };
2095
2096 static int __init enable_mrs_emulation(void)
2097 {
2098         register_undef_hook(&mrs_hook);
2099         return 0;
2100 }
2101
2102 core_initcall(enable_mrs_emulation);