2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/cpumask.h>
23 #include <linux/sort.h>
24 #include <linux/stop_machine.h>
25 #include <linux/types.h>
28 #include <asm/cpufeature.h>
29 #include <asm/cpu_ops.h>
30 #include <asm/fpsimd.h>
31 #include <asm/mmu_context.h>
32 #include <asm/processor.h>
33 #include <asm/sysreg.h>
34 #include <asm/traps.h>
37 unsigned long elf_hwcap __read_mostly;
38 EXPORT_SYMBOL_GPL(elf_hwcap);
41 #define COMPAT_ELF_HWCAP_DEFAULT \
42 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
43 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
44 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
45 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
46 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
48 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
49 unsigned int compat_elf_hwcap2 __read_mostly;
52 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
53 EXPORT_SYMBOL(cpu_hwcaps);
56 * Flag to indicate if we have computed the system wide
57 * capabilities based on the boot time active CPUs. This
58 * will be used to determine if a new booting CPU should
59 * go through the verification process to make sure that it
60 * supports the system capabilities, without using a hotplug
63 static bool sys_caps_initialised;
65 static inline void set_sys_caps_initialised(void)
67 sys_caps_initialised = true;
70 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
72 /* file-wide pr_fmt adds "CPU features: " prefix */
73 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
77 static struct notifier_block cpu_hwcaps_notifier = {
78 .notifier_call = dump_cpu_hwcaps
81 static int __init register_cpu_hwcaps_dumper(void)
83 atomic_notifier_chain_register(&panic_notifier_list,
84 &cpu_hwcaps_notifier);
87 __initcall(register_cpu_hwcaps_dumper);
89 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
90 EXPORT_SYMBOL(cpu_hwcap_keys);
92 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
100 .safe_val = SAFE_VAL, \
103 /* Define a feature with unsigned values */
104 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
105 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
107 /* Define a feature with a signed value */
108 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
109 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
111 #define ARM64_FTR_END \
116 /* meta feature for alternatives */
117 static bool __maybe_unused
118 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
122 * NOTE: Any changes to the visibility of features should be kept in
123 * sync with the documentation of the CPU feature register ABI.
125 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
126 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
128 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
134 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
135 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
136 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
140 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
141 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
142 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
143 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
144 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
148 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
149 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
150 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
151 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
152 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
153 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
154 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
155 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
156 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
157 /* Linux doesn't care about the EL3 */
158 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
159 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
160 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
161 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
165 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
166 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
167 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
169 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
170 /* Linux shouldn't care about secure memory */
171 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
172 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
173 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
175 * Differing PARange is fine as long as all peripherals and memory are mapped
176 * within the minimum PARange of all CPUs
178 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
182 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
183 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
184 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
185 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
186 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
187 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
188 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
192 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
193 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
201 static const struct arm64_ftr_bits ftr_ctr[] = {
202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
207 * Linux can handle differing I-cache policies. Userspace JITs will
208 * make use of *minLine.
209 * If we have differing I-cache policies, report it as the weakest - VIPT.
211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
216 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
217 .name = "SYS_CTR_EL0",
221 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
222 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
223 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
227 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
233 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
240 * We can instantiate multiple PMU instances with different levels
243 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
249 static const struct arm64_ftr_bits ftr_mvfr2[] = {
250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
255 static const struct arm64_ftr_bits ftr_dczid[] = {
256 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
262 static const struct arm64_ftr_bits ftr_id_isar5[] = {
263 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
264 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
265 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
266 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
272 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
273 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
277 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
285 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
287 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
297 static const struct arm64_ftr_bits ftr_zcr[] = {
298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
299 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
304 * Common ftr bits for a 32bit register with all hidden, strict
305 * attributes, with 4bit feature fields and a default safe value of
306 * 0. Covers the following 32bit registers:
307 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
309 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
321 /* Table for a single 32bit feature value */
322 static const struct arm64_ftr_bits ftr_single32[] = {
323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
327 static const struct arm64_ftr_bits ftr_raz[] = {
331 #define ARM64_FTR_REG(id, table) { \
333 .reg = &(struct arm64_ftr_reg){ \
335 .ftr_bits = &((table)[0]), \
338 static const struct __ftr_reg_entry {
340 struct arm64_ftr_reg *reg;
341 } arm64_ftr_regs[] = {
343 /* Op1 = 0, CRn = 0, CRm = 1 */
344 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
345 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
346 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
347 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
348 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
349 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
350 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
352 /* Op1 = 0, CRn = 0, CRm = 2 */
353 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
354 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
355 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
356 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
357 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
358 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
359 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
361 /* Op1 = 0, CRn = 0, CRm = 3 */
362 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
363 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
364 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
366 /* Op1 = 0, CRn = 0, CRm = 4 */
367 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
368 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz),
369 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz),
371 /* Op1 = 0, CRn = 0, CRm = 5 */
372 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
373 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
375 /* Op1 = 0, CRn = 0, CRm = 6 */
376 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
377 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
379 /* Op1 = 0, CRn = 0, CRm = 7 */
380 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
381 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
382 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
384 /* Op1 = 0, CRn = 1, CRm = 2 */
385 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
387 /* Op1 = 3, CRn = 0, CRm = 0 */
388 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
389 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
391 /* Op1 = 3, CRn = 14, CRm = 0 */
392 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
395 static int search_cmp_ftr_reg(const void *id, const void *regp)
397 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
401 * get_arm64_ftr_reg - Lookup a feature register entry using its
402 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
403 * ascending order of sys_id , we use binary search to find a matching
406 * returns - Upon success, matching ftr_reg entry for id.
407 * - NULL on failure. It is upto the caller to decide
408 * the impact of a failure.
410 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
412 const struct __ftr_reg_entry *ret;
414 ret = bsearch((const void *)(unsigned long)sys_id,
416 ARRAY_SIZE(arm64_ftr_regs),
417 sizeof(arm64_ftr_regs[0]),
424 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
427 u64 mask = arm64_ftr_mask(ftrp);
430 reg |= (ftr_val << ftrp->shift) & mask;
434 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
439 switch (ftrp->type) {
441 ret = ftrp->safe_val;
444 ret = new < cur ? new : cur;
446 case FTR_HIGHER_SAFE:
447 ret = new > cur ? new : cur;
456 static void __init sort_ftr_regs(void)
460 /* Check that the array is sorted so that we can do the binary search */
461 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
462 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
466 * Initialise the CPU feature register from Boot CPU values.
467 * Also initiliases the strict_mask for the register.
468 * Any bits that are not covered by an arm64_ftr_bits entry are considered
469 * RES0 for the system-wide value, and must strictly match.
471 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
474 u64 strict_mask = ~0x0ULL;
478 const struct arm64_ftr_bits *ftrp;
479 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
483 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
484 u64 ftr_mask = arm64_ftr_mask(ftrp);
485 s64 ftr_new = arm64_ftr_value(ftrp, new);
487 val = arm64_ftr_set_value(ftrp, val, ftr_new);
489 valid_mask |= ftr_mask;
491 strict_mask &= ~ftr_mask;
493 user_mask |= ftr_mask;
495 reg->user_val = arm64_ftr_set_value(ftrp,
503 reg->strict_mask = strict_mask;
504 reg->user_mask = user_mask;
507 void __init init_cpu_features(struct cpuinfo_arm64 *info)
509 /* Before we start using the tables, make sure it is sorted */
512 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
513 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
514 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
515 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
516 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
517 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
518 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
519 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
520 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
521 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
522 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
523 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
524 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
526 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
527 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
528 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
529 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
530 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
531 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
532 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
533 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
534 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
535 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
536 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
537 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
538 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
539 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
540 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
541 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
542 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
545 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
546 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
551 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
553 const struct arm64_ftr_bits *ftrp;
555 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
556 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
557 s64 ftr_new = arm64_ftr_value(ftrp, new);
559 if (ftr_cur == ftr_new)
561 /* Find a safe value */
562 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
563 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
568 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
570 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
573 update_cpu_ftr_reg(regp, val);
574 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
576 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
577 regp->name, boot, cpu, val);
582 * Update system wide CPU feature registers with the values from a
583 * non-boot CPU. Also performs SANITY checks to make sure that there
584 * aren't any insane variations from that of the boot CPU.
586 void update_cpu_features(int cpu,
587 struct cpuinfo_arm64 *info,
588 struct cpuinfo_arm64 *boot)
593 * The kernel can handle differing I-cache policies, but otherwise
594 * caches should look identical. Userspace JITs will make use of
597 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
598 info->reg_ctr, boot->reg_ctr);
601 * Userspace may perform DC ZVA instructions. Mismatched block sizes
602 * could result in too much or too little memory being zeroed if a
603 * process is preempted and migrated between CPUs.
605 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
606 info->reg_dczid, boot->reg_dczid);
608 /* If different, timekeeping will be broken (especially with KVM) */
609 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
610 info->reg_cntfrq, boot->reg_cntfrq);
613 * The kernel uses self-hosted debug features and expects CPUs to
614 * support identical debug features. We presently need CTX_CMPs, WRPs,
615 * and BRPs to be identical.
616 * ID_AA64DFR1 is currently RES0.
618 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
619 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
620 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
621 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
623 * Even in big.LITTLE, processors should be identical instruction-set
626 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
627 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
628 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
629 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
632 * Differing PARange support is fine as long as all peripherals and
633 * memory are mapped within the minimum PARange of all CPUs.
634 * Linux should not care about secure memory.
636 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
637 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
638 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
639 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
640 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
641 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
644 * EL3 is not our concern.
645 * ID_AA64PFR1 is currently RES0.
647 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
648 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
649 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
650 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
652 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
653 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
656 * If we have AArch32, we care about 32-bit features for compat.
657 * If the system doesn't support AArch32, don't update them.
659 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
660 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
662 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
663 info->reg_id_dfr0, boot->reg_id_dfr0);
664 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
665 info->reg_id_isar0, boot->reg_id_isar0);
666 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
667 info->reg_id_isar1, boot->reg_id_isar1);
668 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
669 info->reg_id_isar2, boot->reg_id_isar2);
670 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
671 info->reg_id_isar3, boot->reg_id_isar3);
672 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
673 info->reg_id_isar4, boot->reg_id_isar4);
674 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
675 info->reg_id_isar5, boot->reg_id_isar5);
678 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
679 * ACTLR formats could differ across CPUs and therefore would have to
680 * be trapped for virtualization anyway.
682 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
683 info->reg_id_mmfr0, boot->reg_id_mmfr0);
684 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
685 info->reg_id_mmfr1, boot->reg_id_mmfr1);
686 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
687 info->reg_id_mmfr2, boot->reg_id_mmfr2);
688 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
689 info->reg_id_mmfr3, boot->reg_id_mmfr3);
690 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
691 info->reg_id_pfr0, boot->reg_id_pfr0);
692 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
693 info->reg_id_pfr1, boot->reg_id_pfr1);
694 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
695 info->reg_mvfr0, boot->reg_mvfr0);
696 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
697 info->reg_mvfr1, boot->reg_mvfr1);
698 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
699 info->reg_mvfr2, boot->reg_mvfr2);
702 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
703 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
704 info->reg_zcr, boot->reg_zcr);
706 /* Probe vector lengths, unless we already gave up on SVE */
707 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
708 !sys_caps_initialised)
713 * Mismatched CPU features are a recipe for disaster. Don't even
714 * pretend to support them.
717 pr_warn_once("Unsupported CPU feature variation detected.\n");
718 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
722 u64 read_sanitised_ftr_reg(u32 id)
724 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
726 /* We shouldn't get a request for an unsupported register */
728 return regp->sys_val;
731 #define read_sysreg_case(r) \
732 case r: return read_sysreg_s(r)
735 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
736 * Read the system register on the current CPU
738 static u64 __read_sysreg_by_encoding(u32 sys_id)
741 read_sysreg_case(SYS_ID_PFR0_EL1);
742 read_sysreg_case(SYS_ID_PFR1_EL1);
743 read_sysreg_case(SYS_ID_DFR0_EL1);
744 read_sysreg_case(SYS_ID_MMFR0_EL1);
745 read_sysreg_case(SYS_ID_MMFR1_EL1);
746 read_sysreg_case(SYS_ID_MMFR2_EL1);
747 read_sysreg_case(SYS_ID_MMFR3_EL1);
748 read_sysreg_case(SYS_ID_ISAR0_EL1);
749 read_sysreg_case(SYS_ID_ISAR1_EL1);
750 read_sysreg_case(SYS_ID_ISAR2_EL1);
751 read_sysreg_case(SYS_ID_ISAR3_EL1);
752 read_sysreg_case(SYS_ID_ISAR4_EL1);
753 read_sysreg_case(SYS_ID_ISAR5_EL1);
754 read_sysreg_case(SYS_MVFR0_EL1);
755 read_sysreg_case(SYS_MVFR1_EL1);
756 read_sysreg_case(SYS_MVFR2_EL1);
758 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
759 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
760 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
761 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
762 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
763 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
764 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
765 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
766 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
768 read_sysreg_case(SYS_CNTFRQ_EL0);
769 read_sysreg_case(SYS_CTR_EL0);
770 read_sysreg_case(SYS_DCZID_EL0);
778 #include <linux/irqchip/arm-gic-v3.h>
781 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
783 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
785 return val >= entry->min_field_value;
789 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
793 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
794 if (scope == SCOPE_SYSTEM)
795 val = read_sanitised_ftr_reg(entry->sys_reg);
797 val = __read_sysreg_by_encoding(entry->sys_reg);
799 return feature_matches(val, entry);
802 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
806 if (!has_cpuid_feature(entry, scope))
809 has_sre = gic_enable_sre();
811 pr_warn_once("%s present but disabled by higher exception level\n",
817 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
819 u32 midr = read_cpuid_id();
821 /* Cavium ThunderX pass 1.x and 2.x */
822 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
823 MIDR_CPU_VAR_REV(0, 0),
824 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
827 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
829 return is_kernel_in_hyp_mode();
832 static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
835 phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
838 * Activate the lower HYP offset only if:
839 * - the idmap doesn't clash with it,
840 * - the kernel is not running at EL2.
842 return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
845 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
847 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
849 return cpuid_feature_extract_signed_field(pfr0,
850 ID_AA64PFR0_FP_SHIFT) < 0;
853 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
854 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
856 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
859 char const *str = "command line option";
860 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
863 * For reasons that aren't entirely clear, enabling KPTI on Cavium
864 * ThunderX leads to apparent I-cache corruption of kernel text, which
865 * ends as well as you might imagine. Don't even try.
867 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
868 str = "ARM64_WORKAROUND_CAVIUM_27456";
874 pr_info_once("kernel page table isolation forced %s by %s\n",
875 __kpti_forced > 0 ? "ON" : "OFF", str);
876 return __kpti_forced > 0;
879 /* Useful for KASLR robustness */
880 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
883 /* Don't force KPTI for CPUs that are not vulnerable */
884 switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) {
885 case MIDR_CAVIUM_THUNDERX2:
886 case MIDR_BRCM_VULCAN:
890 /* Defer to CPU feature registers */
891 return !cpuid_feature_extract_unsigned_field(pfr0,
892 ID_AA64PFR0_CSV3_SHIFT);
895 static int kpti_install_ng_mappings(void *__unused)
897 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
898 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
899 kpti_remap_fn *remap_fn;
901 static bool kpti_applied = false;
902 int cpu = smp_processor_id();
907 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
910 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
911 cpu_uninstall_idmap();
919 static int __init parse_kpti(char *str)
922 int ret = strtobool(str, &enabled);
927 __kpti_forced = enabled ? 1 : -1;
930 __setup("kpti=", parse_kpti);
931 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
933 static int cpu_copy_el2regs(void *__unused)
936 * Copy register values that aren't redirected by hardware.
938 * Before code patching, we only set tpidr_el1, all CPUs need to copy
939 * this value to tpidr_el2 before we patch the code. Once we've done
940 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
943 if (!alternatives_applied)
944 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
949 static const struct arm64_cpu_capabilities arm64_features[] = {
951 .desc = "GIC system register CPU interface",
952 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
953 .def_scope = SCOPE_SYSTEM,
954 .matches = has_useable_gicv3_cpuif,
955 .sys_reg = SYS_ID_AA64PFR0_EL1,
956 .field_pos = ID_AA64PFR0_GIC_SHIFT,
957 .sign = FTR_UNSIGNED,
958 .min_field_value = 1,
960 #ifdef CONFIG_ARM64_PAN
962 .desc = "Privileged Access Never",
963 .capability = ARM64_HAS_PAN,
964 .def_scope = SCOPE_SYSTEM,
965 .matches = has_cpuid_feature,
966 .sys_reg = SYS_ID_AA64MMFR1_EL1,
967 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
968 .sign = FTR_UNSIGNED,
969 .min_field_value = 1,
970 .enable = cpu_enable_pan,
972 #endif /* CONFIG_ARM64_PAN */
973 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
975 .desc = "LSE atomic instructions",
976 .capability = ARM64_HAS_LSE_ATOMICS,
977 .def_scope = SCOPE_SYSTEM,
978 .matches = has_cpuid_feature,
979 .sys_reg = SYS_ID_AA64ISAR0_EL1,
980 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
981 .sign = FTR_UNSIGNED,
982 .min_field_value = 2,
984 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
986 .desc = "Software prefetching using PRFM",
987 .capability = ARM64_HAS_NO_HW_PREFETCH,
988 .def_scope = SCOPE_SYSTEM,
989 .matches = has_no_hw_prefetch,
991 #ifdef CONFIG_ARM64_UAO
993 .desc = "User Access Override",
994 .capability = ARM64_HAS_UAO,
995 .def_scope = SCOPE_SYSTEM,
996 .matches = has_cpuid_feature,
997 .sys_reg = SYS_ID_AA64MMFR2_EL1,
998 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
999 .min_field_value = 1,
1001 * We rely on stop_machine() calling uao_thread_switch() to set
1002 * UAO immediately after patching.
1005 #endif /* CONFIG_ARM64_UAO */
1006 #ifdef CONFIG_ARM64_PAN
1008 .capability = ARM64_ALT_PAN_NOT_UAO,
1009 .def_scope = SCOPE_SYSTEM,
1010 .matches = cpufeature_pan_not_uao,
1012 #endif /* CONFIG_ARM64_PAN */
1014 .desc = "Virtualization Host Extensions",
1015 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1016 .def_scope = SCOPE_SYSTEM,
1017 .matches = runs_at_el2,
1018 .enable = cpu_copy_el2regs,
1021 .desc = "32-bit EL0 Support",
1022 .capability = ARM64_HAS_32BIT_EL0,
1023 .def_scope = SCOPE_SYSTEM,
1024 .matches = has_cpuid_feature,
1025 .sys_reg = SYS_ID_AA64PFR0_EL1,
1026 .sign = FTR_UNSIGNED,
1027 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1028 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1031 .desc = "Reduced HYP mapping offset",
1032 .capability = ARM64_HYP_OFFSET_LOW,
1033 .def_scope = SCOPE_SYSTEM,
1034 .matches = hyp_offset_low,
1036 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1038 .desc = "Kernel page table isolation (KPTI)",
1039 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1040 .def_scope = SCOPE_SYSTEM,
1041 .matches = unmap_kernel_at_el0,
1042 .enable = kpti_install_ng_mappings,
1046 /* FP/SIMD is not implemented */
1047 .capability = ARM64_HAS_NO_FPSIMD,
1048 .def_scope = SCOPE_SYSTEM,
1049 .min_field_value = 0,
1050 .matches = has_no_fpsimd,
1052 #ifdef CONFIG_ARM64_PMEM
1054 .desc = "Data cache clean to Point of Persistence",
1055 .capability = ARM64_HAS_DCPOP,
1056 .def_scope = SCOPE_SYSTEM,
1057 .matches = has_cpuid_feature,
1058 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1059 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1060 .min_field_value = 1,
1063 #ifdef CONFIG_ARM64_SVE
1065 .desc = "Scalable Vector Extension",
1066 .capability = ARM64_SVE,
1067 .def_scope = SCOPE_SYSTEM,
1068 .sys_reg = SYS_ID_AA64PFR0_EL1,
1069 .sign = FTR_UNSIGNED,
1070 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1071 .min_field_value = ID_AA64PFR0_SVE,
1072 .matches = has_cpuid_feature,
1073 .enable = sve_kernel_enable,
1075 #endif /* CONFIG_ARM64_SVE */
1076 #ifdef CONFIG_ARM64_RAS_EXTN
1078 .desc = "RAS Extension Support",
1079 .capability = ARM64_HAS_RAS_EXTN,
1080 .def_scope = SCOPE_SYSTEM,
1081 .matches = has_cpuid_feature,
1082 .sys_reg = SYS_ID_AA64PFR0_EL1,
1083 .sign = FTR_UNSIGNED,
1084 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1085 .min_field_value = ID_AA64PFR0_RAS_V1,
1086 .enable = cpu_clear_disr,
1088 #endif /* CONFIG_ARM64_RAS_EXTN */
1092 #define HWCAP_CAP(reg, field, s, min_value, type, cap) \
1095 .def_scope = SCOPE_SYSTEM, \
1096 .matches = has_cpuid_feature, \
1098 .field_pos = field, \
1100 .min_field_value = min_value, \
1101 .hwcap_type = type, \
1105 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1106 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1107 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1108 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1109 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
1110 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
1111 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1112 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
1113 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
1114 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1115 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1116 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1117 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
1118 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
1119 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
1120 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
1121 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
1122 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
1123 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
1124 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
1125 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
1126 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
1127 #ifdef CONFIG_ARM64_SVE
1128 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
1133 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1134 #ifdef CONFIG_COMPAT
1135 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1136 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1137 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1138 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1139 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1144 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1146 switch (cap->hwcap_type) {
1148 elf_hwcap |= cap->hwcap;
1150 #ifdef CONFIG_COMPAT
1151 case CAP_COMPAT_HWCAP:
1152 compat_elf_hwcap |= (u32)cap->hwcap;
1154 case CAP_COMPAT_HWCAP2:
1155 compat_elf_hwcap2 |= (u32)cap->hwcap;
1164 /* Check if we have a particular HWCAP enabled */
1165 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1169 switch (cap->hwcap_type) {
1171 rc = (elf_hwcap & cap->hwcap) != 0;
1173 #ifdef CONFIG_COMPAT
1174 case CAP_COMPAT_HWCAP:
1175 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1177 case CAP_COMPAT_HWCAP2:
1178 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1189 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1191 /* We support emulation of accesses to CPU ID feature registers */
1192 elf_hwcap |= HWCAP_CPUID;
1193 for (; hwcaps->matches; hwcaps++)
1194 if (hwcaps->matches(hwcaps, hwcaps->def_scope))
1195 cap_set_elf_hwcap(hwcaps);
1199 * Check if the current CPU has a given feature capability.
1200 * Should be called from non-preemptible context.
1202 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1205 const struct arm64_cpu_capabilities *caps;
1207 if (WARN_ON(preemptible()))
1210 for (caps = cap_array; caps->matches; caps++)
1211 if (caps->capability == cap &&
1212 caps->matches(caps, SCOPE_LOCAL_CPU))
1217 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1220 for (; caps->matches; caps++) {
1221 if (!caps->matches(caps, caps->def_scope))
1224 if (!cpus_have_cap(caps->capability) && caps->desc)
1225 pr_info("%s %s\n", info, caps->desc);
1226 cpus_set_cap(caps->capability);
1231 * Run through the enabled capabilities and enable() it on all active
1234 void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
1236 for (; caps->matches; caps++) {
1237 unsigned int num = caps->capability;
1239 if (!cpus_have_cap(num))
1242 /* Ensure cpus_have_const_cap(num) works */
1243 static_branch_enable(&cpu_hwcap_keys[num]);
1247 * Use stop_machine() as it schedules the work allowing
1248 * us to modify PSTATE, instead of on_each_cpu() which
1249 * uses an IPI, giving us a PSTATE that disappears when
1252 stop_machine(caps->enable, (void *)caps, cpu_online_mask);
1258 * Check for CPU features that are used in early boot
1259 * based on the Boot CPU value.
1261 static void check_early_cpu_features(void)
1263 verify_cpu_run_el();
1264 verify_cpu_asid_bits();
1268 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1271 for (; caps->matches; caps++)
1272 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1273 pr_crit("CPU%d: missing HWCAP: %s\n",
1274 smp_processor_id(), caps->desc);
1280 verify_local_cpu_features(const struct arm64_cpu_capabilities *caps_list)
1282 const struct arm64_cpu_capabilities *caps = caps_list;
1283 for (; caps->matches; caps++) {
1284 if (!cpus_have_cap(caps->capability))
1287 * If the new CPU misses an advertised feature, we cannot proceed
1288 * further, park the cpu.
1290 if (!__this_cpu_has_cap(caps_list, caps->capability)) {
1291 pr_crit("CPU%d: missing feature: %s\n",
1292 smp_processor_id(), caps->desc);
1296 caps->enable((void *)caps);
1300 static void verify_sve_features(void)
1302 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1303 u64 zcr = read_zcr_features();
1305 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1306 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1308 if (len < safe_len || sve_verify_vq_map()) {
1309 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1310 smp_processor_id());
1314 /* Add checks on other ZCR bits here if necessary */
1318 * Run through the enabled system capabilities and enable() it on this CPU.
1319 * The capabilities were decided based on the available CPUs at the boot time.
1320 * Any new CPU should match the system wide status of the capability. If the
1321 * new CPU doesn't have a capability which the system now has enabled, we
1322 * cannot do anything to fix it up and could cause unexpected failures. So
1325 static void verify_local_cpu_capabilities(void)
1327 verify_local_cpu_errata_workarounds();
1328 verify_local_cpu_features(arm64_features);
1329 verify_local_elf_hwcaps(arm64_elf_hwcaps);
1331 if (system_supports_32bit_el0())
1332 verify_local_elf_hwcaps(compat_elf_hwcaps);
1334 if (system_supports_sve())
1335 verify_sve_features();
1337 if (system_uses_ttbr0_pan())
1338 pr_info("Emulating Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
1341 void check_local_cpu_capabilities(void)
1344 * All secondary CPUs should conform to the early CPU features
1345 * in use by the kernel based on boot CPU.
1347 check_early_cpu_features();
1350 * If we haven't finalised the system capabilities, this CPU gets
1351 * a chance to update the errata work arounds.
1352 * Otherwise, this CPU should verify that it has all the system
1353 * advertised capabilities.
1355 if (!sys_caps_initialised)
1356 update_cpu_errata_workarounds();
1358 verify_local_cpu_capabilities();
1361 static void __init setup_feature_capabilities(void)
1363 update_cpu_capabilities(arm64_features, "detected feature:");
1364 enable_cpu_capabilities(arm64_features);
1367 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1368 EXPORT_SYMBOL(arm64_const_caps_ready);
1370 static void __init mark_const_caps_ready(void)
1372 static_branch_enable(&arm64_const_caps_ready);
1375 extern const struct arm64_cpu_capabilities arm64_errata[];
1377 bool this_cpu_has_cap(unsigned int cap)
1379 return (__this_cpu_has_cap(arm64_features, cap) ||
1380 __this_cpu_has_cap(arm64_errata, cap));
1383 void __init setup_cpu_features(void)
1388 /* Set the CPU feature capabilies */
1389 setup_feature_capabilities();
1390 enable_errata_workarounds();
1391 mark_const_caps_ready();
1392 setup_elf_hwcaps(arm64_elf_hwcaps);
1394 if (system_supports_32bit_el0())
1395 setup_elf_hwcaps(compat_elf_hwcaps);
1399 /* Advertise that we have computed the system capabilities */
1400 set_sys_caps_initialised();
1403 * Check for sane CTR_EL0.CWG value.
1405 cwg = cache_type_cwg();
1406 cls = cache_line_size();
1408 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1410 if (L1_CACHE_BYTES < cls)
1411 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1412 L1_CACHE_BYTES, cls);
1415 static bool __maybe_unused
1416 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1418 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
1422 * We emulate only the following system register space.
1423 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1424 * See Table C5-6 System instruction encodings for System register accesses,
1425 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1427 static inline bool __attribute_const__ is_emulated(u32 id)
1429 return (sys_reg_Op0(id) == 0x3 &&
1430 sys_reg_CRn(id) == 0x0 &&
1431 sys_reg_Op1(id) == 0x0 &&
1432 (sys_reg_CRm(id) == 0 ||
1433 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1437 * With CRm == 0, reg should be one of :
1438 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1440 static inline int emulate_id_reg(u32 id, u64 *valp)
1444 *valp = read_cpuid_id();
1447 *valp = SYS_MPIDR_SAFE_VAL;
1449 case SYS_REVIDR_EL1:
1450 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1460 static int emulate_sys_reg(u32 id, u64 *valp)
1462 struct arm64_ftr_reg *regp;
1464 if (!is_emulated(id))
1467 if (sys_reg_CRm(id) == 0)
1468 return emulate_id_reg(id, valp);
1470 regp = get_arm64_ftr_reg(id);
1472 *valp = arm64_ftr_reg_user_value(regp);
1475 * The untracked registers are either IMPLEMENTATION DEFINED
1476 * (e.g, ID_AFR0_EL1) or reserved RAZ.
1482 static int emulate_mrs(struct pt_regs *regs, u32 insn)
1489 * sys_reg values are defined as used in mrs/msr instruction.
1490 * shift the imm value to get the encoding.
1492 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1493 rc = emulate_sys_reg(sys_reg, &val);
1495 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
1496 pt_regs_write_reg(regs, dst, val);
1497 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1503 static struct undef_hook mrs_hook = {
1504 .instr_mask = 0xfff00000,
1505 .instr_val = 0xd5300000,
1506 .pstate_mask = COMPAT_PSR_MODE_MASK,
1507 .pstate_val = PSR_MODE_EL0t,
1511 static int __init enable_mrs_emulation(void)
1513 register_undef_hook(&mrs_hook);
1517 core_initcall(enable_mrs_emulation);
1519 int cpu_clear_disr(void *__unused)
1521 /* Firmware may have left a deferred SError in this register. */
1522 write_sysreg_s(0, SYS_DISR_EL1);