1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Macros for accessing system registers with older binutils.
5 * Copyright (C) 2014 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
10 #define __ASM_SYSREG_H
12 #include <linux/bits.h>
13 #include <linux/stringify.h>
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
19 * ARMv8 ARM reserves the following encoding for system registers:
20 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
21 * C5.2, version:ARM DDI 0487A.f)
39 #define sys_reg(op0, op1, crn, crm, op2) \
40 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
41 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
44 #define sys_insn sys_reg
46 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
47 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
48 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
49 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
50 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
52 #ifndef CONFIG_BROKEN_GAS_INST
55 // The space separator is omitted so that __emit_inst(x) can be parsed as
56 // either an assembler directive or an assembler macro argument.
57 #define __emit_inst(x) .inst(x)
59 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
62 #else /* CONFIG_BROKEN_GAS_INST */
64 #ifndef CONFIG_CPU_BIG_ENDIAN
65 #define __INSTR_BSWAP(x) (x)
66 #else /* CONFIG_CPU_BIG_ENDIAN */
67 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
68 (((x) << 8) & 0x00ff0000) | \
69 (((x) >> 8) & 0x0000ff00) | \
70 (((x) >> 24) & 0x000000ff))
71 #endif /* CONFIG_CPU_BIG_ENDIAN */
74 #define __emit_inst(x) .long __INSTR_BSWAP(x)
75 #else /* __ASSEMBLY__ */
76 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
77 #endif /* __ASSEMBLY__ */
79 #endif /* CONFIG_BROKEN_GAS_INST */
82 * Instructions for modifying PSTATE fields.
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
84 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
85 * for accessing PSTATE fields have the following encoding:
87 * Op1, Op2 encodes the PSTATE field modified and defines the constraints.
88 * CRm = Imm4 for the instruction.
91 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)
92 #define PSTATE_Imm_shift CRm_shift
93 #define SET_PSTATE(x, r) __emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
95 #define PSTATE_PAN pstate_field(0, 4)
96 #define PSTATE_UAO pstate_field(0, 3)
97 #define PSTATE_SSBS pstate_field(3, 1)
98 #define PSTATE_DIT pstate_field(3, 2)
99 #define PSTATE_TCO pstate_field(3, 4)
101 #define SET_PSTATE_PAN(x) SET_PSTATE((x), PAN)
102 #define SET_PSTATE_UAO(x) SET_PSTATE((x), UAO)
103 #define SET_PSTATE_SSBS(x) SET_PSTATE((x), SSBS)
104 #define SET_PSTATE_DIT(x) SET_PSTATE((x), DIT)
105 #define SET_PSTATE_TCO(x) SET_PSTATE((x), TCO)
107 #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x))
108 #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x))
109 #define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x))
110 #define set_pstate_dit(x) asm volatile(SET_PSTATE_DIT(x))
112 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \
113 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
115 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
117 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
118 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
119 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
122 * Automatically generated definitions for system registers, the
123 * manual encodings below are in the process of being converted to
124 * come from here. The header relies on the definition of sys_reg()
125 * earlier in this file.
127 #include "asm/sysreg-defs.h"
130 * System registers, organised loosely by encoding but grouped together
131 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
133 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
134 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
135 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
137 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
138 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
139 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
140 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
141 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
142 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
143 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
144 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
145 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
146 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
148 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
149 #define SYS_OSLAR_OSLK BIT(0)
151 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
152 #define SYS_OSLSR_OSLM_MASK (BIT(3) | BIT(0))
153 #define SYS_OSLSR_OSLM_NI 0
154 #define SYS_OSLSR_OSLM_IMPLEMENTED BIT(3)
155 #define SYS_OSLSR_OSLK BIT(1)
157 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
158 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
159 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
160 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
161 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
162 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
163 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
164 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
165 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
166 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
168 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
169 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
170 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
172 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
173 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
174 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
176 #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
178 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
180 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
181 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
182 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
183 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
185 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
186 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
187 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
188 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
190 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
191 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
193 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
194 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
196 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
198 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
199 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
200 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
202 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
203 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
204 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
205 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
206 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
207 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
208 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
209 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
210 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
211 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
213 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
215 #define SYS_PAR_EL1_F BIT(0)
216 #define SYS_PAR_EL1_FST GENMASK(6, 1)
218 /*** Statistical Profiling Extension ***/
220 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
221 #define SYS_PMSIDR_EL1_FE_SHIFT 0
222 #define SYS_PMSIDR_EL1_FT_SHIFT 1
223 #define SYS_PMSIDR_EL1_FL_SHIFT 2
224 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3
225 #define SYS_PMSIDR_EL1_LDS_SHIFT 4
226 #define SYS_PMSIDR_EL1_ERND_SHIFT 5
227 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8
228 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL
229 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
230 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL
231 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16
232 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL
234 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7)
235 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0
236 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU
237 #define SYS_PMBIDR_EL1_P_SHIFT 4
238 #define SYS_PMBIDR_EL1_F_SHIFT 5
240 /* Sampling controls */
241 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0)
242 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0
243 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1
244 #define SYS_PMSCR_EL1_CX_SHIFT 3
245 #define SYS_PMSCR_EL1_PA_SHIFT 4
246 #define SYS_PMSCR_EL1_TS_SHIFT 5
247 #define SYS_PMSCR_EL1_PCT_SHIFT 6
249 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0)
250 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0
251 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1
252 #define SYS_PMSCR_EL2_CX_SHIFT 3
253 #define SYS_PMSCR_EL2_PA_SHIFT 4
254 #define SYS_PMSCR_EL2_TS_SHIFT 5
255 #define SYS_PMSCR_EL2_PCT_SHIFT 6
257 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2)
259 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3)
260 #define SYS_PMSIRR_EL1_RND_SHIFT 0
261 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8
262 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL
264 /* Filtering controls */
265 #define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1)
267 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4)
268 #define SYS_PMSFCR_EL1_FE_SHIFT 0
269 #define SYS_PMSFCR_EL1_FT_SHIFT 1
270 #define SYS_PMSFCR_EL1_FL_SHIFT 2
271 #define SYS_PMSFCR_EL1_B_SHIFT 16
272 #define SYS_PMSFCR_EL1_LD_SHIFT 17
273 #define SYS_PMSFCR_EL1_ST_SHIFT 18
275 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
276 #define PMSEVFR_EL1_RES0_IMP \
277 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
278 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
279 #define PMSEVFR_EL1_RES0_V1P1 \
280 (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
282 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
283 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
285 /* Buffer controls */
286 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0)
287 #define SYS_PMBLIMITR_EL1_E_SHIFT 0
288 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1
289 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL
290 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
292 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1)
294 /* Buffer error reporting */
295 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3)
296 #define SYS_PMBSR_EL1_COLL_SHIFT 16
297 #define SYS_PMBSR_EL1_S_SHIFT 17
298 #define SYS_PMBSR_EL1_EA_SHIFT 18
299 #define SYS_PMBSR_EL1_DL_SHIFT 19
300 #define SYS_PMBSR_EL1_EC_SHIFT 26
301 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL
303 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
304 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
305 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
307 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0
308 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL
310 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0
311 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL
313 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
315 /*** End of Statistical Profiling Extension ***/
320 #define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0)
321 #define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1)
322 #define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2)
323 #define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3)
324 #define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4)
325 #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6)
326 #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
328 #define TRBLIMITR_LIMIT_MASK GENMASK_ULL(51, 0)
329 #define TRBLIMITR_LIMIT_SHIFT 12
330 #define TRBLIMITR_NVM BIT(5)
331 #define TRBLIMITR_TRIG_MODE_MASK GENMASK(1, 0)
332 #define TRBLIMITR_TRIG_MODE_SHIFT 3
333 #define TRBLIMITR_FILL_MODE_MASK GENMASK(1, 0)
334 #define TRBLIMITR_FILL_MODE_SHIFT 1
335 #define TRBLIMITR_ENABLE BIT(0)
336 #define TRBPTR_PTR_MASK GENMASK_ULL(63, 0)
337 #define TRBPTR_PTR_SHIFT 0
338 #define TRBBASER_BASE_MASK GENMASK_ULL(51, 0)
339 #define TRBBASER_BASE_SHIFT 12
340 #define TRBSR_EC_MASK GENMASK(5, 0)
341 #define TRBSR_EC_SHIFT 26
342 #define TRBSR_IRQ BIT(22)
343 #define TRBSR_TRG BIT(21)
344 #define TRBSR_WRAP BIT(20)
345 #define TRBSR_ABORT BIT(18)
346 #define TRBSR_STOP BIT(17)
347 #define TRBSR_MSS_MASK GENMASK(15, 0)
348 #define TRBSR_MSS_SHIFT 0
349 #define TRBSR_BSC_MASK GENMASK(5, 0)
350 #define TRBSR_BSC_SHIFT 0
351 #define TRBSR_FSC_MASK GENMASK(5, 0)
352 #define TRBSR_FSC_SHIFT 0
353 #define TRBMAR_SHARE_MASK GENMASK(1, 0)
354 #define TRBMAR_SHARE_SHIFT 8
355 #define TRBMAR_OUTER_MASK GENMASK(3, 0)
356 #define TRBMAR_OUTER_SHIFT 4
357 #define TRBMAR_INNER_MASK GENMASK(3, 0)
358 #define TRBMAR_INNER_SHIFT 0
359 #define TRBTRG_TRG_MASK GENMASK(31, 0)
360 #define TRBTRG_TRG_SHIFT 0
361 #define TRBIDR_FLAG BIT(5)
362 #define TRBIDR_PROG BIT(4)
363 #define TRBIDR_ALIGN_MASK GENMASK(3, 0)
364 #define TRBIDR_ALIGN_SHIFT 0
366 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
367 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
369 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
371 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
372 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
374 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
375 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
377 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
378 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
379 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
380 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
381 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
382 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
383 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
384 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
385 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
386 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
387 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
388 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
389 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
390 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
391 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
392 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
393 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
394 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
395 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
396 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
397 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
398 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
399 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
400 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
401 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
402 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
403 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
405 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
407 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
408 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
410 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
411 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
413 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
414 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
415 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
416 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
417 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
418 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
419 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
420 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
421 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
422 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
423 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
424 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
425 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
427 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
428 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
429 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
431 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
433 /* Definitions for system register interface to AMU for ARMv8.4 onwards */
434 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
435 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0)
436 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1)
437 #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2)
438 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
439 #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4)
440 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
441 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
442 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
445 * Group 0 of activity monitors (architected):
446 * op0 op1 CRn CRm op2
447 * Counter: 11 011 1101 010:n<3> n<2:0>
448 * Type: 11 011 1101 011:n<3> n<2:0>
451 * Group 1 of activity monitors (auxiliary):
452 * op0 op1 CRn CRm op2
453 * Counter: 11 011 1101 110:n<3> n<2:0>
454 * Type: 11 011 1101 111:n<3> n<2:0>
458 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
459 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
460 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
461 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
463 /* AMU v1: Fixed (architecturally defined) activity monitors */
464 #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0)
465 #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1)
466 #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2)
467 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
469 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
471 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
472 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
474 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
475 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
476 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
478 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
479 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
481 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
482 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
483 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
485 #define __PMEV_op2(n) ((n) & 0x7)
486 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
487 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
488 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
489 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
491 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
493 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
494 #define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4)
495 #define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5)
496 #define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
497 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
498 #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4)
499 #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5)
500 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
501 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
502 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
503 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
504 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
505 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
506 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
507 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
509 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
510 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
511 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
512 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
513 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
514 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
516 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
517 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
518 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
519 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
520 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
522 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
523 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
524 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
525 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
526 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
527 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
528 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
529 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
531 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
532 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
533 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
534 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
535 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
536 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
537 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
538 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
539 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
541 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
542 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
543 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
544 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
545 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
546 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
547 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
548 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
549 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
551 /* VHE encodings for architectural EL0/1 system registers */
552 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
553 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
554 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
555 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
556 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
557 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
558 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
559 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
560 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
561 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
562 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
563 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
564 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
565 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
566 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
567 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
568 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
569 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
570 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
571 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
573 /* Common SCTLR_ELx flags. */
574 #define SCTLR_ELx_ENTP2 (BIT(60))
575 #define SCTLR_ELx_DSSBS (BIT(44))
576 #define SCTLR_ELx_ATA (BIT(43))
578 #define SCTLR_ELx_ENIA_SHIFT 31
580 #define SCTLR_ELx_ITFSB (BIT(37))
581 #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT))
582 #define SCTLR_ELx_ENIB (BIT(30))
583 #define SCTLR_ELx_LSMAOE (BIT(29))
584 #define SCTLR_ELx_nTLSMD (BIT(28))
585 #define SCTLR_ELx_ENDA (BIT(27))
586 #define SCTLR_ELx_EE (BIT(25))
587 #define SCTLR_ELx_EIS (BIT(22))
588 #define SCTLR_ELx_IESB (BIT(21))
589 #define SCTLR_ELx_TSCXT (BIT(20))
590 #define SCTLR_ELx_WXN (BIT(19))
591 #define SCTLR_ELx_ENDB (BIT(13))
592 #define SCTLR_ELx_I (BIT(12))
593 #define SCTLR_ELx_EOS (BIT(11))
594 #define SCTLR_ELx_SA (BIT(3))
595 #define SCTLR_ELx_C (BIT(2))
596 #define SCTLR_ELx_A (BIT(1))
597 #define SCTLR_ELx_M (BIT(0))
599 /* SCTLR_EL2 specific flags. */
600 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
601 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
604 #ifdef CONFIG_CPU_BIG_ENDIAN
605 #define ENDIAN_SET_EL2 SCTLR_ELx_EE
607 #define ENDIAN_SET_EL2 0
610 #define INIT_SCTLR_EL2_MMU_ON \
611 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \
612 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | \
613 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1)
615 #define INIT_SCTLR_EL2_MMU_OFF \
616 (SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
618 /* SCTLR_EL1 specific flags. */
619 #ifdef CONFIG_CPU_BIG_ENDIAN
620 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
622 #define ENDIAN_SET_EL1 0
625 #define INIT_SCTLR_EL1_MMU_OFF \
626 (ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \
627 SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | SCTLR_EL1_EOS)
629 #define INIT_SCTLR_EL1_MMU_ON \
630 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \
631 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | \
632 SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_nTWE | \
633 SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
634 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | \
635 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \
636 SCTLR_EL1_TSCXT | SCTLR_EL1_EOS)
638 /* MAIR_ELx memory attributes (used by Linux) */
639 #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00)
640 #define MAIR_ATTR_DEVICE_nGnRE UL(0x04)
641 #define MAIR_ATTR_NORMAL_NC UL(0x44)
642 #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0)
643 #define MAIR_ATTR_NORMAL UL(0xff)
644 #define MAIR_ATTR_MASK UL(0xff)
646 /* Position the attr at the correct index */
647 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
650 #define ID_AA64PFR0_EL1_ELx_64BIT_ONLY 0x1
651 #define ID_AA64PFR0_EL1_ELx_32BIT_64BIT 0x2
654 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0
655 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7
656 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0
657 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7
658 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1
659 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf
661 #define ARM64_MIN_PARANGE_BITS 32
663 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0
664 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1
665 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2
666 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7
668 #ifdef CONFIG_ARM64_PA_BITS_52
669 #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52
671 #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48
674 #if defined(CONFIG_ARM64_4K_PAGES)
675 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT
676 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
677 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
678 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
679 #elif defined(CONFIG_ARM64_16K_PAGES)
680 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT
681 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
682 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
683 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT
684 #elif defined(CONFIG_ARM64_64K_PAGES)
685 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN64_SHIFT
686 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN
687 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX
688 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
691 #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
692 #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
694 #define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */
695 #define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */
697 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
698 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
700 /* GCR_EL1 Definitions */
701 #define SYS_GCR_EL1_RRND (BIT(16))
702 #define SYS_GCR_EL1_EXCL_MASK 0xffffUL
704 #ifdef CONFIG_KASAN_HW_TAGS
706 * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
707 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
709 #define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf)
710 #define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf)
711 #define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)
712 #define KERNEL_GCR_EL1_EXCL (SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL)
714 #define KERNEL_GCR_EL1_EXCL SYS_GCR_EL1_EXCL_MASK
717 #define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
719 /* RGSR_EL1 Definitions */
720 #define SYS_RGSR_EL1_TAG_MASK 0xfUL
721 #define SYS_RGSR_EL1_SEED_SHIFT 8
722 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL
724 /* TFSR{,E0}_EL1 bit definitions */
725 #define SYS_TFSR_EL1_TF0_SHIFT 0
726 #define SYS_TFSR_EL1_TF1_SHIFT 1
727 #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
728 #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
730 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
731 #define SYS_MPIDR_SAFE_VAL (BIT(31))
733 #define TRFCR_ELx_TS_SHIFT 5
734 #define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT)
735 #define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
736 #define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
737 #define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
738 #define TRFCR_EL2_CX BIT(3)
739 #define TRFCR_ELx_ExTRE BIT(1)
740 #define TRFCR_ELx_E0TRE BIT(0)
742 /* GIC Hypervisor interface registers */
743 /* ICH_MISR_EL2 bit definitions */
744 #define ICH_MISR_EOI (1 << 0)
745 #define ICH_MISR_U (1 << 1)
747 /* ICH_LR*_EL2 bit definitions */
748 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
750 #define ICH_LR_EOI (1ULL << 41)
751 #define ICH_LR_GROUP (1ULL << 60)
752 #define ICH_LR_HW (1ULL << 61)
753 #define ICH_LR_STATE (3ULL << 62)
754 #define ICH_LR_PENDING_BIT (1ULL << 62)
755 #define ICH_LR_ACTIVE_BIT (1ULL << 63)
756 #define ICH_LR_PHYS_ID_SHIFT 32
757 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
758 #define ICH_LR_PRIORITY_SHIFT 48
759 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
761 /* ICH_HCR_EL2 bit definitions */
762 #define ICH_HCR_EN (1 << 0)
763 #define ICH_HCR_UIE (1 << 1)
764 #define ICH_HCR_NPIE (1 << 3)
765 #define ICH_HCR_TC (1 << 10)
766 #define ICH_HCR_TALL0 (1 << 11)
767 #define ICH_HCR_TALL1 (1 << 12)
768 #define ICH_HCR_TDIR (1 << 14)
769 #define ICH_HCR_EOIcount_SHIFT 27
770 #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT)
772 /* ICH_VMCR_EL2 bit definitions */
773 #define ICH_VMCR_ACK_CTL_SHIFT 2
774 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)
775 #define ICH_VMCR_FIQ_EN_SHIFT 3
776 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT)
777 #define ICH_VMCR_CBPR_SHIFT 4
778 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
779 #define ICH_VMCR_EOIM_SHIFT 9
780 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
781 #define ICH_VMCR_BPR1_SHIFT 18
782 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
783 #define ICH_VMCR_BPR0_SHIFT 21
784 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
785 #define ICH_VMCR_PMR_SHIFT 24
786 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
787 #define ICH_VMCR_ENG0_SHIFT 0
788 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
789 #define ICH_VMCR_ENG1_SHIFT 1
790 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
792 /* ICH_VTR_EL2 bit definitions */
793 #define ICH_VTR_PRI_BITS_SHIFT 29
794 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
795 #define ICH_VTR_ID_BITS_SHIFT 23
796 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
797 #define ICH_VTR_SEIS_SHIFT 22
798 #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
799 #define ICH_VTR_A3V_SHIFT 21
800 #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
801 #define ICH_VTR_TDS_SHIFT 19
802 #define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT)
804 /* HFG[WR]TR_EL2 bit definitions */
805 #define HFGxTR_EL2_nTPIDR2_EL0_SHIFT 55
806 #define HFGxTR_EL2_nTPIDR2_EL0_MASK BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT)
807 #define HFGxTR_EL2_nSMPRI_EL1_SHIFT 54
808 #define HFGxTR_EL2_nSMPRI_EL1_MASK BIT_MASK(HFGxTR_EL2_nSMPRI_EL1_SHIFT)
810 #define ARM64_FEATURE_FIELD_BITS 4
812 /* Create a mask for the feature bits of the specified feature. */
813 #define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
817 .macro mrs_s, rt, sreg
818 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
821 .macro msr_s, sreg, rt
822 __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
827 #include <linux/bitfield.h>
828 #include <linux/build_bug.h>
829 #include <linux/types.h>
830 #include <asm/alternative.h>
832 #define DEFINE_MRS_S \
833 __DEFINE_ASM_GPR_NUMS \
834 " .macro mrs_s, rt, sreg\n" \
835 __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) \
838 #define DEFINE_MSR_S \
839 __DEFINE_ASM_GPR_NUMS \
840 " .macro msr_s, sreg, rt\n" \
841 __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) \
844 #define UNDEFINE_MRS_S \
847 #define UNDEFINE_MSR_S \
850 #define __mrs_s(v, r) \
852 " mrs_s " v ", " __stringify(r) "\n" \
855 #define __msr_s(r, v) \
857 " msr_s " __stringify(r) ", " v "\n" \
861 * Unlike read_cpuid, calls to read_sysreg are never expected to be
862 * optimized away or replaced with synthetic values.
864 #define read_sysreg(r) ({ \
866 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
871 * The "Z" constraint normally means a zero immediate, but when combined with
872 * the "%x0" template means XZR.
874 #define write_sysreg(v, r) do { \
875 u64 __val = (u64)(v); \
876 asm volatile("msr " __stringify(r) ", %x0" \
881 * For registers without architectural names, or simply unsupported by
884 #define read_sysreg_s(r) ({ \
886 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \
890 #define write_sysreg_s(v, r) do { \
891 u64 __val = (u64)(v); \
892 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \
896 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
897 * set mask are set. Other bits are left as-is.
899 #define sysreg_clear_set(sysreg, clear, set) do { \
900 u64 __scs_val = read_sysreg(sysreg); \
901 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
902 if (__scs_new != __scs_val) \
903 write_sysreg(__scs_new, sysreg); \
906 #define sysreg_clear_set_s(sysreg, clear, set) do { \
907 u64 __scs_val = read_sysreg_s(sysreg); \
908 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
909 if (__scs_new != __scs_val) \
910 write_sysreg_s(__scs_new, sysreg); \
913 #define read_sysreg_par() ({ \
915 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \
916 par = read_sysreg(par_el1); \
917 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \
921 #define SYS_FIELD_GET(reg, field, val) \
922 FIELD_GET(reg##_##field##_MASK, val)
924 #define SYS_FIELD_PREP(reg, field, val) \
925 FIELD_PREP(reg##_##field##_MASK, val)
927 #define SYS_FIELD_PREP_ENUM(reg, field, val) \
928 FIELD_PREP(reg##_##field##_MASK, reg##_##field##_##val)
932 #endif /* __ASM_SYSREG_H */