1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 ARM Ltd.
5 #ifndef __ASM_PGTABLE_H
6 #define __ASM_PGTABLE_H
9 #include <asm/proc-fns.h>
11 #include <asm/memory.h>
13 #include <asm/pgtable-hwdef.h>
14 #include <asm/pgtable-prot.h>
15 #include <asm/tlbflush.h>
20 * VMALLOC_START: beginning of the kernel vmalloc space
21 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space
24 #define VMALLOC_START (MODULES_END)
25 #define VMALLOC_END (VMEMMAP_START - SZ_256M)
27 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
31 #include <asm/cmpxchg.h>
32 #include <asm/fixmap.h>
33 #include <linux/mmdebug.h>
34 #include <linux/mm_types.h>
35 #include <linux/sched.h>
36 #include <linux/page_table_check.h>
38 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
39 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
41 /* Set stride and tlb_level in flush_*_tlb_range */
42 #define flush_pmd_tlb_range(vma, addr, end) \
43 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
44 #define flush_pud_tlb_range(vma, addr, end) \
45 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
46 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
48 static inline bool arch_thp_swp_supported(void)
50 return !system_supports_mte();
52 #define arch_thp_swp_supported arch_thp_swp_supported
55 * Outside of a few very special situations (e.g. hibernation), we always
56 * use broadcast TLB invalidation instructions, therefore a spurious page
57 * fault on one CPU which has been handled concurrently by another CPU
58 * does not need to perform additional invalidation.
60 #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0)
63 * ZERO_PAGE is a global shared page that is always zero: used
64 * for zero-mapped memory areas etc..
66 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
67 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page))
69 #define pte_ERROR(e) \
70 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
73 * Macros to convert between a physical address and its placement in a
74 * page table entry, taking care of 52-bit addresses.
76 #ifdef CONFIG_ARM64_PA_BITS_52
77 static inline phys_addr_t __pte_to_phys(pte_t pte)
79 return (pte_val(pte) & PTE_ADDR_LOW) |
80 ((pte_val(pte) & PTE_ADDR_HIGH) << 36);
82 static inline pteval_t __phys_to_pte_val(phys_addr_t phys)
84 return (phys | (phys >> 36)) & PTE_ADDR_MASK;
87 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
88 #define __phys_to_pte_val(phys) (phys)
91 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT)
92 #define pfn_pte(pfn,prot) \
93 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
95 #define pte_none(pte) (!pte_val(pte))
96 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
97 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
100 * The following only work if pte_present(). Undefined behaviour otherwise.
102 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
103 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
104 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
105 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
106 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER))
107 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
108 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
109 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP))
110 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \
111 PTE_ATTRINDX(MT_NORMAL_TAGGED))
113 #define pte_cont_addr_end(addr, end) \
114 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \
115 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
118 #define pmd_cont_addr_end(addr, end) \
119 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \
120 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
123 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
124 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
125 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
127 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
129 * Execute-only user mappings do not have the PTE_USER bit set. All valid
130 * kernel mappings have the PTE_UXN bit set.
132 #define pte_valid_not_user(pte) \
133 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN))
135 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
136 * so that we don't erroneously return false for pages that have been
137 * remapped as PROT_NONE but are yet to be flushed from the TLB.
138 * Note that we can't make any assumptions based on the state of the access
139 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the
142 #define pte_accessible(mm, pte) \
143 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
146 * p??_access_permitted() is true for valid user mappings (PTE_USER
147 * bit set, subject to the write permission check). For execute-only
148 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits
149 * not set) must return false. PROT_NONE mappings do not have the
152 #define pte_access_permitted(pte, write) \
153 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte)))
154 #define pmd_access_permitted(pmd, write) \
155 (pte_access_permitted(pmd_pte(pmd), (write)))
156 #define pud_access_permitted(pud, write) \
157 (pte_access_permitted(pud_pte(pud), (write)))
159 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
161 pte_val(pte) &= ~pgprot_val(prot);
165 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
167 pte_val(pte) |= pgprot_val(prot);
171 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
173 pmd_val(pmd) &= ~pgprot_val(prot);
177 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
179 pmd_val(pmd) |= pgprot_val(prot);
183 static inline pte_t pte_mkwrite(pte_t pte)
185 pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
186 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
190 static inline pte_t pte_mkclean(pte_t pte)
192 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
193 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
198 static inline pte_t pte_mkdirty(pte_t pte)
200 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
203 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
208 static inline pte_t pte_wrprotect(pte_t pte)
211 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
212 * clear), set the PTE_DIRTY bit.
214 if (pte_hw_dirty(pte))
215 pte = pte_mkdirty(pte);
217 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
218 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
222 static inline pte_t pte_mkold(pte_t pte)
224 return clear_pte_bit(pte, __pgprot(PTE_AF));
227 static inline pte_t pte_mkyoung(pte_t pte)
229 return set_pte_bit(pte, __pgprot(PTE_AF));
232 static inline pte_t pte_mkspecial(pte_t pte)
234 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
237 static inline pte_t pte_mkcont(pte_t pte)
239 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
240 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
243 static inline pte_t pte_mknoncont(pte_t pte)
245 return clear_pte_bit(pte, __pgprot(PTE_CONT));
248 static inline pte_t pte_mkpresent(pte_t pte)
250 return set_pte_bit(pte, __pgprot(PTE_VALID));
253 static inline pmd_t pmd_mkcont(pmd_t pmd)
255 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
258 static inline pte_t pte_mkdevmap(pte_t pte)
260 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
263 static inline void set_pte(pte_t *ptep, pte_t pte)
265 WRITE_ONCE(*ptep, pte);
268 * Only if the new pte is valid and kernel, otherwise TLB maintenance
269 * or update_mmu_cache() have the necessary barriers.
271 if (pte_valid_not_user(pte)) {
277 extern void __sync_icache_dcache(pte_t pteval);
280 * PTE bits configuration in the presence of hardware Dirty Bit Management
281 * (PTE_WRITE == PTE_DBM):
283 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
289 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
290 * the page fault mechanism. Checking the dirty status of a pte becomes:
292 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
295 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep,
300 if (!IS_ENABLED(CONFIG_DEBUG_VM))
303 old_pte = READ_ONCE(*ptep);
305 if (!pte_valid(old_pte) || !pte_valid(pte))
307 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
311 * Check for potential race with hardware updates of the pte
312 * (ptep_set_access_flags safely changes valid ptes without going
313 * through an invalid entry).
315 VM_WARN_ONCE(!pte_young(pte),
316 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
317 __func__, pte_val(old_pte), pte_val(pte));
318 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
319 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
320 __func__, pte_val(old_pte), pte_val(pte));
323 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
324 pte_t *ptep, pte_t pte)
326 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
327 __sync_icache_dcache(pte);
330 * If the PTE would provide user space access to the tags associated
331 * with it then ensure that the MTE tags are synchronised. Although
332 * pte_access_permitted() returns false for exec only mappings, they
333 * don't expose tags (instruction fetches don't check tags).
335 if (system_supports_mte() && pte_access_permitted(pte, false) &&
337 pte_t old_pte = READ_ONCE(*ptep);
339 * We only need to synchronise if the new PTE has tags enabled
340 * or if swapping in (in which case another mapping may have
341 * set tags in the past even if this PTE isn't tagged).
342 * (!pte_none() && !pte_present()) is an open coded version of
345 if (pte_tagged(pte) || (!pte_none(old_pte) && !pte_present(old_pte)))
346 mte_sync_tags(old_pte, pte);
349 __check_racy_pte_update(mm, ptep, pte);
354 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
355 pte_t *ptep, pte_t pte)
357 page_table_check_pte_set(mm, addr, ptep, pte);
358 return __set_pte_at(mm, addr, ptep, pte);
362 * Huge pte definitions.
364 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
367 * Hugetlb definitions.
369 #define HUGE_MAX_HSTATE 4
370 #define HPAGE_SHIFT PMD_SHIFT
371 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
372 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
373 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
375 static inline pte_t pgd_pte(pgd_t pgd)
377 return __pte(pgd_val(pgd));
380 static inline pte_t p4d_pte(p4d_t p4d)
382 return __pte(p4d_val(p4d));
385 static inline pte_t pud_pte(pud_t pud)
387 return __pte(pud_val(pud));
390 static inline pud_t pte_pud(pte_t pte)
392 return __pud(pte_val(pte));
395 static inline pmd_t pud_pmd(pud_t pud)
397 return __pmd(pud_val(pud));
400 static inline pte_t pmd_pte(pmd_t pmd)
402 return __pte(pmd_val(pmd));
405 static inline pmd_t pte_pmd(pte_t pte)
407 return __pmd(pte_val(pte));
410 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
412 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT);
415 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
417 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT);
420 #define __HAVE_ARCH_PTE_SWP_EXCLUSIVE
421 static inline pte_t pte_swp_mkexclusive(pte_t pte)
423 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE));
426 static inline int pte_swp_exclusive(pte_t pte)
428 return pte_val(pte) & PTE_SWP_EXCLUSIVE;
431 static inline pte_t pte_swp_clear_exclusive(pte_t pte)
433 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE));
437 * Select all bits except the pfn
439 static inline pgprot_t pte_pgprot(pte_t pte)
441 unsigned long pfn = pte_pfn(pte);
443 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte));
446 #ifdef CONFIG_NUMA_BALANCING
448 * See the comment in include/linux/pgtable.h
450 static inline int pte_protnone(pte_t pte)
452 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
455 static inline int pmd_protnone(pmd_t pmd)
457 return pte_protnone(pmd_pte(pmd));
461 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID))
463 static inline int pmd_present(pmd_t pmd)
465 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd);
472 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
473 static inline int pmd_trans_huge(pmd_t pmd)
475 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
477 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
479 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
480 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
481 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
482 #define pmd_user(pmd) pte_user(pmd_pte(pmd))
483 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd))
484 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd))
485 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
486 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
487 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
488 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
489 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
490 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
492 static inline pmd_t pmd_mkinvalid(pmd_t pmd)
494 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
495 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
500 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
502 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
504 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
506 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
507 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd))
509 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
511 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
514 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
515 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
516 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
517 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
518 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
520 #define pud_young(pud) pte_young(pud_pte(pud))
521 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
522 #define pud_write(pud) pte_write(pud_pte(pud))
524 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
526 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
527 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
528 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
529 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
531 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
532 pmd_t *pmdp, pmd_t pmd)
534 page_table_check_pmd_set(mm, addr, pmdp, pmd);
535 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd));
538 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr,
539 pud_t *pudp, pud_t pud)
541 page_table_check_pud_set(mm, addr, pudp, pud);
542 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud));
545 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d))
546 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys)
548 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd))
549 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
551 #define __pgprot_modify(prot,mask,bits) \
552 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
554 #define pgprot_nx(prot) \
555 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN)
558 * Mark the prot value as uncacheable and unbufferable.
560 #define pgprot_noncached(prot) \
561 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
562 #define pgprot_writecombine(prot) \
563 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
564 #define pgprot_device(prot) \
565 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
566 #define pgprot_tagged(prot) \
567 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED))
568 #define pgprot_mhp pgprot_tagged
570 * DMA allocations for non-coherent devices use what the Arm architecture calls
571 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
572 * and merging of writes. This is different from "Device-nGnR[nE]" memory which
573 * is intended for MMIO and thus forbids speculation, preserves access size,
574 * requires strict alignment and can also force write responses to come from the
577 #define pgprot_dmacoherent(prot) \
578 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
579 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
581 #define __HAVE_PHYS_MEM_ACCESS_PROT
583 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
584 unsigned long size, pgprot_t vma_prot);
586 #define pmd_none(pmd) (!pmd_val(pmd))
588 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
590 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
592 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd))
593 #define pmd_bad(pmd) (!pmd_table(pmd))
595 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE)
596 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE)
598 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
599 static inline bool pud_sect(pud_t pud) { return false; }
600 static inline bool pud_table(pud_t pud) { return true; }
602 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
604 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
608 extern pgd_t init_pg_dir[PTRS_PER_PGD];
609 extern pgd_t init_pg_end[];
610 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
611 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
612 extern pgd_t idmap_pg_end[];
613 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
614 extern pgd_t reserved_pg_dir[PTRS_PER_PGD];
616 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
618 static inline bool in_swapper_pgdir(void *addr)
620 return ((unsigned long)addr & PAGE_MASK) ==
621 ((unsigned long)swapper_pg_dir & PAGE_MASK);
624 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
626 #ifdef __PAGETABLE_PMD_FOLDED
627 if (in_swapper_pgdir(pmdp)) {
628 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
631 #endif /* __PAGETABLE_PMD_FOLDED */
633 WRITE_ONCE(*pmdp, pmd);
635 if (pmd_valid(pmd)) {
641 static inline void pmd_clear(pmd_t *pmdp)
643 set_pmd(pmdp, __pmd(0));
646 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
648 return __pmd_to_phys(pmd);
651 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
653 return (unsigned long)__va(pmd_page_paddr(pmd));
656 /* Find an entry in the third-level page table. */
657 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
659 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
660 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
661 #define pte_clear_fixmap() clear_fixmap(FIX_PTE)
663 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd))
665 /* use ONLY for statically allocated translation tables */
666 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
669 * Conversion functions: convert a page and protection to a page entry,
670 * and a page entry and page directory to the page they refer to.
672 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
674 #if CONFIG_PGTABLE_LEVELS > 2
676 #define pmd_ERROR(e) \
677 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e))
679 #define pud_none(pud) (!pud_val(pud))
680 #define pud_bad(pud) (!pud_table(pud))
681 #define pud_present(pud) pte_present(pud_pte(pud))
682 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud))
683 #define pud_valid(pud) pte_valid(pud_pte(pud))
684 #define pud_user(pud) pte_user(pud_pte(pud))
687 static inline void set_pud(pud_t *pudp, pud_t pud)
689 #ifdef __PAGETABLE_PUD_FOLDED
690 if (in_swapper_pgdir(pudp)) {
691 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
694 #endif /* __PAGETABLE_PUD_FOLDED */
696 WRITE_ONCE(*pudp, pud);
698 if (pud_valid(pud)) {
704 static inline void pud_clear(pud_t *pudp)
706 set_pud(pudp, __pud(0));
709 static inline phys_addr_t pud_page_paddr(pud_t pud)
711 return __pud_to_phys(pud);
714 static inline pmd_t *pud_pgtable(pud_t pud)
716 return (pmd_t *)__va(pud_page_paddr(pud));
719 /* Find an entry in the second-level page table. */
720 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
722 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
723 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
724 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
726 #define pud_page(pud) phys_to_page(__pud_to_phys(pud))
728 /* use ONLY for statically allocated translation tables */
729 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
733 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
735 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
736 #define pmd_set_fixmap(addr) NULL
737 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
738 #define pmd_clear_fixmap()
740 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
742 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
744 #if CONFIG_PGTABLE_LEVELS > 3
746 #define pud_ERROR(e) \
747 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e))
749 #define p4d_none(p4d) (!p4d_val(p4d))
750 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2))
751 #define p4d_present(p4d) (p4d_val(p4d))
753 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
755 if (in_swapper_pgdir(p4dp)) {
756 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d)));
760 WRITE_ONCE(*p4dp, p4d);
765 static inline void p4d_clear(p4d_t *p4dp)
767 set_p4d(p4dp, __p4d(0));
770 static inline phys_addr_t p4d_page_paddr(p4d_t p4d)
772 return __p4d_to_phys(p4d);
775 static inline pud_t *p4d_pgtable(p4d_t p4d)
777 return (pud_t *)__va(p4d_page_paddr(p4d));
780 /* Find an entry in the first-level page table. */
781 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
783 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
784 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr))
785 #define pud_clear_fixmap() clear_fixmap(FIX_PUD)
787 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d)))
789 /* use ONLY for statically allocated translation tables */
790 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
794 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;})
795 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;})
797 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
798 #define pud_set_fixmap(addr) NULL
799 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
800 #define pud_clear_fixmap()
802 #define pud_offset_kimg(dir,addr) ((pud_t *)dir)
804 #endif /* CONFIG_PGTABLE_LEVELS > 3 */
806 #define pgd_ERROR(e) \
807 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
809 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
810 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
812 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
815 * Normal and Normal-Tagged are two different memory types and indices
816 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK.
818 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
819 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP |
821 /* preserve the hardware dirty information */
822 if (pte_hw_dirty(pte))
823 pte = pte_mkdirty(pte);
824 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
828 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
830 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
833 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
834 extern int ptep_set_access_flags(struct vm_area_struct *vma,
835 unsigned long address, pte_t *ptep,
836 pte_t entry, int dirty);
838 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
839 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
840 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
841 unsigned long address, pmd_t *pmdp,
842 pmd_t entry, int dirty)
844 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
847 static inline int pud_devmap(pud_t pud)
852 static inline int pgd_devmap(pgd_t pgd)
858 #ifdef CONFIG_PAGE_TABLE_CHECK
859 static inline bool pte_user_accessible_page(pte_t pte)
861 return pte_present(pte) && (pte_user(pte) || pte_user_exec(pte));
864 static inline bool pmd_user_accessible_page(pmd_t pmd)
866 return pmd_present(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd));
869 static inline bool pud_user_accessible_page(pud_t pud)
871 return pud_present(pud) && pud_user(pud);
876 * Atomic pte/pmd modifications.
878 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
879 static inline int __ptep_test_and_clear_young(pte_t *ptep)
883 pte = READ_ONCE(*ptep);
886 pte = pte_mkold(pte);
887 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
888 pte_val(old_pte), pte_val(pte));
889 } while (pte_val(pte) != pte_val(old_pte));
891 return pte_young(pte);
894 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
895 unsigned long address,
898 return __ptep_test_and_clear_young(ptep);
901 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
902 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
903 unsigned long address, pte_t *ptep)
905 int young = ptep_test_and_clear_young(vma, address, ptep);
909 * We can elide the trailing DSB here since the worst that can
910 * happen is that a CPU continues to use the young entry in its
911 * TLB and we mistakenly reclaim the associated page. The
912 * window for such an event is bounded by the next
913 * context-switch, which provides a DSB to complete the TLB
916 flush_tlb_page_nosync(vma, address);
922 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
923 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
924 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
925 unsigned long address,
928 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
930 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
932 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
933 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
934 unsigned long address, pte_t *ptep)
936 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0));
938 page_table_check_pte_clear(mm, address, pte);
943 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
944 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
945 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
946 unsigned long address, pmd_t *pmdp)
948 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0));
950 page_table_check_pmd_clear(mm, address, pmd);
954 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
957 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
958 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
960 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
961 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
965 pte = READ_ONCE(*ptep);
968 pte = pte_wrprotect(pte);
969 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
970 pte_val(old_pte), pte_val(pte));
971 } while (pte_val(pte) != pte_val(old_pte));
974 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
975 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
976 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
977 unsigned long address, pmd_t *pmdp)
979 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
982 #define pmdp_establish pmdp_establish
983 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
984 unsigned long address, pmd_t *pmdp, pmd_t pmd)
986 page_table_check_pmd_set(vma->vm_mm, address, pmdp, pmd);
987 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
992 * Encode and decode a swap entry:
993 * bits 0-1: present (must be zero)
994 * bits 2: remember PG_anon_exclusive
995 * bits 3-7: swap type
996 * bits 8-57: swap offset
997 * bit 58: PTE_PROT_NONE (must be zero)
999 #define __SWP_TYPE_SHIFT 3
1000 #define __SWP_TYPE_BITS 5
1001 #define __SWP_OFFSET_BITS 50
1002 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
1003 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
1004 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
1006 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
1007 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
1008 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
1010 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1011 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
1013 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
1014 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) })
1015 #define __swp_entry_to_pmd(swp) __pmd((swp).val)
1016 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
1019 * Ensure that there are not more swap files than can be encoded in the kernel
1022 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
1024 #ifdef CONFIG_ARM64_MTE
1026 #define __HAVE_ARCH_PREPARE_TO_SWAP
1027 static inline int arch_prepare_to_swap(struct page *page)
1029 if (system_supports_mte())
1030 return mte_save_tags(page);
1034 #define __HAVE_ARCH_SWAP_INVALIDATE
1035 static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
1037 if (system_supports_mte())
1038 mte_invalidate_tags(type, offset);
1041 static inline void arch_swap_invalidate_area(int type)
1043 if (system_supports_mte())
1044 mte_invalidate_tags_area(type);
1047 #define __HAVE_ARCH_SWAP_RESTORE
1048 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio)
1050 if (system_supports_mte() && mte_restore_tags(entry, &folio->page))
1051 set_bit(PG_mte_tagged, &folio->flags);
1054 #endif /* CONFIG_ARM64_MTE */
1057 * On AArch64, the cache coherency is handled via the set_pte_at() function.
1059 static inline void update_mmu_cache(struct vm_area_struct *vma,
1060 unsigned long addr, pte_t *ptep)
1063 * We don't do anything here, so there's a very small chance of
1064 * us retaking a user fault which we just fixed up. The alternative
1065 * is doing a dsb(ishst), but that penalises the fastpath.
1069 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
1071 #ifdef CONFIG_ARM64_PA_BITS_52
1072 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
1074 #define phys_to_ttbr(addr) (addr)
1078 * On arm64 without hardware Access Flag, copying from user will fail because
1079 * the pte is old and cannot be marked young. So we always end up with zeroed
1080 * page after fork() + CoW for pfn mappings. We don't always have a
1081 * hardware-managed access flag on arm64.
1083 #define arch_has_hw_pte_young cpu_has_hw_af
1086 * Experimentally, it's cheap to set the access flag in hardware and we
1087 * benefit from prefaulting mappings as 'old' to start with.
1089 #define arch_wants_old_prefaulted_pte cpu_has_hw_af
1091 static inline bool pud_sect_supported(void)
1093 return PAGE_SIZE == SZ_4K;
1097 #endif /* !__ASSEMBLY__ */
1099 #endif /* __ASM_PGTABLE_H */