1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 ARM Ltd.
5 #ifndef __ASM_PGTABLE_H
6 #define __ASM_PGTABLE_H
9 #include <asm/proc-fns.h>
11 #include <asm/memory.h>
13 #include <asm/pgtable-hwdef.h>
14 #include <asm/pgtable-prot.h>
15 #include <asm/tlbflush.h>
20 * VMALLOC_START: beginning of the kernel vmalloc space
21 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space
24 #define VMALLOC_START (MODULES_END)
25 #define VMALLOC_END (- PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
27 #define FIRST_USER_ADDRESS 0UL
31 #include <asm/cmpxchg.h>
32 #include <asm/fixmap.h>
33 #include <linux/mmdebug.h>
34 #include <linux/mm_types.h>
35 #include <linux/sched.h>
37 extern struct page *vmemmap;
39 extern void __pte_error(const char *file, int line, unsigned long val);
40 extern void __pmd_error(const char *file, int line, unsigned long val);
41 extern void __pud_error(const char *file, int line, unsigned long val);
42 extern void __pgd_error(const char *file, int line, unsigned long val);
44 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
45 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
47 /* Set stride and tlb_level in flush_*_tlb_range */
48 #define flush_pmd_tlb_range(vma, addr, end) \
49 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
50 #define flush_pud_tlb_range(vma, addr, end) \
51 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
52 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
55 * ZERO_PAGE is a global shared page that is always zero: used
56 * for zero-mapped memory areas etc..
58 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
59 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page))
61 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
64 * Macros to convert between a physical address and its placement in a
65 * page table entry, taking care of 52-bit addresses.
67 #ifdef CONFIG_ARM64_PA_BITS_52
68 #define __pte_to_phys(pte) \
69 ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36))
70 #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK)
72 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
73 #define __phys_to_pte_val(phys) (phys)
76 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT)
77 #define pfn_pte(pfn,prot) \
78 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
80 #define pte_none(pte) (!pte_val(pte))
81 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
82 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
85 * The following only work if pte_present(). Undefined behaviour otherwise.
87 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
88 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
89 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
90 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
91 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
92 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
93 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP))
94 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \
95 PTE_ATTRINDX(MT_NORMAL_TAGGED))
97 #define pte_cont_addr_end(addr, end) \
98 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \
99 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
102 #define pmd_cont_addr_end(addr, end) \
103 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \
104 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
107 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
108 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
109 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
111 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
112 #define pte_valid_not_user(pte) \
113 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
114 #define pte_valid_young(pte) \
115 ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF))
116 #define pte_valid_user(pte) \
117 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
120 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
121 * so that we don't erroneously return false for pages that have been
122 * remapped as PROT_NONE but are yet to be flushed from the TLB.
124 #define pte_accessible(mm, pte) \
125 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte))
128 * p??_access_permitted() is true for valid user mappings (subject to the
129 * write permission check). PROT_NONE mappings do not have the PTE_VALID bit
132 #define pte_access_permitted(pte, write) \
133 (pte_valid_user(pte) && (!(write) || pte_write(pte)))
134 #define pmd_access_permitted(pmd, write) \
135 (pte_access_permitted(pmd_pte(pmd), (write)))
136 #define pud_access_permitted(pud, write) \
137 (pte_access_permitted(pud_pte(pud), (write)))
139 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
141 pte_val(pte) &= ~pgprot_val(prot);
145 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
147 pte_val(pte) |= pgprot_val(prot);
151 static inline pte_t pte_wrprotect(pte_t pte)
153 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
154 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
158 static inline pte_t pte_mkwrite(pte_t pte)
160 pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
161 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
165 static inline pte_t pte_mkclean(pte_t pte)
167 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
168 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
173 static inline pte_t pte_mkdirty(pte_t pte)
175 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
178 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
183 static inline pte_t pte_mkold(pte_t pte)
185 return clear_pte_bit(pte, __pgprot(PTE_AF));
188 static inline pte_t pte_mkyoung(pte_t pte)
190 return set_pte_bit(pte, __pgprot(PTE_AF));
193 static inline pte_t pte_mkspecial(pte_t pte)
195 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
198 static inline pte_t pte_mkcont(pte_t pte)
200 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
201 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
204 static inline pte_t pte_mknoncont(pte_t pte)
206 return clear_pte_bit(pte, __pgprot(PTE_CONT));
209 static inline pte_t pte_mkpresent(pte_t pte)
211 return set_pte_bit(pte, __pgprot(PTE_VALID));
214 static inline pmd_t pmd_mkcont(pmd_t pmd)
216 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
219 static inline pte_t pte_mkdevmap(pte_t pte)
221 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
224 static inline void set_pte(pte_t *ptep, pte_t pte)
226 WRITE_ONCE(*ptep, pte);
229 * Only if the new pte is valid and kernel, otherwise TLB maintenance
230 * or update_mmu_cache() have the necessary barriers.
232 if (pte_valid_not_user(pte)) {
238 extern void __sync_icache_dcache(pte_t pteval);
241 * PTE bits configuration in the presence of hardware Dirty Bit Management
242 * (PTE_WRITE == PTE_DBM):
244 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
250 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
251 * the page fault mechanism. Checking the dirty status of a pte becomes:
253 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
256 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep,
261 if (!IS_ENABLED(CONFIG_DEBUG_VM))
264 old_pte = READ_ONCE(*ptep);
266 if (!pte_valid(old_pte) || !pte_valid(pte))
268 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
272 * Check for potential race with hardware updates of the pte
273 * (ptep_set_access_flags safely changes valid ptes without going
274 * through an invalid entry).
276 VM_WARN_ONCE(!pte_young(pte),
277 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
278 __func__, pte_val(old_pte), pte_val(pte));
279 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
280 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
281 __func__, pte_val(old_pte), pte_val(pte));
284 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
285 pte_t *ptep, pte_t pte)
287 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
288 __sync_icache_dcache(pte);
290 if (system_supports_mte() &&
291 pte_present(pte) && pte_tagged(pte) && !pte_special(pte))
292 mte_sync_tags(ptep, pte);
294 __check_racy_pte_update(mm, ptep, pte);
300 * Huge pte definitions.
302 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
305 * Hugetlb definitions.
307 #define HUGE_MAX_HSTATE 4
308 #define HPAGE_SHIFT PMD_SHIFT
309 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
310 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
311 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
313 static inline pte_t pgd_pte(pgd_t pgd)
315 return __pte(pgd_val(pgd));
318 static inline pte_t p4d_pte(p4d_t p4d)
320 return __pte(p4d_val(p4d));
323 static inline pte_t pud_pte(pud_t pud)
325 return __pte(pud_val(pud));
328 static inline pud_t pte_pud(pte_t pte)
330 return __pud(pte_val(pte));
333 static inline pmd_t pud_pmd(pud_t pud)
335 return __pmd(pud_val(pud));
338 static inline pte_t pmd_pte(pmd_t pmd)
340 return __pte(pmd_val(pmd));
343 static inline pmd_t pte_pmd(pte_t pte)
345 return __pmd(pte_val(pte));
348 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
350 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT);
353 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
355 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT);
358 #ifdef CONFIG_NUMA_BALANCING
360 * See the comment in include/linux/pgtable.h
362 static inline int pte_protnone(pte_t pte)
364 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
367 static inline int pmd_protnone(pmd_t pmd)
369 return pte_protnone(pmd_pte(pmd));
377 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
378 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
379 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
381 #define pmd_present(pmd) pte_present(pmd_pte(pmd))
382 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
383 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
384 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
385 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
386 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
387 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
388 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
389 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
390 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
391 #define pmd_mkinvalid(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID))
393 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
395 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
397 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
399 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
400 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd))
402 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
404 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
407 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
408 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
409 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
410 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
411 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
413 #define pud_young(pud) pte_young(pud_pte(pud))
414 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
415 #define pud_write(pud) pte_write(pud_pte(pud))
417 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
419 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
420 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
421 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
422 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
424 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
426 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d))
427 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys)
429 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd))
430 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
432 #define __pgprot_modify(prot,mask,bits) \
433 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
435 #define pgprot_nx(prot) \
436 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN)
439 * Mark the prot value as uncacheable and unbufferable.
441 #define pgprot_noncached(prot) \
442 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
443 #define pgprot_writecombine(prot) \
444 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
445 #define pgprot_device(prot) \
446 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
448 * DMA allocations for non-coherent devices use what the Arm architecture calls
449 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
450 * and merging of writes. This is different from "Device-nGnR[nE]" memory which
451 * is intended for MMIO and thus forbids speculation, preserves access size,
452 * requires strict alignment and can also force write responses to come from the
455 #define pgprot_dmacoherent(prot) \
456 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
457 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
459 #define __HAVE_PHYS_MEM_ACCESS_PROT
461 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
462 unsigned long size, pgprot_t vma_prot);
464 #define pmd_none(pmd) (!pmd_val(pmd))
466 #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT))
468 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
470 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
472 #define pmd_leaf(pmd) pmd_sect(pmd)
474 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
475 static inline bool pud_sect(pud_t pud) { return false; }
476 static inline bool pud_table(pud_t pud) { return true; }
478 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
480 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
484 extern pgd_t init_pg_dir[PTRS_PER_PGD];
485 extern pgd_t init_pg_end[];
486 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
487 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
488 extern pgd_t idmap_pg_end[];
489 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
491 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
493 static inline bool in_swapper_pgdir(void *addr)
495 return ((unsigned long)addr & PAGE_MASK) ==
496 ((unsigned long)swapper_pg_dir & PAGE_MASK);
499 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
501 #ifdef __PAGETABLE_PMD_FOLDED
502 if (in_swapper_pgdir(pmdp)) {
503 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
506 #endif /* __PAGETABLE_PMD_FOLDED */
508 WRITE_ONCE(*pmdp, pmd);
510 if (pmd_valid(pmd)) {
516 static inline void pmd_clear(pmd_t *pmdp)
518 set_pmd(pmdp, __pmd(0));
521 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
523 return __pmd_to_phys(pmd);
526 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
528 return (unsigned long)__va(pmd_page_paddr(pmd));
531 /* Find an entry in the third-level page table. */
532 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
534 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
535 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
536 #define pte_clear_fixmap() clear_fixmap(FIX_PTE)
538 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd))
540 /* use ONLY for statically allocated translation tables */
541 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
544 * Conversion functions: convert a page and protection to a page entry,
545 * and a page entry and page directory to the page they refer to.
547 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
549 #if CONFIG_PGTABLE_LEVELS > 2
551 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
553 #define pud_none(pud) (!pud_val(pud))
554 #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT))
555 #define pud_present(pud) pte_present(pud_pte(pud))
556 #define pud_leaf(pud) pud_sect(pud)
557 #define pud_valid(pud) pte_valid(pud_pte(pud))
559 static inline void set_pud(pud_t *pudp, pud_t pud)
561 #ifdef __PAGETABLE_PUD_FOLDED
562 if (in_swapper_pgdir(pudp)) {
563 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
566 #endif /* __PAGETABLE_PUD_FOLDED */
568 WRITE_ONCE(*pudp, pud);
570 if (pud_valid(pud)) {
576 static inline void pud_clear(pud_t *pudp)
578 set_pud(pudp, __pud(0));
581 static inline phys_addr_t pud_page_paddr(pud_t pud)
583 return __pud_to_phys(pud);
586 static inline unsigned long pud_page_vaddr(pud_t pud)
588 return (unsigned long)__va(pud_page_paddr(pud));
591 /* Find an entry in the second-level page table. */
592 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
594 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
595 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
596 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
598 #define pud_page(pud) phys_to_page(__pud_to_phys(pud))
600 /* use ONLY for statically allocated translation tables */
601 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
605 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
607 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
608 #define pmd_set_fixmap(addr) NULL
609 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
610 #define pmd_clear_fixmap()
612 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
614 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
616 #if CONFIG_PGTABLE_LEVELS > 3
618 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
620 #define p4d_none(p4d) (!p4d_val(p4d))
621 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2))
622 #define p4d_present(p4d) (p4d_val(p4d))
624 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
626 if (in_swapper_pgdir(p4dp)) {
627 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d)));
631 WRITE_ONCE(*p4dp, p4d);
636 static inline void p4d_clear(p4d_t *p4dp)
638 set_p4d(p4dp, __p4d(0));
641 static inline phys_addr_t p4d_page_paddr(p4d_t p4d)
643 return __p4d_to_phys(p4d);
646 static inline unsigned long p4d_page_vaddr(p4d_t p4d)
648 return (unsigned long)__va(p4d_page_paddr(p4d));
651 /* Find an entry in the frst-level page table. */
652 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
654 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
655 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr))
656 #define pud_clear_fixmap() clear_fixmap(FIX_PUD)
658 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d)))
660 /* use ONLY for statically allocated translation tables */
661 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
665 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;})
666 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;})
668 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
669 #define pud_set_fixmap(addr) NULL
670 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
671 #define pud_clear_fixmap()
673 #define pud_offset_kimg(dir,addr) ((pud_t *)dir)
675 #endif /* CONFIG_PGTABLE_LEVELS > 3 */
677 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
679 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
680 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
682 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
685 * Normal and Normal-Tagged are two different memory types and indices
686 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK.
688 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
689 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP |
691 /* preserve the hardware dirty information */
692 if (pte_hw_dirty(pte))
693 pte = pte_mkdirty(pte);
694 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
698 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
700 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
703 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
704 extern int ptep_set_access_flags(struct vm_area_struct *vma,
705 unsigned long address, pte_t *ptep,
706 pte_t entry, int dirty);
708 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
709 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
710 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
711 unsigned long address, pmd_t *pmdp,
712 pmd_t entry, int dirty)
714 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
717 static inline int pud_devmap(pud_t pud)
722 static inline int pgd_devmap(pgd_t pgd)
729 * Atomic pte/pmd modifications.
731 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
732 static inline int __ptep_test_and_clear_young(pte_t *ptep)
736 pte = READ_ONCE(*ptep);
739 pte = pte_mkold(pte);
740 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
741 pte_val(old_pte), pte_val(pte));
742 } while (pte_val(pte) != pte_val(old_pte));
744 return pte_young(pte);
747 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
748 unsigned long address,
751 return __ptep_test_and_clear_young(ptep);
754 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
755 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
756 unsigned long address, pte_t *ptep)
758 int young = ptep_test_and_clear_young(vma, address, ptep);
762 * We can elide the trailing DSB here since the worst that can
763 * happen is that a CPU continues to use the young entry in its
764 * TLB and we mistakenly reclaim the associated page. The
765 * window for such an event is bounded by the next
766 * context-switch, which provides a DSB to complete the TLB
769 flush_tlb_page_nosync(vma, address);
775 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
776 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
777 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
778 unsigned long address,
781 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
783 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
785 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
786 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
787 unsigned long address, pte_t *ptep)
789 return __pte(xchg_relaxed(&pte_val(*ptep), 0));
792 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
793 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
794 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
795 unsigned long address, pmd_t *pmdp)
797 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
799 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
802 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
803 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
805 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
806 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
810 pte = READ_ONCE(*ptep);
814 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
815 * clear), set the PTE_DIRTY bit.
817 if (pte_hw_dirty(pte))
818 pte = pte_mkdirty(pte);
819 pte = pte_wrprotect(pte);
820 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
821 pte_val(old_pte), pte_val(pte));
822 } while (pte_val(pte) != pte_val(old_pte));
825 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
826 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
827 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
828 unsigned long address, pmd_t *pmdp)
830 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
833 #define pmdp_establish pmdp_establish
834 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
835 unsigned long address, pmd_t *pmdp, pmd_t pmd)
837 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
842 * Encode and decode a swap entry:
843 * bits 0-1: present (must be zero)
844 * bits 2-7: swap type
845 * bits 8-57: swap offset
846 * bit 58: PTE_PROT_NONE (must be zero)
848 #define __SWP_TYPE_SHIFT 2
849 #define __SWP_TYPE_BITS 6
850 #define __SWP_OFFSET_BITS 50
851 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
852 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
853 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
855 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
856 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
857 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
859 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
860 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
863 * Ensure that there are not more swap files than can be encoded in the kernel
866 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
868 extern int kern_addr_valid(unsigned long addr);
871 * On AArch64, the cache coherency is handled via the set_pte_at() function.
873 static inline void update_mmu_cache(struct vm_area_struct *vma,
874 unsigned long addr, pte_t *ptep)
877 * We don't do anything here, so there's a very small chance of
878 * us retaking a user fault which we just fixed up. The alternative
879 * is doing a dsb(ishst), but that penalises the fastpath.
883 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
885 #ifdef CONFIG_ARM64_PA_BITS_52
886 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
888 #define phys_to_ttbr(addr) (addr)
892 * On arm64 without hardware Access Flag, copying from user will fail because
893 * the pte is old and cannot be marked young. So we always end up with zeroed
894 * page after fork() + CoW for pfn mappings. We don't always have a
895 * hardware-managed access flag on arm64.
897 static inline bool arch_faults_on_old_pte(void)
899 WARN_ON(preemptible());
901 return !cpu_has_hw_af();
903 #define arch_faults_on_old_pte arch_faults_on_old_pte
905 #endif /* !__ASSEMBLY__ */
907 #endif /* __ASM_PGTABLE_H */