arch/arm64/include/asm/kvm_host.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2012,2013 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  *
   6  * Derived from arch/arm/include/asm/kvm_host.h:
   7  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   8  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
   9  */
  10
  11 #ifndef __ARM64_KVM_HOST_H__
  12 #define __ARM64_KVM_HOST_H__
  13
  14 #include <linux/arm-smccc.h>
  15 #include <linux/bitmap.h>
  16 #include <linux/types.h>
  17 #include <linux/jump_label.h>
  18 #include <linux/kvm_types.h>
  19 #include <linux/maple_tree.h>
  20 #include <linux/percpu.h>
  21 #include <linux/psci.h>
  22 #include <asm/arch_gicv3.h>
  23 #include <asm/barrier.h>
  24 #include <asm/cpufeature.h>
  25 #include <asm/cputype.h>
  26 #include <asm/daifflags.h>
  27 #include <asm/fpsimd.h>
  28 #include <asm/kvm.h>
  29 #include <asm/kvm_asm.h>
  30
  31 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
  32
  33 #define KVM_HALT_POLL_NS_DEFAULT 500000
  34
  35 #include <kvm/arm_vgic.h>
  36 #include <kvm/arm_arch_timer.h>
  37 #include <kvm/arm_pmu.h>
  38
  39 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
  40
  41 #define KVM_VCPU_MAX_FEATURES 7
  42
  43 #define KVM_REQ_SLEEP \
  44         KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
  45 #define KVM_REQ_IRQ_PENDING     KVM_ARCH_REQ(1)
  46 #define KVM_REQ_VCPU_RESET      KVM_ARCH_REQ(2)
  47 #define KVM_REQ_RECORD_STEAL    KVM_ARCH_REQ(3)
  48 #define KVM_REQ_RELOAD_GICv4    KVM_ARCH_REQ(4)
  49 #define KVM_REQ_RELOAD_PMU      KVM_ARCH_REQ(5)
  50 #define KVM_REQ_SUSPEND         KVM_ARCH_REQ(6)
  51
  52 #define KVM_DIRTY_LOG_MANUAL_CAPS   (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
  53                                      KVM_DIRTY_LOG_INITIALLY_SET)
  54
  55 #define KVM_HAVE_MMU_RWLOCK
  56
  57 /*
  58  * Mode of operation configurable with kvm-arm.mode early param.
  59  * See Documentation/admin-guide/kernel-parameters.txt for more information.
  60  */
  61 enum kvm_mode {
  62         KVM_MODE_DEFAULT,
  63         KVM_MODE_PROTECTED,
  64         KVM_MODE_NV,
  65         KVM_MODE_NONE,
  66 };
  67 #ifdef CONFIG_KVM
  68 enum kvm_mode kvm_get_mode(void);
  69 #else
  70 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; };
  71 #endif
  72
  73 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
  74
  75 extern unsigned int __ro_after_init kvm_sve_max_vl;
  76 int __init kvm_arm_init_sve(void);
  77
  78 u32 __attribute_const__ kvm_target_cpu(void);
  79 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
  80 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
  81
  82 struct kvm_hyp_memcache {
  83         phys_addr_t head;
  84         unsigned long nr_pages;
  85 };
  86
  87 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc,
  88                                      phys_addr_t *p,
  89                                      phys_addr_t (*to_pa)(void *virt))
  90 {
  91         *p = mc->head;
  92         mc->head = to_pa(p);
  93         mc->nr_pages++;
  94 }
  95
  96 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc,
  97                                      void *(*to_va)(phys_addr_t phys))
  98 {
  99         phys_addr_t *p = to_va(mc->head);
 100
 101         if (!mc->nr_pages)
 102                 return NULL;
 103
 104         mc->head = *p;
 105         mc->nr_pages--;
 106
 107         return p;
 108 }
 109
 110 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc,
 111                                        unsigned long min_pages,
 112                                        void *(*alloc_fn)(void *arg),
 113                                        phys_addr_t (*to_pa)(void *virt),
 114                                        void *arg)
 115 {
 116         while (mc->nr_pages < min_pages) {
 117                 phys_addr_t *p = alloc_fn(arg);
 118
 119                 if (!p)
 120                         return -ENOMEM;
 121                 push_hyp_memcache(mc, p, to_pa);
 122         }
 123
 124         return 0;
 125 }
 126
 127 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc,
 128                                        void (*free_fn)(void *virt, void *arg),
 129                                        void *(*to_va)(phys_addr_t phys),
 130                                        void *arg)
 131 {
 132         while (mc->nr_pages)
 133                 free_fn(pop_hyp_memcache(mc, to_va), arg);
 134 }
 135
 136 void free_hyp_memcache(struct kvm_hyp_memcache *mc);
 137 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages);
 138
 139 struct kvm_vmid {
 140         atomic64_t id;
 141 };
 142
 143 struct kvm_s2_mmu {
 144         struct kvm_vmid vmid;
 145
 146         /*
 147          * stage2 entry level table
 148          *
 149          * Two kvm_s2_mmu structures in the same VM can point to the same
 150          * pgd here.  This happens when running a guest using a
 151          * translation regime that isn't affected by its own stage-2
 152          * translation, such as a non-VHE hypervisor running at vEL2, or
 153          * for vEL1/EL0 with vHCR_EL2.VM == 0.  In that case, we use the
 154          * canonical stage-2 page tables.
 155          */
 156         phys_addr_t     pgd_phys;
 157         struct kvm_pgtable *pgt;
 158
 159         /* The last vcpu id that ran on each physical CPU */
 160         int __percpu *last_vcpu_ran;
 161
 162         struct kvm_arch *arch;
 163 };
 164
 165 struct kvm_arch_memory_slot {
 166 };
 167
 168 /**
 169  * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests
 170  *
 171  * @std_bmap: Bitmap of standard secure service calls
 172  * @std_hyp_bmap: Bitmap of standard hypervisor service calls
 173  * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls
 174  */
 175 struct kvm_smccc_features {
 176         unsigned long std_bmap;
 177         unsigned long std_hyp_bmap;
 178         unsigned long vendor_hyp_bmap;
 179 };
 180
 181 typedef unsigned int pkvm_handle_t;
 182
 183 struct kvm_protected_vm {
 184         pkvm_handle_t handle;
 185         struct kvm_hyp_memcache teardown_mc;
 186 };
 187
 188 struct kvm_arch {
 189         struct kvm_s2_mmu mmu;
 190
 191         /* VTCR_EL2 value for this VM */
 192         u64    vtcr;
 193
 194         /* Interrupt controller */
 195         struct vgic_dist        vgic;
 196
 197         /* Timers */
 198         struct arch_timer_vm_data timer_data;
 199
 200         /* Mandated version of PSCI */
 201         u32 psci_version;
 202
 203         /* Protects VM-scoped configuration data */
 204         struct mutex config_lock;
 205
 206         /*
 207          * If we encounter a data abort without valid instruction syndrome
 208          * information, report this to user space.  User space can (and
 209          * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
 210          * supported.
 211          */
 212 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER      0
 213         /* Memory Tagging Extension enabled for the guest */
 214 #define KVM_ARCH_FLAG_MTE_ENABLED                       1
 215         /* At least one vCPU has ran in the VM */
 216 #define KVM_ARCH_FLAG_HAS_RAN_ONCE                      2
 217         /*
 218          * The following two bits are used to indicate the guest's EL1
 219          * register width configuration. A value of KVM_ARCH_FLAG_EL1_32BIT
 220          * bit is valid only when KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED is set.
 221          * Otherwise, the guest's EL1 register width has not yet been
 222          * determined yet.
 223          */
 224 #define KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED              3
 225 #define KVM_ARCH_FLAG_EL1_32BIT                         4
 226         /* PSCI SYSTEM_SUSPEND enabled for the guest */
 227 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED            5
 228         /* VM counter offset */
 229 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET                 6
 230         /* Timer PPIs made immutable */
 231 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE              7
 232         /* SMCCC filter initialized for the VM */
 233 #define KVM_ARCH_FLAG_SMCCC_FILTER_CONFIGURED           8
 234         unsigned long flags;
 235
 236         /*
 237          * VM-wide PMU filter, implemented as a bitmap and big enough for
 238          * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
 239          */
 240         unsigned long *pmu_filter;
 241         struct arm_pmu *arm_pmu;
 242
 243         cpumask_var_t supported_cpus;
 244
 245         u8 pfr0_csv2;
 246         u8 pfr0_csv3;
 247         struct {
 248                 u8 imp:4;
 249                 u8 unimp:4;
 250         } dfr0_pmuver;
 251
 252         /* Hypercall features firmware registers' descriptor */
 253         struct kvm_smccc_features smccc_feat;
 254         struct maple_tree smccc_filter;
 255
 256         /*
 257          * For an untrusted host VM, 'pkvm.handle' is used to lookup
 258          * the associated pKVM instance in the hypervisor.
 259          */
 260         struct kvm_protected_vm pkvm;
 261 };
 262
 263 struct kvm_vcpu_fault_info {
 264         u64 esr_el2;            /* Hyp Syndrom Register */
 265         u64 far_el2;            /* Hyp Fault Address Register */
 266         u64 hpfar_el2;          /* Hyp IPA Fault Address Register */
 267         u64 disr_el1;           /* Deferred [SError] Status Register */
 268 };
 269
 270 enum vcpu_sysreg {
 271         __INVALID_SYSREG__,   /* 0 is reserved as an invalid value */
 272         MPIDR_EL1,      /* MultiProcessor Affinity Register */
 273         CLIDR_EL1,      /* Cache Level ID Register */
 274         CSSELR_EL1,     /* Cache Size Selection Register */
 275         SCTLR_EL1,      /* System Control Register */
 276         ACTLR_EL1,      /* Auxiliary Control Register */
 277         CPACR_EL1,      /* Coprocessor Access Control */
 278         ZCR_EL1,        /* SVE Control */
 279         TTBR0_EL1,      /* Translation Table Base Register 0 */
 280         TTBR1_EL1,      /* Translation Table Base Register 1 */
 281         TCR_EL1,        /* Translation Control Register */
 282         ESR_EL1,        /* Exception Syndrome Register */
 283         AFSR0_EL1,      /* Auxiliary Fault Status Register 0 */
 284         AFSR1_EL1,      /* Auxiliary Fault Status Register 1 */
 285         FAR_EL1,        /* Fault Address Register */
 286         MAIR_EL1,       /* Memory Attribute Indirection Register */
 287         VBAR_EL1,       /* Vector Base Address Register */
 288         CONTEXTIDR_EL1, /* Context ID Register */
 289         TPIDR_EL0,      /* Thread ID, User R/W */
 290         TPIDRRO_EL0,    /* Thread ID, User R/O */
 291         TPIDR_EL1,      /* Thread ID, Privileged */
 292         AMAIR_EL1,      /* Aux Memory Attribute Indirection Register */
 293         CNTKCTL_EL1,    /* Timer Control Register (EL1) */
 294         PAR_EL1,        /* Physical Address Register */
 295         MDSCR_EL1,      /* Monitor Debug System Control Register */
 296         MDCCINT_EL1,    /* Monitor Debug Comms Channel Interrupt Enable Reg */
 297         OSLSR_EL1,      /* OS Lock Status Register */
 298         DISR_EL1,       /* Deferred Interrupt Status Register */
 299
 300         /* Performance Monitors Registers */
 301         PMCR_EL0,       /* Control Register */
 302         PMSELR_EL0,     /* Event Counter Selection Register */
 303         PMEVCNTR0_EL0,  /* Event Counter Register (0-30) */
 304         PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
 305         PMCCNTR_EL0,    /* Cycle Counter Register */
 306         PMEVTYPER0_EL0, /* Event Type Register (0-30) */
 307         PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
 308         PMCCFILTR_EL0,  /* Cycle Count Filter Register */
 309         PMCNTENSET_EL0, /* Count Enable Set Register */
 310         PMINTENSET_EL1, /* Interrupt Enable Set Register */
 311         PMOVSSET_EL0,   /* Overflow Flag Status Set Register */
 312         PMUSERENR_EL0,  /* User Enable Register */
 313
 314         /* Pointer Authentication Registers in a strict increasing order. */
 315         APIAKEYLO_EL1,
 316         APIAKEYHI_EL1,
 317         APIBKEYLO_EL1,
 318         APIBKEYHI_EL1,
 319         APDAKEYLO_EL1,
 320         APDAKEYHI_EL1,
 321         APDBKEYLO_EL1,
 322         APDBKEYHI_EL1,
 323         APGAKEYLO_EL1,
 324         APGAKEYHI_EL1,
 325
 326         ELR_EL1,
 327         SP_EL1,
 328         SPSR_EL1,
 329
 330         CNTVOFF_EL2,
 331         CNTV_CVAL_EL0,
 332         CNTV_CTL_EL0,
 333         CNTP_CVAL_EL0,
 334         CNTP_CTL_EL0,
 335
 336         /* Memory Tagging Extension registers */
 337         RGSR_EL1,       /* Random Allocation Tag Seed Register */
 338         GCR_EL1,        /* Tag Control Register */
 339         TFSR_EL1,       /* Tag Fault Status Register (EL1) */
 340         TFSRE0_EL1,     /* Tag Fault Status Register (EL0) */
 341
 342         /* 32bit specific registers. */
 343         DACR32_EL2,     /* Domain Access Control Register */
 344         IFSR32_EL2,     /* Instruction Fault Status Register */
 345         FPEXC32_EL2,    /* Floating-Point Exception Control Register */
 346         DBGVCR32_EL2,   /* Debug Vector Catch Register */
 347
 348         /* EL2 registers */
 349         VPIDR_EL2,      /* Virtualization Processor ID Register */
 350         VMPIDR_EL2,     /* Virtualization Multiprocessor ID Register */
 351         SCTLR_EL2,      /* System Control Register (EL2) */
 352         ACTLR_EL2,      /* Auxiliary Control Register (EL2) */
 353         HCR_EL2,        /* Hypervisor Configuration Register */
 354         MDCR_EL2,       /* Monitor Debug Configuration Register (EL2) */
 355         CPTR_EL2,       /* Architectural Feature Trap Register (EL2) */
 356         HSTR_EL2,       /* Hypervisor System Trap Register */
 357         HACR_EL2,       /* Hypervisor Auxiliary Control Register */
 358         TTBR0_EL2,      /* Translation Table Base Register 0 (EL2) */
 359         TTBR1_EL2,      /* Translation Table Base Register 1 (EL2) */
 360         TCR_EL2,        /* Translation Control Register (EL2) */
 361         VTTBR_EL2,      /* Virtualization Translation Table Base Register */
 362         VTCR_EL2,       /* Virtualization Translation Control Register */
 363         SPSR_EL2,       /* EL2 saved program status register */
 364         ELR_EL2,        /* EL2 exception link register */
 365         AFSR0_EL2,      /* Auxiliary Fault Status Register 0 (EL2) */
 366         AFSR1_EL2,      /* Auxiliary Fault Status Register 1 (EL2) */
 367         ESR_EL2,        /* Exception Syndrome Register (EL2) */
 368         FAR_EL2,        /* Fault Address Register (EL2) */
 369         HPFAR_EL2,      /* Hypervisor IPA Fault Address Register */
 370         MAIR_EL2,       /* Memory Attribute Indirection Register (EL2) */
 371         AMAIR_EL2,      /* Auxiliary Memory Attribute Indirection Register (EL2) */
 372         VBAR_EL2,       /* Vector Base Address Register (EL2) */
 373         RVBAR_EL2,      /* Reset Vector Base Address Register */
 374         CONTEXTIDR_EL2, /* Context ID Register (EL2) */
 375         TPIDR_EL2,      /* EL2 Software Thread ID Register */
 376         CNTHCTL_EL2,    /* Counter-timer Hypervisor Control register */
 377         SP_EL2,         /* EL2 Stack Pointer */
 378         CNTHP_CTL_EL2,
 379         CNTHP_CVAL_EL2,
 380         CNTHV_CTL_EL2,
 381         CNTHV_CVAL_EL2,
 382
 383         NR_SYS_REGS     /* Nothing after this line! */
 384 };
 385
 386 struct kvm_cpu_context {
 387         struct user_pt_regs regs;       /* sp = sp_el0 */
 388
 389         u64     spsr_abt;
 390         u64     spsr_und;
 391         u64     spsr_irq;
 392         u64     spsr_fiq;
 393
 394         struct user_fpsimd_state fp_regs;
 395
 396         u64 sys_regs[NR_SYS_REGS];
 397
 398         struct kvm_vcpu *__hyp_running_vcpu;
 399 };
 400
 401 struct kvm_host_data {
 402         struct kvm_cpu_context host_ctxt;
 403 };
 404
 405 struct kvm_host_psci_config {
 406         /* PSCI version used by host. */
 407         u32 version;
 408
 409         /* Function IDs used by host if version is v0.1. */
 410         struct psci_0_1_function_ids function_ids_0_1;
 411
 412         bool psci_0_1_cpu_suspend_implemented;
 413         bool psci_0_1_cpu_on_implemented;
 414         bool psci_0_1_cpu_off_implemented;
 415         bool psci_0_1_migrate_implemented;
 416 };
 417
 418 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
 419 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
 420
 421 extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
 422 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
 423
 424 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
 425 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
 426
 427 struct vcpu_reset_state {
 428         unsigned long   pc;
 429         unsigned long   r0;
 430         bool            be;
 431         bool            reset;
 432 };
 433
 434 struct kvm_vcpu_arch {
 435         struct kvm_cpu_context ctxt;
 436
 437         /*
 438          * Guest floating point state
 439          *
 440          * The architecture has two main floating point extensions,
 441          * the original FPSIMD and SVE.  These have overlapping
 442          * register views, with the FPSIMD V registers occupying the
 443          * low 128 bits of the SVE Z registers.  When the core
 444          * floating point code saves the register state of a task it
 445          * records which view it saved in fp_type.
 446          */
 447         void *sve_state;
 448         enum fp_type fp_type;
 449         unsigned int sve_max_vl;
 450         u64 svcr;
 451
 452         /* Stage 2 paging state used by the hardware on next switch */
 453         struct kvm_s2_mmu *hw_mmu;
 454
 455         /* Values of trap registers for the guest. */
 456         u64 hcr_el2;
 457         u64 mdcr_el2;
 458         u64 cptr_el2;
 459
 460         /* Values of trap registers for the host before guest entry. */
 461         u64 mdcr_el2_host;
 462
 463         /* Exception Information */
 464         struct kvm_vcpu_fault_info fault;
 465
 466         /* Ownership of the FP regs */
 467         enum {
 468                 FP_STATE_FREE,
 469                 FP_STATE_HOST_OWNED,
 470                 FP_STATE_GUEST_OWNED,
 471         } fp_state;
 472
 473         /* Configuration flags, set once and for all before the vcpu can run */
 474         u8 cflags;
 475
 476         /* Input flags to the hypervisor code, potentially cleared after use */
 477         u8 iflags;
 478
 479         /* State flags for kernel bookkeeping, unused by the hypervisor code */
 480         u8 sflags;
 481
 482         /*
 483          * Don't run the guest (internal implementation need).
 484          *
 485          * Contrary to the flags above, this is set/cleared outside of
 486          * a vcpu context, and thus cannot be mixed with the flags
 487          * themselves (or the flag accesses need to be made atomic).
 488          */
 489         bool pause;
 490
 491         /*
 492          * We maintain more than a single set of debug registers to support
 493          * debugging the guest from the host and to maintain separate host and
 494          * guest state during world switches. vcpu_debug_state are the debug
 495          * registers of the vcpu as the guest sees them.  host_debug_state are
 496          * the host registers which are saved and restored during
 497          * world switches. external_debug_state contains the debug
 498          * values we want to debug the guest. This is set via the
 499          * KVM_SET_GUEST_DEBUG ioctl.
 500          *
 501          * debug_ptr points to the set of debug registers that should be loaded
 502          * onto the hardware when running the guest.
 503          */
 504         struct kvm_guest_debug_arch *debug_ptr;
 505         struct kvm_guest_debug_arch vcpu_debug_state;
 506         struct kvm_guest_debug_arch external_debug_state;
 507
 508         struct user_fpsimd_state *host_fpsimd_state;    /* hyp VA */
 509         struct task_struct *parent_task;
 510
 511         struct {
 512                 /* {Break,watch}point registers */
 513                 struct kvm_guest_debug_arch regs;
 514                 /* Statistical profiling extension */
 515                 u64 pmscr_el1;
 516                 /* Self-hosted trace */
 517                 u64 trfcr_el1;
 518         } host_debug_state;
 519
 520         /* VGIC state */
 521         struct vgic_cpu vgic_cpu;
 522         struct arch_timer_cpu timer_cpu;
 523         struct kvm_pmu pmu;
 524
 525         /*
 526          * Guest registers we preserve during guest debugging.
 527          *
 528          * These shadow registers are updated by the kvm_handle_sys_reg
 529          * trap handler if the guest accesses or updates them while we
 530          * are using guest debug.
 531          */
 532         struct {
 533                 u32     mdscr_el1;
 534                 bool    pstate_ss;
 535         } guest_debug_preserved;
 536
 537         /* vcpu power state */
 538         struct kvm_mp_state mp_state;
 539         spinlock_t mp_state_lock;
 540
 541         /* Cache some mmu pages needed inside spinlock regions */
 542         struct kvm_mmu_memory_cache mmu_page_cache;
 543
 544         /* Target CPU and feature flags */
 545         int target;
 546         DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
 547
 548         /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
 549         u64 vsesr_el2;
 550
 551         /* Additional reset state */
 552         struct vcpu_reset_state reset_state;
 553
 554         /* Guest PV state */
 555         struct {
 556                 u64 last_steal;
 557                 gpa_t base;
 558         } steal;
 559
 560         /* Per-vcpu CCSIDR override or NULL */
 561         u32 *ccsidr;
 562 };
 563
 564 /*
 565  * Each 'flag' is composed of a comma-separated triplet:
 566  *
 567  * - the flag-set it belongs to in the vcpu->arch structure
 568  * - the value for that flag
 569  * - the mask for that flag
 570  *
 571  *  __vcpu_single_flag() builds such a triplet for a single-bit flag.
 572  * unpack_vcpu_flag() extract the flag value from the triplet for
 573  * direct use outside of the flag accessors.
 574  */
 575 #define __vcpu_single_flag(_set, _f)    _set, (_f), (_f)
 576
 577 #define __unpack_flag(_set, _f, _m)     _f
 578 #define unpack_vcpu_flag(...)           __unpack_flag(__VA_ARGS__)
 579
 580 #define __build_check_flag(v, flagset, f, m)                    \
 581         do {                                                    \
 582                 typeof(v->arch.flagset) *_fset;                 \
 583                                                                 \
 584                 /* Check that the flags fit in the mask */      \
 585                 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \
 586                 /* Check that the flags fit in the type */      \
 587                 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \
 588         } while (0)
 589
 590 #define __vcpu_get_flag(v, flagset, f, m)                       \
 591         ({                                                      \
 592                 __build_check_flag(v, flagset, f, m);           \
 593                                                                 \
 594                 v->arch.flagset & (m);                          \
 595         })
 596
 597 #define __vcpu_set_flag(v, flagset, f, m)                       \
 598         do {                                                    \
 599                 typeof(v->arch.flagset) *fset;                  \
 600                                                                 \
 601                 __build_check_flag(v, flagset, f, m);           \
 602                                                                 \
 603                 fset = &v->arch.flagset;                        \
 604                 if (HWEIGHT(m) > 1)                             \
 605                         *fset &= ~(m);                          \
 606                 *fset |= (f);                                   \
 607         } while (0)
 608
 609 #define __vcpu_clear_flag(v, flagset, f, m)                     \
 610         do {                                                    \
 611                 typeof(v->arch.flagset) *fset;                  \
 612                                                                 \
 613                 __build_check_flag(v, flagset, f, m);           \
 614                                                                 \
 615                 fset = &v->arch.flagset;                        \
 616                 *fset &= ~(m);                                  \
 617         } while (0)
 618
 619 #define vcpu_get_flag(v, ...)   __vcpu_get_flag((v), __VA_ARGS__)
 620 #define vcpu_set_flag(v, ...)   __vcpu_set_flag((v), __VA_ARGS__)
 621 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__)
 622
 623 /* SVE exposed to guest */
 624 #define GUEST_HAS_SVE           __vcpu_single_flag(cflags, BIT(0))
 625 /* SVE config completed */
 626 #define VCPU_SVE_FINALIZED      __vcpu_single_flag(cflags, BIT(1))
 627 /* PTRAUTH exposed to guest */
 628 #define GUEST_HAS_PTRAUTH       __vcpu_single_flag(cflags, BIT(2))
 629
 630 /* Exception pending */
 631 #define PENDING_EXCEPTION       __vcpu_single_flag(iflags, BIT(0))
 632 /*
 633  * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't
 634  * be set together with an exception...
 635  */
 636 #define INCREMENT_PC            __vcpu_single_flag(iflags, BIT(1))
 637 /* Target EL/MODE (not a single flag, but let's abuse the macro) */
 638 #define EXCEPT_MASK             __vcpu_single_flag(iflags, GENMASK(3, 1))
 639
 640 /* Helpers to encode exceptions with minimum fuss */
 641 #define __EXCEPT_MASK_VAL       unpack_vcpu_flag(EXCEPT_MASK)
 642 #define __EXCEPT_SHIFT          __builtin_ctzl(__EXCEPT_MASK_VAL)
 643 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL
 644
 645 /*
 646  * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following
 647  * values:
 648  *
 649  * For AArch32 EL1:
 650  */
 651 #define EXCEPT_AA32_UND         __vcpu_except_flags(0)
 652 #define EXCEPT_AA32_IABT        __vcpu_except_flags(1)
 653 #define EXCEPT_AA32_DABT        __vcpu_except_flags(2)
 654 /* For AArch64: */
 655 #define EXCEPT_AA64_EL1_SYNC    __vcpu_except_flags(0)
 656 #define EXCEPT_AA64_EL1_IRQ     __vcpu_except_flags(1)
 657 #define EXCEPT_AA64_EL1_FIQ     __vcpu_except_flags(2)
 658 #define EXCEPT_AA64_EL1_SERR    __vcpu_except_flags(3)
 659 /* For AArch64 with NV: */
 660 #define EXCEPT_AA64_EL2_SYNC    __vcpu_except_flags(4)
 661 #define EXCEPT_AA64_EL2_IRQ     __vcpu_except_flags(5)
 662 #define EXCEPT_AA64_EL2_FIQ     __vcpu_except_flags(6)
 663 #define EXCEPT_AA64_EL2_SERR    __vcpu_except_flags(7)
 664 /* Guest debug is live */
 665 #define DEBUG_DIRTY             __vcpu_single_flag(iflags, BIT(4))
 666 /* Save SPE context if active  */
 667 #define DEBUG_STATE_SAVE_SPE    __vcpu_single_flag(iflags, BIT(5))
 668 /* Save TRBE context if active  */
 669 #define DEBUG_STATE_SAVE_TRBE   __vcpu_single_flag(iflags, BIT(6))
 670 /* vcpu running in HYP context */
 671 #define VCPU_HYP_CONTEXT        __vcpu_single_flag(iflags, BIT(7))
 672
 673 /* SVE enabled for host EL0 */
 674 #define HOST_SVE_ENABLED        __vcpu_single_flag(sflags, BIT(0))
 675 /* SME enabled for EL0 */
 676 #define HOST_SME_ENABLED        __vcpu_single_flag(sflags, BIT(1))
 677 /* Physical CPU not in supported_cpus */
 678 #define ON_UNSUPPORTED_CPU      __vcpu_single_flag(sflags, BIT(2))
 679 /* WFIT instruction trapped */
 680 #define IN_WFIT                 __vcpu_single_flag(sflags, BIT(3))
 681 /* vcpu system registers loaded on physical CPU */
 682 #define SYSREGS_ON_CPU          __vcpu_single_flag(sflags, BIT(4))
 683 /* Software step state is Active-pending */
 684 #define DBG_SS_ACTIVE_PENDING   __vcpu_single_flag(sflags, BIT(5))
 685
 686
 687 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
 688 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) +      \
 689                              sve_ffr_offset((vcpu)->arch.sve_max_vl))
 690
 691 #define vcpu_sve_max_vq(vcpu)   sve_vq_from_vl((vcpu)->arch.sve_max_vl)
 692
 693 #define vcpu_sve_state_size(vcpu) ({                                    \
 694         size_t __size_ret;                                              \
 695         unsigned int __vcpu_vq;                                         \
 696                                                                         \
 697         if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) {          \
 698                 __size_ret = 0;                                         \
 699         } else {                                                        \
 700                 __vcpu_vq = vcpu_sve_max_vq(vcpu);                      \
 701                 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq);              \
 702         }                                                               \
 703                                                                         \
 704         __size_ret;                                                     \
 705 })
 706
 707 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
 708                                  KVM_GUESTDBG_USE_SW_BP | \
 709                                  KVM_GUESTDBG_USE_HW | \
 710                                  KVM_GUESTDBG_SINGLESTEP)
 711
 712 #define vcpu_has_sve(vcpu) (system_supports_sve() &&                    \
 713                             vcpu_get_flag(vcpu, GUEST_HAS_SVE))
 714
 715 #ifdef CONFIG_ARM64_PTR_AUTH
 716 #define vcpu_has_ptrauth(vcpu)                                          \
 717         ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) ||                \
 718           cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) &&               \
 719           vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH))
 720 #else
 721 #define vcpu_has_ptrauth(vcpu)          false
 722 #endif
 723
 724 #define vcpu_on_unsupported_cpu(vcpu)                                   \
 725         vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU)
 726
 727 #define vcpu_set_on_unsupported_cpu(vcpu)                               \
 728         vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU)
 729
 730 #define vcpu_clear_on_unsupported_cpu(vcpu)                             \
 731         vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU)
 732
 733 #define vcpu_gp_regs(v)         (&(v)->arch.ctxt.regs)
 734
 735 /*
 736  * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
 737  * memory backed version of a register, and not the one most recently
 738  * accessed by a running VCPU.  For example, for userspace access or
 739  * for system registers that are never context switched, but only
 740  * emulated.
 741  */
 742 #define __ctxt_sys_reg(c,r)     (&(c)->sys_regs[(r)])
 743
 744 #define ctxt_sys_reg(c,r)       (*__ctxt_sys_reg(c,r))
 745
 746 #define __vcpu_sys_reg(v,r)     (ctxt_sys_reg(&(v)->arch.ctxt, (r)))
 747
 748 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
 749 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
 750
 751 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
 752 {
 753         /*
 754          * *** VHE ONLY ***
 755          *
 756          * System registers listed in the switch are not saved on every
 757          * exit from the guest but are only saved on vcpu_put.
 758          *
 759          * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
 760          * should never be listed below, because the guest cannot modify its
 761          * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
 762          * thread when emulating cross-VCPU communication.
 763          */
 764         if (!has_vhe())
 765                 return false;
 766
 767         switch (reg) {
 768         case SCTLR_EL1:         *val = read_sysreg_s(SYS_SCTLR_EL12);   break;
 769         case CPACR_EL1:         *val = read_sysreg_s(SYS_CPACR_EL12);   break;
 770         case TTBR0_EL1:         *val = read_sysreg_s(SYS_TTBR0_EL12);   break;
 771         case TTBR1_EL1:         *val = read_sysreg_s(SYS_TTBR1_EL12);   break;
 772         case TCR_EL1:           *val = read_sysreg_s(SYS_TCR_EL12);     break;
 773         case ESR_EL1:           *val = read_sysreg_s(SYS_ESR_EL12);     break;
 774         case AFSR0_EL1:         *val = read_sysreg_s(SYS_AFSR0_EL12);   break;
 775         case AFSR1_EL1:         *val = read_sysreg_s(SYS_AFSR1_EL12);   break;
 776         case FAR_EL1:           *val = read_sysreg_s(SYS_FAR_EL12);     break;
 777         case MAIR_EL1:          *val = read_sysreg_s(SYS_MAIR_EL12);    break;
 778         case VBAR_EL1:          *val = read_sysreg_s(SYS_VBAR_EL12);    break;
 779         case CONTEXTIDR_EL1:    *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
 780         case TPIDR_EL0:         *val = read_sysreg_s(SYS_TPIDR_EL0);    break;
 781         case TPIDRRO_EL0:       *val = read_sysreg_s(SYS_TPIDRRO_EL0);  break;
 782         case TPIDR_EL1:         *val = read_sysreg_s(SYS_TPIDR_EL1);    break;
 783         case AMAIR_EL1:         *val = read_sysreg_s(SYS_AMAIR_EL12);   break;
 784         case CNTKCTL_EL1:       *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
 785         case ELR_EL1:           *val = read_sysreg_s(SYS_ELR_EL12);     break;
 786         case PAR_EL1:           *val = read_sysreg_par();               break;
 787         case DACR32_EL2:        *val = read_sysreg_s(SYS_DACR32_EL2);   break;
 788         case IFSR32_EL2:        *val = read_sysreg_s(SYS_IFSR32_EL2);   break;
 789         case DBGVCR32_EL2:      *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
 790         default:                return false;
 791         }
 792
 793         return true;
 794 }
 795
 796 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
 797 {
 798         /*
 799          * *** VHE ONLY ***
 800          *
 801          * System registers listed in the switch are not restored on every
 802          * entry to the guest but are only restored on vcpu_load.
 803          *
 804          * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
 805          * should never be listed below, because the MPIDR should only be set
 806          * once, before running the VCPU, and never changed later.
 807          */
 808         if (!has_vhe())
 809                 return false;
 810
 811         switch (reg) {
 812         case SCTLR_EL1:         write_sysreg_s(val, SYS_SCTLR_EL12);    break;
 813         case CPACR_EL1:         write_sysreg_s(val, SYS_CPACR_EL12);    break;
 814         case TTBR0_EL1:         write_sysreg_s(val, SYS_TTBR0_EL12);    break;
 815         case TTBR1_EL1:         write_sysreg_s(val, SYS_TTBR1_EL12);    break;
 816         case TCR_EL1:           write_sysreg_s(val, SYS_TCR_EL12);      break;
 817         case ESR_EL1:           write_sysreg_s(val, SYS_ESR_EL12);      break;
 818         case AFSR0_EL1:         write_sysreg_s(val, SYS_AFSR0_EL12);    break;
 819         case AFSR1_EL1:         write_sysreg_s(val, SYS_AFSR1_EL12);    break;
 820         case FAR_EL1:           write_sysreg_s(val, SYS_FAR_EL12);      break;
 821         case MAIR_EL1:          write_sysreg_s(val, SYS_MAIR_EL12);     break;
 822         case VBAR_EL1:          write_sysreg_s(val, SYS_VBAR_EL12);     break;
 823         case CONTEXTIDR_EL1:    write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
 824         case TPIDR_EL0:         write_sysreg_s(val, SYS_TPIDR_EL0);     break;
 825         case TPIDRRO_EL0:       write_sysreg_s(val, SYS_TPIDRRO_EL0);   break;
 826         case TPIDR_EL1:         write_sysreg_s(val, SYS_TPIDR_EL1);     break;
 827         case AMAIR_EL1:         write_sysreg_s(val, SYS_AMAIR_EL12);    break;
 828         case CNTKCTL_EL1:       write_sysreg_s(val, SYS_CNTKCTL_EL12);  break;
 829         case ELR_EL1:           write_sysreg_s(val, SYS_ELR_EL12);      break;
 830         case PAR_EL1:           write_sysreg_s(val, SYS_PAR_EL1);       break;
 831         case DACR32_EL2:        write_sysreg_s(val, SYS_DACR32_EL2);    break;
 832         case IFSR32_EL2:        write_sysreg_s(val, SYS_IFSR32_EL2);    break;
 833         case DBGVCR32_EL2:      write_sysreg_s(val, SYS_DBGVCR32_EL2);  break;
 834         default:                return false;
 835         }
 836
 837         return true;
 838 }
 839
 840 struct kvm_vm_stat {
 841         struct kvm_vm_stat_generic generic;
 842 };
 843
 844 struct kvm_vcpu_stat {
 845         struct kvm_vcpu_stat_generic generic;
 846         u64 hvc_exit_stat;
 847         u64 wfe_exit_stat;
 848         u64 wfi_exit_stat;
 849         u64 mmio_exit_user;
 850         u64 mmio_exit_kernel;
 851         u64 signal_exits;
 852         u64 exits;
 853 };
 854
 855 void kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
 856 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
 857 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
 858 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
 859 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
 860
 861 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
 862 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
 863
 864 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
 865                               struct kvm_vcpu_events *events);
 866
 867 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
 868                               struct kvm_vcpu_events *events);
 869
 870 #define KVM_ARCH_WANT_MMU_NOTIFIER
 871
 872 void kvm_arm_halt_guest(struct kvm *kvm);
 873 void kvm_arm_resume_guest(struct kvm *kvm);
 874
 875 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid)
 876
 877 #ifndef __KVM_NVHE_HYPERVISOR__
 878 #define kvm_call_hyp_nvhe(f, ...)                                               \
 879         ({                                                              \
 880                 struct arm_smccc_res res;                               \
 881                                                                         \
 882                 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f),               \
 883                                   ##__VA_ARGS__, &res);                 \
 884                 WARN_ON(res.a0 != SMCCC_RET_SUCCESS);                   \
 885                                                                         \
 886                 res.a1;                                                 \
 887         })
 888
 889 /*
 890  * The couple of isb() below are there to guarantee the same behaviour
 891  * on VHE as on !VHE, where the eret to EL1 acts as a context
 892  * synchronization event.
 893  */
 894 #define kvm_call_hyp(f, ...)                                            \
 895         do {                                                            \
 896                 if (has_vhe()) {                                        \
 897                         f(__VA_ARGS__);                                 \
 898                         isb();                                          \
 899                 } else {                                                \
 900                         kvm_call_hyp_nvhe(f, ##__VA_ARGS__);            \
 901                 }                                                       \
 902         } while(0)
 903
 904 #define kvm_call_hyp_ret(f, ...)                                        \
 905         ({                                                              \
 906                 typeof(f(__VA_ARGS__)) ret;                             \
 907                                                                         \
 908                 if (has_vhe()) {                                        \
 909                         ret = f(__VA_ARGS__);                           \
 910                         isb();                                          \
 911                 } else {                                                \
 912                         ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__);      \
 913                 }                                                       \
 914                                                                         \
 915                 ret;                                                    \
 916         })
 917 #else /* __KVM_NVHE_HYPERVISOR__ */
 918 #define kvm_call_hyp(f, ...) f(__VA_ARGS__)
 919 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
 920 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
 921 #endif /* __KVM_NVHE_HYPERVISOR__ */
 922
 923 void force_vm_exit(const cpumask_t *mask);
 924
 925 int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
 926 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
 927
 928 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
 929 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
 930 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
 931 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
 932 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
 933 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
 934 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
 935
 936 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
 937
 938 int __init kvm_sys_reg_table_init(void);
 939
 940 bool lock_all_vcpus(struct kvm *kvm);
 941 void unlock_all_vcpus(struct kvm *kvm);
 942
 943 /* MMIO helpers */
 944 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
 945 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
 946
 947 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
 948 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
 949
 950 /*
 951  * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event,
 952  * arrived in guest context.  For arm64, any event that arrives while a vCPU is
 953  * loaded is considered to be "in guest".
 954  */
 955 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu)
 956 {
 957         return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu;
 958 }
 959
 960 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
 961 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
 962 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
 963
 964 bool kvm_arm_pvtime_supported(void);
 965 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
 966                             struct kvm_device_attr *attr);
 967 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
 968                             struct kvm_device_attr *attr);
 969 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
 970                             struct kvm_device_attr *attr);
 971
 972 extern unsigned int __ro_after_init kvm_arm_vmid_bits;
 973 int __init kvm_arm_vmid_alloc_init(void);
 974 void __init kvm_arm_vmid_alloc_free(void);
 975 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
 976 void kvm_arm_vmid_clear_active(void);
 977
 978 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
 979 {
 980         vcpu_arch->steal.base = INVALID_GPA;
 981 }
 982
 983 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
 984 {
 985         return (vcpu_arch->steal.base != INVALID_GPA);
 986 }
 987
 988 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
 989
 990 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
 991
 992 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
 993
 994 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
 995 {
 996         /* The host's MPIDR is immutable, so let's set it up at boot time */
 997         ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
 998 }
 999
1000 static inline bool kvm_system_needs_idmapped_vectors(void)
1001 {
1002         return cpus_have_const_cap(ARM64_SPECTRE_V3A);
1003 }
1004
1005 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu);
1006
1007 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
1008 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
1009
1010 void kvm_arm_init_debug(void);
1011 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu);
1012 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
1013 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
1014 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
1015
1016 #define kvm_vcpu_os_lock_enabled(vcpu)          \
1017         (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & SYS_OSLSR_OSLK))
1018
1019 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
1020                                struct kvm_device_attr *attr);
1021 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
1022                                struct kvm_device_attr *attr);
1023 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
1024                                struct kvm_device_attr *attr);
1025
1026 long kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1027                                 struct kvm_arm_copy_mte_tags *copy_tags);
1028 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm,
1029                                     struct kvm_arm_counter_offset *offset);
1030
1031 /* Guest/host FPSIMD coordination helpers */
1032 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
1033 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
1034 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu);
1035 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
1036 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
1037 void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu);
1038
1039 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
1040 {
1041         return (!has_vhe() && attr->exclude_host);
1042 }
1043
1044 /* Flags for host debug state */
1045 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu);
1046 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu);
1047
1048 #ifdef CONFIG_KVM
1049 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
1050 void kvm_clr_pmu_events(u32 clr);
1051 #else
1052 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
1053 static inline void kvm_clr_pmu_events(u32 clr) {}
1054 #endif
1055
1056 void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);
1057 void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu);
1058
1059 int __init kvm_set_ipa_limit(void);
1060
1061 #define __KVM_HAVE_ARCH_VM_ALLOC
1062 struct kvm *kvm_arch_alloc_vm(void);
1063
1064 static inline bool kvm_vm_is_protected(struct kvm *kvm)
1065 {
1066         return false;
1067 }
1068
1069 void kvm_init_protected_traps(struct kvm_vcpu *vcpu);
1070
1071 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
1072 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
1073
1074 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED)
1075
1076 #define kvm_has_mte(kvm)                                        \
1077         (system_supports_mte() &&                               \
1078          test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags))
1079
1080 #define kvm_supports_32bit_el0()                                \
1081         (system_supports_32bit_el0() &&                         \
1082          !static_branch_unlikely(&arm64_mismatched_32bit_el0))
1083
1084 #define kvm_vm_has_ran_once(kvm)                                        \
1085         (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags))
1086
1087 int kvm_trng_call(struct kvm_vcpu *vcpu);
1088 #ifdef CONFIG_KVM
1089 extern phys_addr_t hyp_mem_base;
1090 extern phys_addr_t hyp_mem_size;
1091 void __init kvm_hyp_reserve(void);
1092 #else
1093 static inline void kvm_hyp_reserve(void) { }
1094 #endif
1095
1096 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
1097 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
1098
1099 #endif /* __ARM64_KVM_HOST_H__ */