2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * Derived from arch/arm/include/asm/kvm_host.h:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef __ARM64_KVM_HOST_H__
23 #define __ARM64_KVM_HOST_H__
25 #include <linux/bitmap.h>
26 #include <linux/types.h>
27 #include <linux/jump_label.h>
28 #include <linux/kvm_types.h>
29 #include <linux/percpu.h>
30 #include <asm/arch_gicv3.h>
31 #include <asm/barrier.h>
32 #include <asm/cpufeature.h>
33 #include <asm/daifflags.h>
34 #include <asm/fpsimd.h>
36 #include <asm/kvm_asm.h>
37 #include <asm/kvm_mmio.h>
38 #include <asm/smp_plat.h>
39 #include <asm/thread_info.h>
41 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
43 #define KVM_USER_MEM_SLOTS 512
44 #define KVM_HALT_POLL_NS_DEFAULT 500000
46 #include <kvm/arm_vgic.h>
47 #include <kvm/arm_arch_timer.h>
48 #include <kvm/arm_pmu.h>
50 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
52 #define KVM_VCPU_MAX_FEATURES 5
54 #define KVM_REQ_SLEEP \
55 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
56 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
57 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
59 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
61 extern unsigned int kvm_sve_max_vl;
62 int kvm_arm_init_sve(void);
64 int __attribute_const__ kvm_target_cpu(void);
65 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
66 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu);
67 int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext);
68 void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start);
71 /* The VMID generation used for the virt. memory system */
79 /* stage2 entry level table */
83 /* VTCR_EL2 value for this VM */
86 /* The last vcpu id that ran on each physical CPU */
87 int __percpu *last_vcpu_ran;
89 /* The maximum number of vCPUs depends on the used GIC model */
92 /* Interrupt controller */
93 struct vgic_dist vgic;
95 /* Mandated version of PSCI */
99 #define KVM_NR_MEM_OBJS 40
102 * We don't want allocation failures within the mmu code, so we preallocate
103 * enough memory for a single page fault in a cache.
105 struct kvm_mmu_memory_cache {
107 void *objects[KVM_NR_MEM_OBJS];
110 struct kvm_vcpu_fault_info {
111 u32 esr_el2; /* Hyp Syndrom Register */
112 u64 far_el2; /* Hyp Fault Address Register */
113 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
114 u64 disr_el1; /* Deferred [SError] Status Register */
118 * 0 is reserved as an invalid value.
119 * Order should be kept in sync with the save/restore code.
123 MPIDR_EL1, /* MultiProcessor Affinity Register */
124 CSSELR_EL1, /* Cache Size Selection Register */
125 SCTLR_EL1, /* System Control Register */
126 ACTLR_EL1, /* Auxiliary Control Register */
127 CPACR_EL1, /* Coprocessor Access Control */
128 ZCR_EL1, /* SVE Control */
129 TTBR0_EL1, /* Translation Table Base Register 0 */
130 TTBR1_EL1, /* Translation Table Base Register 1 */
131 TCR_EL1, /* Translation Control Register */
132 ESR_EL1, /* Exception Syndrome Register */
133 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
134 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
135 FAR_EL1, /* Fault Address Register */
136 MAIR_EL1, /* Memory Attribute Indirection Register */
137 VBAR_EL1, /* Vector Base Address Register */
138 CONTEXTIDR_EL1, /* Context ID Register */
139 TPIDR_EL0, /* Thread ID, User R/W */
140 TPIDRRO_EL0, /* Thread ID, User R/O */
141 TPIDR_EL1, /* Thread ID, Privileged */
142 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
143 CNTKCTL_EL1, /* Timer Control Register (EL1) */
144 PAR_EL1, /* Physical Address Register */
145 MDSCR_EL1, /* Monitor Debug System Control Register */
146 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
147 DISR_EL1, /* Deferred Interrupt Status Register */
149 /* Performance Monitors Registers */
150 PMCR_EL0, /* Control Register */
151 PMSELR_EL0, /* Event Counter Selection Register */
152 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
153 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
154 PMCCNTR_EL0, /* Cycle Counter Register */
155 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
156 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
157 PMCCFILTR_EL0, /* Cycle Count Filter Register */
158 PMCNTENSET_EL0, /* Count Enable Set Register */
159 PMINTENSET_EL1, /* Interrupt Enable Set Register */
160 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
161 PMSWINC_EL0, /* Software Increment Register */
162 PMUSERENR_EL0, /* User Enable Register */
164 /* 32bit specific registers. Keep them at the end of the range */
165 DACR32_EL2, /* Domain Access Control Register */
166 IFSR32_EL2, /* Instruction Fault Status Register */
167 FPEXC32_EL2, /* Floating-Point Exception Control Register */
168 DBGVCR32_EL2, /* Debug Vector Catch Register */
170 NR_SYS_REGS /* Nothing after this line! */
174 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
175 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
176 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
177 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
178 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
179 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
180 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
181 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
182 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
183 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
184 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
185 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
186 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
187 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
188 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
189 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
190 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
191 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
192 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
193 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
194 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
195 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
196 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
197 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
198 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
199 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
200 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
201 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
202 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
204 #define cp14_DBGDSCRext (MDSCR_EL1 * 2)
205 #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
206 #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
207 #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1)
208 #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
209 #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
210 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
212 #define NR_COPRO_REGS (NR_SYS_REGS * 2)
214 struct kvm_cpu_context {
215 struct kvm_regs gp_regs;
217 u64 sys_regs[NR_SYS_REGS];
218 u32 copro[NR_COPRO_REGS];
221 struct kvm_vcpu *__hyp_running_vcpu;
224 typedef struct kvm_cpu_context kvm_cpu_context_t;
226 struct vcpu_reset_state {
233 struct kvm_vcpu_arch {
234 struct kvm_cpu_context ctxt;
236 unsigned int sve_max_vl;
238 /* HYP configuration */
242 /* Exception Information */
243 struct kvm_vcpu_fault_info fault;
245 /* State of various workarounds, see kvm_asm.h for bit assignment */
246 u64 workaround_flags;
248 /* Miscellaneous vcpu state flags */
252 * We maintain more than a single set of debug registers to support
253 * debugging the guest from the host and to maintain separate host and
254 * guest state during world switches. vcpu_debug_state are the debug
255 * registers of the vcpu as the guest sees them. host_debug_state are
256 * the host registers which are saved and restored during
257 * world switches. external_debug_state contains the debug
258 * values we want to debug the guest. This is set via the
259 * KVM_SET_GUEST_DEBUG ioctl.
261 * debug_ptr points to the set of debug registers that should be loaded
262 * onto the hardware when running the guest.
264 struct kvm_guest_debug_arch *debug_ptr;
265 struct kvm_guest_debug_arch vcpu_debug_state;
266 struct kvm_guest_debug_arch external_debug_state;
268 /* Pointer to host CPU context */
269 kvm_cpu_context_t *host_cpu_context;
271 struct thread_info *host_thread_info; /* hyp VA */
272 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */
275 /* {Break,watch}point registers */
276 struct kvm_guest_debug_arch regs;
277 /* Statistical profiling extension */
282 struct vgic_cpu vgic_cpu;
283 struct arch_timer_cpu timer_cpu;
287 * Anything that is not used directly from assembly code goes
292 * Guest registers we preserve during guest debugging.
294 * These shadow registers are updated by the kvm_handle_sys_reg
295 * trap handler if the guest accesses or updates them while we
296 * are using guest debug.
300 } guest_debug_preserved;
302 /* vcpu power-off state */
305 /* Don't run the guest (internal implementation need) */
308 /* IO related fields */
309 struct kvm_decode mmio_decode;
311 /* Cache some mmu pages needed inside spinlock regions */
312 struct kvm_mmu_memory_cache mmu_page_cache;
314 /* Target CPU and feature flags */
316 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
318 /* Detect first run of a vcpu */
321 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
324 /* Additional reset state */
325 struct vcpu_reset_state reset_state;
327 /* True when deferrable sysregs are loaded on the physical CPU,
328 * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */
329 bool sysregs_loaded_on_cpu;
332 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
333 #define vcpu_sve_pffr(vcpu) ((void *)((char *)((vcpu)->arch.sve_state) + \
334 sve_ffr_offset((vcpu)->arch.sve_max_vl)))
336 #define vcpu_sve_state_size(vcpu) ({ \
338 unsigned int __vcpu_vq; \
340 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \
343 __vcpu_vq = sve_vq_from_vl((vcpu)->arch.sve_max_vl); \
344 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \
350 /* vcpu_arch flags field values: */
351 #define KVM_ARM64_DEBUG_DIRTY (1 << 0)
352 #define KVM_ARM64_FP_ENABLED (1 << 1) /* guest FP regs loaded */
353 #define KVM_ARM64_FP_HOST (1 << 2) /* host FP regs loaded */
354 #define KVM_ARM64_HOST_SVE_IN_USE (1 << 3) /* backup for host TIF_SVE */
355 #define KVM_ARM64_HOST_SVE_ENABLED (1 << 4) /* SVE enabled for EL0 */
356 #define KVM_ARM64_GUEST_HAS_SVE (1 << 5) /* SVE exposed to guest */
357 #define KVM_ARM64_VCPU_SVE_FINALIZED (1 << 6) /* SVE config completed */
358 #define KVM_ARM64_GUEST_HAS_PTRAUTH (1 << 7) /* PTRAUTH exposed to guest */
360 #define vcpu_has_sve(vcpu) (system_supports_sve() && \
361 ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_SVE))
363 #define vcpu_has_ptrauth(vcpu) ((system_supports_address_auth() || \
364 system_supports_generic_auth()) && \
365 ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_PTRAUTH))
367 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs)
370 * Only use __vcpu_sys_reg if you know you want the memory backed version of a
371 * register, and not the one most recently accessed by a running VCPU. For
372 * example, for userspace access or for system registers that are never context
373 * switched, but only emulated.
375 #define __vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)])
377 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
378 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
381 * CP14 and CP15 live in the same array, as they are backed by the
382 * same system registers.
384 #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)])
385 #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)])
388 ulong remote_tlb_flush;
391 struct kvm_vcpu_stat {
392 u64 halt_successful_poll;
393 u64 halt_attempted_poll;
394 u64 halt_poll_invalid;
400 u64 mmio_exit_kernel;
404 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
405 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
406 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
407 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
408 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
409 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
410 struct kvm_vcpu_events *events);
412 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
413 struct kvm_vcpu_events *events);
415 #define KVM_ARCH_WANT_MMU_NOTIFIER
416 int kvm_unmap_hva_range(struct kvm *kvm,
417 unsigned long start, unsigned long end);
418 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
419 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
420 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
422 struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
423 struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
424 void kvm_arm_halt_guest(struct kvm *kvm);
425 void kvm_arm_resume_guest(struct kvm *kvm);
427 u64 __kvm_call_hyp(void *hypfn, ...);
430 * The couple of isb() below are there to guarantee the same behaviour
431 * on VHE as on !VHE, where the eret to EL1 acts as a context
432 * synchronization event.
434 #define kvm_call_hyp(f, ...) \
440 __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__); \
444 #define kvm_call_hyp_ret(f, ...) \
446 typeof(f(__VA_ARGS__)) ret; \
449 ret = f(__VA_ARGS__); \
452 ret = __kvm_call_hyp(kvm_ksym_ref(f), \
459 void force_vm_exit(const cpumask_t *mask);
460 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
462 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
463 int exception_index);
464 void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run,
465 int exception_index);
467 int kvm_perf_init(void);
468 int kvm_perf_teardown(void);
470 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
472 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
474 DECLARE_PER_CPU(kvm_cpu_context_t, kvm_host_cpu_state);
476 static inline void kvm_init_host_cpu_context(kvm_cpu_context_t *cpu_ctxt,
479 /* The host's MPIDR is immutable, so let's set it up at boot time */
480 cpu_ctxt->sys_regs[MPIDR_EL1] = cpu_logical_map(cpu);
483 void __kvm_enable_ssbs(void);
485 static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
486 unsigned long hyp_stack_ptr,
487 unsigned long vector_ptr)
490 * Calculate the raw per-cpu offset without a translation from the
491 * kernel's mapping to the linear mapping, and store it in tpidr_el2
492 * so that we can use adr_l to access per-cpu variables in EL2.
494 u64 tpidr_el2 = ((u64)this_cpu_ptr(&kvm_host_cpu_state) -
495 (u64)kvm_ksym_ref(kvm_host_cpu_state));
498 * Call initialization code, and switch to the full blown HYP code.
499 * If the cpucaps haven't been finalized yet, something has gone very
500 * wrong, and hyp will crash and burn when it uses any
501 * cpus_have_const_cap() wrapper.
503 BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
504 __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr, tpidr_el2);
507 * Disabling SSBD on a non-VHE system requires us to enable SSBS
510 if (!has_vhe() && this_cpu_has_cap(ARM64_SSBS) &&
511 arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
512 kvm_call_hyp(__kvm_enable_ssbs);
516 static inline bool kvm_arch_requires_vhe(void)
519 * The Arm architecture specifies that implementation of SVE
520 * requires VHE also to be implemented. The KVM code for arm64
521 * relies on this when SVE is present:
523 if (system_supports_sve())
526 /* Some implementations have defects that confine them to VHE */
527 if (cpus_have_cap(ARM64_WORKAROUND_1165522))
533 static inline void kvm_arch_hardware_unsetup(void) {}
534 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
535 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
536 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
538 void kvm_arm_init_debug(void);
539 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
540 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
541 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
542 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
543 struct kvm_device_attr *attr);
544 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
545 struct kvm_device_attr *attr);
546 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
547 struct kvm_device_attr *attr);
549 static inline void __cpu_init_stage2(void) {}
551 /* Guest/host FPSIMD coordination helpers */
552 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
553 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
554 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
555 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
557 #ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */
558 static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu)
560 return kvm_arch_vcpu_run_map_fp(vcpu);
564 static inline void kvm_arm_vhe_guest_enter(void)
569 * Having IRQs masked via PMR when entering the guest means the GIC
570 * will not signal the CPU of interrupts of lower priority, and the
571 * only way to get out will be via guest exceptions.
572 * Naturally, we want to avoid this.
574 if (system_uses_irq_prio_masking()) {
575 gic_write_pmr(GIC_PRIO_IRQON);
580 static inline void kvm_arm_vhe_guest_exit(void)
583 * local_daif_restore() takes care to properly restore PSTATE.DAIF
584 * and the GIC PMR if the host is using IRQ priorities.
586 local_daif_restore(DAIF_PROCCTX_NOIRQ);
589 * When we exit from the guest we change a number of CPU configuration
590 * parameters, such as traps. Make sure these changes take effect
591 * before running the host or additional guests.
596 static inline bool kvm_arm_harden_branch_predictor(void)
598 return cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR);
601 #define KVM_SSBD_UNKNOWN -1
602 #define KVM_SSBD_FORCE_DISABLE 0
603 #define KVM_SSBD_KERNEL 1
604 #define KVM_SSBD_FORCE_ENABLE 2
605 #define KVM_SSBD_MITIGATED 3
607 static inline int kvm_arm_have_ssbd(void)
609 switch (arm64_get_ssbd_state()) {
610 case ARM64_SSBD_FORCE_DISABLE:
611 return KVM_SSBD_FORCE_DISABLE;
612 case ARM64_SSBD_KERNEL:
613 return KVM_SSBD_KERNEL;
614 case ARM64_SSBD_FORCE_ENABLE:
615 return KVM_SSBD_FORCE_ENABLE;
616 case ARM64_SSBD_MITIGATED:
617 return KVM_SSBD_MITIGATED;
618 case ARM64_SSBD_UNKNOWN:
620 return KVM_SSBD_UNKNOWN;
624 void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu);
625 void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu);
627 void kvm_set_ipa_limit(void);
629 #define __KVM_HAVE_ARCH_VM_ALLOC
630 struct kvm *kvm_arch_alloc_vm(void);
631 void kvm_arch_free_vm(struct kvm *kvm);
633 int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type);
635 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
636 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
638 #define kvm_arm_vcpu_sve_finalized(vcpu) \
639 ((vcpu)->arch.flags & KVM_ARM64_VCPU_SVE_FINALIZED)
641 #endif /* __ARM64_KVM_HOST_H__ */