2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __ARM64_KVM_ARM_H__
19 #define __ARM64_KVM_ARM_H__
22 #include <asm/memory.h>
23 #include <asm/types.h>
25 /* Hyp Configuration Register (HCR) bits */
26 #define HCR_FWB (UL(1) << 46)
27 #define HCR_TEA (UL(1) << 37)
28 #define HCR_TERR (UL(1) << 36)
29 #define HCR_TLOR (UL(1) << 35)
30 #define HCR_E2H (UL(1) << 34)
31 #define HCR_ID (UL(1) << 33)
32 #define HCR_CD (UL(1) << 32)
33 #define HCR_RW_SHIFT 31
34 #define HCR_RW (UL(1) << HCR_RW_SHIFT)
35 #define HCR_TRVM (UL(1) << 30)
36 #define HCR_HCD (UL(1) << 29)
37 #define HCR_TDZ (UL(1) << 28)
38 #define HCR_TGE (UL(1) << 27)
39 #define HCR_TVM (UL(1) << 26)
40 #define HCR_TTLB (UL(1) << 25)
41 #define HCR_TPU (UL(1) << 24)
42 #define HCR_TPC (UL(1) << 23)
43 #define HCR_TSW (UL(1) << 22)
44 #define HCR_TAC (UL(1) << 21)
45 #define HCR_TIDCP (UL(1) << 20)
46 #define HCR_TSC (UL(1) << 19)
47 #define HCR_TID3 (UL(1) << 18)
48 #define HCR_TID2 (UL(1) << 17)
49 #define HCR_TID1 (UL(1) << 16)
50 #define HCR_TID0 (UL(1) << 15)
51 #define HCR_TWE (UL(1) << 14)
52 #define HCR_TWI (UL(1) << 13)
53 #define HCR_DC (UL(1) << 12)
54 #define HCR_BSU (3 << 10)
55 #define HCR_BSU_IS (UL(1) << 10)
56 #define HCR_FB (UL(1) << 9)
57 #define HCR_VSE (UL(1) << 8)
58 #define HCR_VI (UL(1) << 7)
59 #define HCR_VF (UL(1) << 6)
60 #define HCR_AMO (UL(1) << 5)
61 #define HCR_IMO (UL(1) << 4)
62 #define HCR_FMO (UL(1) << 3)
63 #define HCR_PTW (UL(1) << 2)
64 #define HCR_SWIO (UL(1) << 1)
65 #define HCR_VM (UL(1) << 0)
68 * The bits we set in HCR:
69 * TLOR: Trap LORegion register accesses
70 * RW: 64bit by default, can be overridden for 32bit VMs
73 * TVM: Trap VM ops (until M+C set in SCTLR_EL1)
74 * TSW: Trap cache operations by set/way
77 * TIDCP: Trap L2CTLR/L2ECTLR
78 * BSU_IS: Upgrade barriers to the inner shareable domain
79 * FB: Force broadcast of all maintainance operations
80 * AMO: Override CPSR.A and enable signaling with VA
81 * IMO: Override CPSR.I and enable signaling with VI
82 * FMO: Override CPSR.F and enable signaling with VF
83 * SWIO: Turn set/way invalidates into set/way clean+invalidate
85 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
86 HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
87 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
89 #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
90 #define HCR_HOST_NVHE_FLAGS (HCR_RW)
91 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
93 /* TCR_EL2 Registers bits */
94 #define TCR_EL2_RES1 ((1 << 31) | (1 << 23))
95 #define TCR_EL2_TBI (1 << 20)
96 #define TCR_EL2_PS_SHIFT 16
97 #define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT)
98 #define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT)
99 #define TCR_EL2_TG0_MASK TCR_TG0_MASK
100 #define TCR_EL2_SH0_MASK TCR_SH0_MASK
101 #define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
102 #define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
103 #define TCR_EL2_T0SZ_MASK 0x3f
104 #define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
105 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)
107 /* VTCR_EL2 Registers bits */
108 #define VTCR_EL2_RES1 (1 << 31)
109 #define VTCR_EL2_HD (1 << 22)
110 #define VTCR_EL2_HA (1 << 21)
111 #define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT
112 #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK
113 #define VTCR_EL2_TG0_MASK TCR_TG0_MASK
114 #define VTCR_EL2_TG0_4K TCR_TG0_4K
115 #define VTCR_EL2_TG0_16K TCR_TG0_16K
116 #define VTCR_EL2_TG0_64K TCR_TG0_64K
117 #define VTCR_EL2_SH0_MASK TCR_SH0_MASK
118 #define VTCR_EL2_SH0_INNER TCR_SH0_INNER
119 #define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
120 #define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA
121 #define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
122 #define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA
123 #define VTCR_EL2_SL0_SHIFT 6
124 #define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT)
125 #define VTCR_EL2_T0SZ_MASK 0x3f
126 #define VTCR_EL2_VS_SHIFT 19
127 #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT)
128 #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT)
130 #define VTCR_EL2_T0SZ(x) TCR_T0SZ(x)
133 * We configure the Stage-2 page tables to always restrict the IPA space to be
134 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
135 * not known to exist and will break with this configuration.
137 * The VTCR_EL2 is configured per VM and is initialised in kvm_arm_setup_stage2().
139 * Note that when using 4K pages, we concatenate two first level page tables
140 * together. With 16K pages, we concatenate 16 first level page tables.
144 #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
145 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)
148 * VTCR_EL2:SL0 indicates the entry level for Stage2 translation.
149 * Interestingly, it depends on the page size.
150 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
152 * -----------------------------------------
153 * | Entry level | 4K | 16K/64K |
154 * ------------------------------------------
155 * | Level: 0 | 2 | - |
156 * ------------------------------------------
157 * | Level: 1 | 1 | 2 |
158 * ------------------------------------------
159 * | Level: 2 | 0 | 1 |
160 * ------------------------------------------
161 * | Level: 3 | - | 0 |
162 * ------------------------------------------
164 * The table roughly translates to :
166 * SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
168 * Where TGRAN_SL0_BASE is a magic number depending on the page size:
169 * TGRAN_SL0_BASE(4K) = 2
170 * TGRAN_SL0_BASE(16K) = 3
171 * TGRAN_SL0_BASE(64K) = 3
172 * provided we take care of ruling out the unsupported cases and
173 * Entry_Level = 4 - Number_of_levels.
176 #ifdef CONFIG_ARM64_64K_PAGES
178 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K
179 #define VTCR_EL2_TGRAN_SL0_BASE 3UL
181 #elif defined(CONFIG_ARM64_16K_PAGES)
183 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K
184 #define VTCR_EL2_TGRAN_SL0_BASE 3UL
188 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K
189 #define VTCR_EL2_TGRAN_SL0_BASE 2UL
193 #define VTCR_EL2_LVLS_TO_SL0(levels) \
194 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
195 #define VTCR_EL2_SL0_TO_LVLS(sl0) \
196 ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
197 #define VTCR_EL2_LVLS(vtcr) \
198 VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT)
200 #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN)
201 #define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
204 * ARM VMSAv8-64 defines an algorithm for finding the translation table
205 * descriptors in section D4.2.8 in ARM DDI 0487C.a.
207 * The algorithm defines the expectations on the translation table
208 * addresses for each level, based on PAGE_SIZE, entry level
209 * and the translation table size (T0SZ). The variable "x" in the
210 * algorithm determines the alignment of a table base address at a given
211 * level and thus determines the alignment of VTTBR:BADDR for stage2
212 * page table entry level.
213 * Since the number of bits resolved at the entry level could vary
214 * depending on the T0SZ, the value of "x" is defined based on a
215 * Magic constant for a given PAGE_SIZE and Entry Level. The
216 * intermediate levels must be always aligned to the PAGE_SIZE (i.e,
219 * The value of "x" for entry level is calculated as :
222 * where Magic_N is an integer depending on the page size and the entry
223 * level of the page table as below:
225 * --------------------------------------------
226 * | Entry level | 4K 16K 64K |
227 * --------------------------------------------
228 * | Level: 0 (4 levels) | 28 | - | - |
229 * --------------------------------------------
230 * | Level: 1 (3 levels) | 37 | 31 | 25 |
231 * --------------------------------------------
232 * | Level: 2 (2 levels) | 46 | 42 | 38 |
233 * --------------------------------------------
234 * | Level: 3 (1 level) | - | 53 | 51 |
235 * --------------------------------------------
237 * We have a magic formula for the Magic_N below:
239 * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
241 * where Number_of_levels = (4 - Level). We are only interested in the
242 * value for Entry_Level for the stage2 page table.
244 * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
246 * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
247 * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
249 * Here is one way to explain the Magic Formula:
251 * x = log2(Size_of_Entry_Level_Table)
253 * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
254 * PAGE_SHIFT bits in the PTE, we have :
256 * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
257 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
258 * where n = number of levels, and since each pointer is 8bytes, we have:
260 * x = Bits_Entry_Level + 3
261 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n
263 * The only constraint here is that, we have to find the number of page table
264 * levels for a given IPA size (which we do, see stage2_pt_levels())
266 #define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3)))
268 #define VTTBR_CNP_BIT (UL(1))
269 #define VTTBR_VMID_SHIFT (UL(48))
270 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
272 /* Hyp System Trap Register */
273 #define HSTR_EL2_T(x) (1 << x)
275 /* Hyp Coprocessor Trap Register Shifts */
276 #define CPTR_EL2_TFP_SHIFT 10
278 /* Hyp Coprocessor Trap Register */
279 #define CPTR_EL2_TCPAC (1 << 31)
280 #define CPTR_EL2_TTA (1 << 20)
281 #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT)
282 #define CPTR_EL2_TZ (1 << 8)
283 #define CPTR_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 */
284 #define CPTR_EL2_DEFAULT CPTR_EL2_RES1
286 /* Hyp Debug Configuration Register bits */
287 #define MDCR_EL2_TPMS (1 << 14)
288 #define MDCR_EL2_E2PB_MASK (UL(0x3))
289 #define MDCR_EL2_E2PB_SHIFT (UL(12))
290 #define MDCR_EL2_TDRA (1 << 11)
291 #define MDCR_EL2_TDOSA (1 << 10)
292 #define MDCR_EL2_TDA (1 << 9)
293 #define MDCR_EL2_TDE (1 << 8)
294 #define MDCR_EL2_HPME (1 << 7)
295 #define MDCR_EL2_TPM (1 << 6)
296 #define MDCR_EL2_TPMCR (1 << 5)
297 #define MDCR_EL2_HPMN_MASK (0x1F)
299 /* For compatibility with fault code shared with 32-bit */
300 #define FSC_FAULT ESR_ELx_FSC_FAULT
301 #define FSC_ACCESS ESR_ELx_FSC_ACCESS
302 #define FSC_PERM ESR_ELx_FSC_PERM
303 #define FSC_SEA ESR_ELx_FSC_EXTABT
304 #define FSC_SEA_TTW0 (0x14)
305 #define FSC_SEA_TTW1 (0x15)
306 #define FSC_SEA_TTW2 (0x16)
307 #define FSC_SEA_TTW3 (0x17)
308 #define FSC_SECC (0x18)
309 #define FSC_SECC_TTW0 (0x1c)
310 #define FSC_SECC_TTW1 (0x1d)
311 #define FSC_SECC_TTW2 (0x1e)
312 #define FSC_SECC_TTW3 (0x1f)
314 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
315 #define HPFAR_MASK (~UL(0xf))
318 * PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12]
319 * HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12]
321 #define PAR_TO_HPFAR(par) \
322 (((par) & GENMASK_ULL(PHYS_MASK_SHIFT - 1, 12)) >> 8)
324 #define kvm_arm_exception_type \
328 #define ECN(x) { ESR_ELx_EC_##x, #x }
330 #define kvm_arm_exception_class \
331 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
332 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(CP14_64), ECN(SVC64), \
333 ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(IMP_DEF), ECN(IABT_LOW), \
334 ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
335 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
336 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
337 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
338 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)
340 #define CPACR_EL1_FPEN (3 << 20)
341 #define CPACR_EL1_TTA (1 << 28)
342 #define CPACR_EL1_DEFAULT (CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN)
344 #endif /* __ARM64_KVM_ARM_H__ */