2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <asm/cputype.h>
21 #define CTR_L1IP_SHIFT 14
22 #define CTR_L1IP_MASK 3
23 #define CTR_DMINLINE_SHIFT 16
24 #define CTR_IMINLINE_SHIFT 0
25 #define CTR_ERG_SHIFT 20
26 #define CTR_CWG_SHIFT 24
27 #define CTR_CWG_MASK 15
28 #define CTR_IDC_SHIFT 28
29 #define CTR_DIC_SHIFT 29
31 #define CTR_CACHE_MINLINE_MASK \
32 (0xf << CTR_DMINLINE_SHIFT | 0xf << CTR_IMINLINE_SHIFT)
34 #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
36 #define ICACHE_POLICY_VPIPT 0
37 #define ICACHE_POLICY_VIPT 2
38 #define ICACHE_POLICY_PIPT 3
40 #define L1_CACHE_SHIFT (6)
41 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
44 #define CLIDR_LOUU_SHIFT 27
45 #define CLIDR_LOC_SHIFT 24
46 #define CLIDR_LOUIS_SHIFT 21
48 #define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
49 #define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
50 #define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
53 * Memory returned by kmalloc() may be used for DMA, so we must make
54 * sure that all such allocations are cache aligned. Otherwise,
55 * unrelated code may cause parts of the buffer to be read into the
56 * cache before the transfer is done, causing old data to be seen by
59 #define ARCH_DMA_MINALIGN (128)
61 #ifdef CONFIG_KASAN_SW_TAGS
62 #define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT)
64 #define ARCH_SLAB_MINALIGN __alignof__(unsigned long long)
69 #include <linux/bitops.h>
71 #define ICACHEF_ALIASING 0
72 #define ICACHEF_VPIPT 1
73 extern unsigned long __icache_flags;
76 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
77 * permitted in the I-cache.
79 static inline int icache_is_aliasing(void)
81 return test_bit(ICACHEF_ALIASING, &__icache_flags);
84 static inline int icache_is_vpipt(void)
86 return test_bit(ICACHEF_VPIPT, &__icache_flags);
89 static inline u32 cache_type_cwg(void)
91 return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
94 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
96 static inline int cache_line_size(void)
98 u32 cwg = cache_type_cwg();
99 return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
103 * Read the effective value of CTR_EL0.
105 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
106 * section D10.2.33 "CTR_EL0, Cache Type Register" :
108 * CTR_EL0.IDC reports the data cache clean requirements for
109 * instruction to data coherence.
111 * 0 - dcache clean to PoU is required unless :
112 * (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
113 * 1 - dcache clean to PoU is not required for i-to-d coherence.
115 * This routine provides the CTR_EL0 with the IDC field updated to the
118 static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
120 u32 ctr = read_cpuid_cachetype();
122 if (!(ctr & BIT(CTR_IDC_SHIFT))) {
123 u64 clidr = read_sysreg(clidr_el1);
125 if (CLIDR_LOC(clidr) == 0 ||
126 (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
127 ctr |= BIT(CTR_IDC_SHIFT);
133 #endif /* __ASSEMBLY__ */