1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
5 * Copyright (C) 1996-2000 Russell King
6 * Copyright (C) 2012 ARM Ltd.
9 #error "Only include this from assembly code"
12 #ifndef __ASM_ASSEMBLER_H
13 #define __ASM_ASSEMBLER_H
15 #include <asm-generic/export.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/alternative.h>
19 #include <asm/asm-bug.h>
20 #include <asm/cpufeature.h>
21 #include <asm/cputype.h>
22 #include <asm/debug-monitors.h>
24 #include <asm/pgtable-hwdef.h>
25 #include <asm/ptrace.h>
26 #include <asm/thread_info.h>
29 * Provide a wxN alias for each wN register so what we can paste a xN
30 * reference after a 'w' to obtain the 32-bit version.
32 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
36 .macro save_and_disable_daif, flags
49 .macro restore_daif, flags:req
53 /* IRQ is the lowest priority flag, unconditionally unmask the rest. */
55 msr daifclr, #(8 | 4 | 1)
59 * Save/restore interrupts.
61 .macro save_and_disable_irq, flags
66 .macro restore_irq, flags
74 .macro disable_step_tsk, flgs, tmp
75 tbz \flgs, #TIF_SINGLESTEP, 9990f
77 bic \tmp, \tmp, #DBG_MDSCR_SS
79 isb // Synchronise with enable_dbg
83 /* call with daif masked */
84 .macro enable_step_tsk, flgs, tmp
85 tbz \flgs, #TIF_SINGLESTEP, 9990f
87 orr \tmp, \tmp, #DBG_MDSCR_SS
93 * RAS Error Synchronization barrier
96 #ifdef CONFIG_ARM64_RAS_EXTN
104 * Value prediction barrier
111 * Speculation barrier
114 alternative_if_not ARM64_HAS_SB
133 * Emit an entry into the exception table
135 .macro _asm_extable, from, to
136 .pushsection __ex_table, "a"
138 .long (\from - .), (\to - .)
142 #define USER(l, x...) \
144 _asm_extable 9999b, l
149 lr .req x30 // link register
160 * Select code when configured for BE.
162 #ifdef CONFIG_CPU_BIG_ENDIAN
163 #define CPU_BE(code...) code
165 #define CPU_BE(code...)
169 * Select code when configured for LE.
171 #ifdef CONFIG_CPU_BIG_ENDIAN
172 #define CPU_LE(code...)
174 #define CPU_LE(code...) code
178 * Define a macro that constructs a 64-bit value by concatenating two
179 * 32-bit registers. Note that on big endian systems the order of the
180 * registers is swapped.
182 #ifndef CONFIG_CPU_BIG_ENDIAN
183 .macro regs_to_64, rd, lbits, hbits
185 .macro regs_to_64, rd, hbits, lbits
187 orr \rd, \lbits, \hbits, lsl #32
191 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
192 * <symbol> is within the range +/- 4 GB of the PC.
195 * @dst: destination register (64 bit wide)
196 * @sym: name of the symbol
198 .macro adr_l, dst, sym
200 add \dst, \dst, :lo12:\sym
204 * @dst: destination register (32 or 64 bit wide)
205 * @sym: name of the symbol
206 * @tmp: optional 64-bit scratch register to be used if <dst> is a
207 * 32-bit wide register, in which case it cannot be used to hold
210 .macro ldr_l, dst, sym, tmp=
213 ldr \dst, [\dst, :lo12:\sym]
216 ldr \dst, [\tmp, :lo12:\sym]
221 * @src: source register (32 or 64 bit wide)
222 * @sym: name of the symbol
223 * @tmp: mandatory 64-bit scratch register to calculate the address
224 * while <src> needs to be preserved.
226 .macro str_l, src, sym, tmp
228 str \src, [\tmp, :lo12:\sym]
232 * @dst: destination register
234 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__)
235 .macro this_cpu_offset, dst
239 .macro this_cpu_offset, dst
240 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
249 * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP)
250 * @sym: The name of the per-cpu variable
251 * @tmp: scratch register
253 .macro adr_this_cpu, dst, sym, tmp
255 add \dst, \tmp, #:lo12:\sym
261 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
262 * @sym: The name of the per-cpu variable
263 * @tmp: scratch register
265 .macro ldr_this_cpu dst, sym, tmp
268 ldr \dst, [\dst, \tmp]
272 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
274 .macro vma_vm_mm, rd, rn
275 ldr \rd, [\rn, #VMA_VM_MM]
279 * read_ctr - read CTR_EL0. If the system has mismatched register fields,
280 * provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val
283 #ifndef __KVM_NVHE_HYPERVISOR__
284 alternative_if_not ARM64_MISMATCHED_CACHE_TYPE
285 mrs \reg, ctr_el0 // read CTR
288 ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
291 alternative_if_not ARM64_KVM_PROTECTED_MODE
293 alternative_else_nop_endif
294 alternative_cb kvm_compute_final_ctr_el0
296 movk \reg, #0, lsl #16
297 movk \reg, #0, lsl #32
298 movk \reg, #0, lsl #48
305 * raw_dcache_line_size - get the minimum D-cache line size on this CPU
306 * from the CTR register.
308 .macro raw_dcache_line_size, reg, tmp
309 mrs \tmp, ctr_el0 // read CTR
310 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
311 mov \reg, #4 // bytes per word
312 lsl \reg, \reg, \tmp // actual cache line size
316 * dcache_line_size - get the safe D-cache line size across all CPUs
318 .macro dcache_line_size, reg, tmp
320 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
321 mov \reg, #4 // bytes per word
322 lsl \reg, \reg, \tmp // actual cache line size
326 * raw_icache_line_size - get the minimum I-cache line size on this CPU
327 * from the CTR register.
329 .macro raw_icache_line_size, reg, tmp
330 mrs \tmp, ctr_el0 // read CTR
331 and \tmp, \tmp, #0xf // cache line size encoding
332 mov \reg, #4 // bytes per word
333 lsl \reg, \reg, \tmp // actual cache line size
337 * icache_line_size - get the safe I-cache line size across all CPUs
339 .macro icache_line_size, reg, tmp
341 and \tmp, \tmp, #0xf // cache line size encoding
342 mov \reg, #4 // bytes per word
343 lsl \reg, \reg, \tmp // actual cache line size
347 * tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map
349 .macro tcr_set_t0sz, valreg, t0sz
350 bfi \valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
354 * tcr_set_t1sz - update TCR.T1SZ
356 .macro tcr_set_t1sz, valreg, t1sz
357 bfi \valreg, \t1sz, #TCR_T1SZ_OFFSET, #TCR_TxSZ_WIDTH
361 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported
362 * ID_AA64MMFR0_EL1.PARange value
364 * tcr: register with the TCR_ELx value to be updated
365 * pos: IPS or PS bitfield position
366 * tmp{0,1}: temporary registers
368 .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1
369 mrs \tmp0, ID_AA64MMFR0_EL1
370 // Narrow PARange to fit the PS field in TCR_ELx
371 ubfx \tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3
372 mov \tmp1, #ID_AA64MMFR0_PARANGE_MAX
374 csel \tmp0, \tmp1, \tmp0, hi
375 bfi \tcr, \tmp0, \pos, #3
379 * Macro to perform a data cache maintenance for the interval
380 * [kaddr, kaddr + size)
382 * op: operation passed to dc instruction
383 * domain: domain used in dsb instruciton
384 * kaddr: starting virtual address of the region
385 * size: size of the region
386 * Corrupts: kaddr, size, tmp1, tmp2
388 .macro __dcache_op_workaround_clean_cache, op, kaddr
389 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
396 .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
397 dcache_line_size \tmp1, \tmp2
398 add \size, \kaddr, \size
400 bic \kaddr, \kaddr, \tmp2
403 __dcache_op_workaround_clean_cache \op, \kaddr
406 __dcache_op_workaround_clean_cache \op, \kaddr
409 sys 3, c7, c12, 1, \kaddr // dc cvap
412 sys 3, c7, c13, 1, \kaddr // dc cvadp
419 add \kaddr, \kaddr, \tmp1
426 * Macro to perform an instruction cache maintenance for the interval
429 * start, end: virtual addresses describing the region
430 * label: A label to branch to on user fault.
431 * Corrupts: tmp1, tmp2
433 .macro invalidate_icache_by_line start, end, tmp1, tmp2, label
434 icache_line_size \tmp1, \tmp2
436 bic \tmp2, \start, \tmp2
438 USER(\label, ic ivau, \tmp2) // invalidate I line PoU
439 add \tmp2, \tmp2, \tmp1
447 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
449 .macro reset_pmuserenr_el0, tmpreg
450 mrs \tmpreg, id_aa64dfr0_el1
451 sbfx \tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4
452 cmp \tmpreg, #1 // Skip if no PMU present
454 msr pmuserenr_el0, xzr // Disable PMU access from EL0
459 * reset_amuserenr_el0 - reset AMUSERENR_EL0 if AMUv1 present
461 .macro reset_amuserenr_el0, tmpreg
462 mrs \tmpreg, id_aa64pfr0_el1 // Check ID_AA64PFR0_EL1
463 ubfx \tmpreg, \tmpreg, #ID_AA64PFR0_AMU_SHIFT, #4
464 cbz \tmpreg, .Lskip_\@ // Skip if no AMU present
465 msr_s SYS_AMUSERENR_EL0, xzr // Disable AMU access from EL0
469 * copy_page - copy src to dest using temp registers t1-t8
471 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
472 9998: ldp \t1, \t2, [\src]
473 ldp \t3, \t4, [\src, #16]
474 ldp \t5, \t6, [\src, #32]
475 ldp \t7, \t8, [\src, #48]
477 stnp \t1, \t2, [\dest]
478 stnp \t3, \t4, [\dest, #16]
479 stnp \t5, \t6, [\dest, #32]
480 stnp \t7, \t8, [\dest, #48]
481 add \dest, \dest, #64
482 tst \src, #(PAGE_SIZE - 1)
487 * Annotate a function as being unsuitable for kprobes.
489 #ifdef CONFIG_KPROBES
490 #define NOKPROBE(x) \
491 .pushsection "_kprobe_blacklist", "aw"; \
498 #if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)
499 #define EXPORT_SYMBOL_NOKASAN(name)
501 #define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name)
505 * Emit a 64-bit absolute little endian symbol reference in a way that
506 * ensures that it will be resolved at build time, even when building a
507 * PIE binary. This requires cooperation from the linker script, which
508 * must emit the lo32/hi32 halves individually.
516 * mov_q - move an immediate constant into a 64-bit register using
517 * between 2 and 4 movz/movk instructions (depending on the
518 * magnitude and sign of the operand)
520 .macro mov_q, reg, val
521 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
522 movz \reg, :abs_g1_s:\val
524 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
525 movz \reg, :abs_g2_s:\val
527 movz \reg, :abs_g3:\val
528 movk \reg, :abs_g2_nc:\val
530 movk \reg, :abs_g1_nc:\val
532 movk \reg, :abs_g0_nc:\val
536 * Return the current task_struct.
538 .macro get_current_task, rd
543 * Offset ttbr1 to allow for 48-bit kernel VAs set with 52-bit PTRS_PER_PGD.
544 * orr is used as it can cover the immediate value (and is idempotent).
545 * In future this may be nop'ed out when dealing with 52-bit kernel VAs.
546 * ttbr: Value of ttbr to set, modified.
548 .macro offset_ttbr1, ttbr, tmp
549 #ifdef CONFIG_ARM64_VA_BITS_52
550 mrs_s \tmp, SYS_ID_AA64MMFR2_EL1
551 and \tmp, \tmp, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
552 cbnz \tmp, .Lskipoffs_\@
553 orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
559 * Perform the reverse of offset_ttbr1.
560 * bic is used as it can cover the immediate value and, in future, won't need
561 * to be nop'ed out when dealing with 52-bit kernel VAs.
563 .macro restore_ttbr1, ttbr
564 #ifdef CONFIG_ARM64_VA_BITS_52
565 bic \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
570 * Arrange a physical address in a TTBR register, taking care of 52-bit
573 * phys: physical address, preserved
574 * ttbr: returns the TTBR value
576 .macro phys_to_ttbr, ttbr, phys
577 #ifdef CONFIG_ARM64_PA_BITS_52
578 orr \ttbr, \phys, \phys, lsr #46
579 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
585 .macro phys_to_pte, pte, phys
586 #ifdef CONFIG_ARM64_PA_BITS_52
588 * We assume \phys is 64K aligned and this is guaranteed by only
589 * supporting this configuration with 64K pages.
591 orr \pte, \phys, \phys, lsr #36
592 and \pte, \pte, #PTE_ADDR_MASK
598 .macro pte_to_phys, phys, pte
599 #ifdef CONFIG_ARM64_PA_BITS_52
600 ubfiz \phys, \pte, #(48 - 16 - 12), #16
601 bfxil \phys, \pte, #16, #32
602 lsl \phys, \phys, #16
604 and \phys, \pte, #PTE_ADDR_MASK
609 * tcr_clear_errata_bits - Clear TCR bits that trigger an errata on this CPU.
611 .macro tcr_clear_errata_bits, tcr, tmp1, tmp2
612 #ifdef CONFIG_FUJITSU_ERRATUM_010001
615 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK
616 and \tmp1, \tmp1, \tmp2
617 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001
621 mov_q \tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001
622 bic \tcr, \tcr, \tmp2
624 #endif /* CONFIG_FUJITSU_ERRATUM_010001 */
628 * Errata workaround prior to disable MMU. Insert an ISB immediately prior
629 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
631 .macro pre_disable_mmu_workaround
632 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
638 * frame_push - Push @regcount callee saved registers to the stack,
639 * starting at x19, as well as x29/x30, and set x29 to
640 * the new value of sp. Add @extra bytes of stack space
643 .macro frame_push, regcount:req, extra
644 __frame st, \regcount, \extra
648 * frame_pop - Pop the callee saved registers from the stack that were
649 * pushed in the most recent call to frame_push, as well
650 * as x29/x30 and any extra stack space that may have been
657 .macro __frame_regs, reg1, reg2, op, num
658 .if .Lframe_regcount == \num
659 \op\()r \reg1, [sp, #(\num + 1) * 8]
660 .elseif .Lframe_regcount > \num
661 \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8]
665 .macro __frame, op, regcount, extra=0
667 .if (\regcount) < 0 || (\regcount) > 10
668 .error "regcount should be in the range [0 ... 10]"
670 .if ((\extra) % 16) != 0
671 .error "extra should be a multiple of 16 bytes"
673 .ifdef .Lframe_regcount
674 .if .Lframe_regcount != -1
675 .error "frame_push/frame_pop may not be nested"
678 .set .Lframe_regcount, \regcount
679 .set .Lframe_extra, \extra
680 .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16
681 stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]!
685 __frame_regs x19, x20, \op, 1
686 __frame_regs x21, x22, \op, 3
687 __frame_regs x23, x24, \op, 5
688 __frame_regs x25, x26, \op, 7
689 __frame_regs x27, x28, \op, 9
692 .if .Lframe_regcount == -1
693 .error "frame_push/frame_pop may not be nested"
695 ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra
696 .set .Lframe_regcount, -1
701 * Set SCTLR_ELx to the @reg value, and invalidate the local icache
702 * in the process. This is called when setting the MMU on.
704 .macro set_sctlr, sreg, reg
708 * Invalidate the local I-cache so that any instructions fetched
709 * speculatively from the PoC are discarded, since they may have
710 * been dynamically patched at the PoU.
717 .macro set_sctlr_el1, reg
718 set_sctlr sctlr_el1, \reg
721 .macro set_sctlr_el2, reg
722 set_sctlr sctlr_el2, \reg
726 * Check whether preempt/bh-disabled asm code should yield as soon as
727 * it is able. This is the case if we are currently running in task
728 * context, and either a softirq is pending, or the TIF_NEED_RESCHED
729 * flag is set and re-enabling preemption a single time would result in
730 * a preempt count of zero. (Note that the TIF_NEED_RESCHED flag is
731 * stored negated in the top word of the thread_info::preempt_count
734 .macro cond_yield, lbl:req, tmp:req, tmp2:req
735 get_current_task \tmp
736 ldr \tmp, [\tmp, #TSK_TI_PREEMPT]
738 * If we are serving a softirq, there is no point in yielding: the
739 * softirq will not be preempted no matter what we do, so we should
740 * run to completion as quickly as we can.
742 tbnz \tmp, #SOFTIRQ_SHIFT, .Lnoyield_\@
743 #ifdef CONFIG_PREEMPTION
744 sub \tmp, \tmp, #PREEMPT_DISABLE_OFFSET
747 adr_l \tmp, irq_stat + IRQ_CPUSTAT_SOFTIRQ_PENDING
748 this_cpu_offset \tmp2
749 ldr w\tmp, [\tmp, \tmp2]
750 cbnz w\tmp, \lbl // yield on pending softirq in task context
755 * This macro emits a program property note section identifying
756 * architecture features which require special handling, mainly for
757 * use in assembly files included in the VDSO.
760 #define NT_GNU_PROPERTY_TYPE_0 5
761 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
763 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)
764 #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1)
766 #ifdef CONFIG_ARM64_BTI_KERNEL
767 #define GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT \
768 ((GNU_PROPERTY_AARCH64_FEATURE_1_BTI | \
769 GNU_PROPERTY_AARCH64_FEATURE_1_PAC))
772 #ifdef GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT
773 .macro emit_aarch64_feature_1_and, feat=GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT
774 .pushsection .note.gnu.property, "a"
778 .long NT_GNU_PROPERTY_TYPE_0
782 3: .long GNU_PROPERTY_AARCH64_FEATURE_1_AND
786 * This is described with an array of char in the Linux API
787 * spec but the text and all other usage (including binutils,
788 * clang and GCC) treat this as a 32 bit value so no swizzling
789 * is required for big endian.
799 .macro emit_aarch64_feature_1_and, feat=0
802 #endif /* GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT */
804 #endif /* __ASM_ASSEMBLER_H */