2 * arch/arm64/include/asm/arch_gicv3.h
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __ASM_ARCH_GICV3_H
19 #define __ASM_ARCH_GICV3_H
21 #include <asm/sysreg.h>
25 #include <linux/irqchip/arm-gic-common.h>
26 #include <linux/stringify.h>
27 #include <asm/barrier.h>
28 #include <asm/cacheflush.h>
30 #define read_gicreg(r) read_sysreg_s(SYS_ ## r)
31 #define write_gicreg(v, r) write_sysreg_s(v, SYS_ ## r)
36 * These system registers are 32 bits, but we make sure that the compiler
37 * sets the GP register's most significant bits to 0 with an explicit cast.
40 static inline void gic_write_eoir(u32 irq)
42 write_sysreg_s(irq, SYS_ICC_EOIR1_EL1);
46 static inline void gic_write_dir(u32 irq)
48 write_sysreg_s(irq, SYS_ICC_DIR_EL1);
52 static inline u64 gic_read_iar_common(void)
56 irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
62 * Cavium ThunderX erratum 23154
64 * The gicv3 of ThunderX requires a modified version for reading the
65 * IAR status to ensure data synchronization (access to icc_iar1_el1
66 * is not sync'ed before and after).
68 static inline u64 gic_read_iar_cavium_thunderx(void)
73 irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
80 static inline void gic_write_ctlr(u32 val)
82 write_sysreg_s(val, SYS_ICC_CTLR_EL1);
86 static inline u32 gic_read_ctlr(void)
88 return read_sysreg_s(SYS_ICC_CTLR_EL1);
91 static inline void gic_write_grpen1(u32 val)
93 write_sysreg_s(val, SYS_ICC_IGRPEN1_EL1);
97 static inline void gic_write_sgi1r(u64 val)
99 write_sysreg_s(val, SYS_ICC_SGI1R_EL1);
102 static inline u32 gic_read_sre(void)
104 return read_sysreg_s(SYS_ICC_SRE_EL1);
107 static inline void gic_write_sre(u32 val)
109 write_sysreg_s(val, SYS_ICC_SRE_EL1);
113 static inline void gic_write_bpr1(u32 val)
115 write_sysreg_s(val, SYS_ICC_BPR1_EL1);
118 static inline u32 gic_read_pmr(void)
120 return read_sysreg_s(SYS_ICC_PMR_EL1);
123 static inline void gic_write_pmr(u32 val)
125 write_sysreg_s(val, SYS_ICC_PMR_EL1);
128 static inline u32 gic_read_rpr(void)
130 return read_sysreg_s(SYS_ICC_RPR_EL1);
133 #define gic_read_typer(c) readq_relaxed(c)
134 #define gic_write_irouter(v, c) writeq_relaxed(v, c)
135 #define gic_read_lpir(c) readq_relaxed(c)
136 #define gic_write_lpir(v, c) writeq_relaxed(v, c)
138 #define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
140 #define gits_read_baser(c) readq_relaxed(c)
141 #define gits_write_baser(v, c) writeq_relaxed(v, c)
143 #define gits_read_cbaser(c) readq_relaxed(c)
144 #define gits_write_cbaser(v, c) writeq_relaxed(v, c)
146 #define gits_write_cwriter(v, c) writeq_relaxed(v, c)
148 #define gicr_read_propbaser(c) readq_relaxed(c)
149 #define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
151 #define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
152 #define gicr_read_pendbaser(c) readq_relaxed(c)
154 #define gits_write_vpropbaser(v, c) writeq_relaxed(v, c)
156 #define gits_write_vpendbaser(v, c) writeq_relaxed(v, c)
157 #define gits_read_vpendbaser(c) readq_relaxed(c)
159 static inline bool gic_prio_masking_enabled(void)
161 return system_uses_irq_prio_masking();
164 static inline void gic_pmr_mask_irqs(void)
166 BUILD_BUG_ON(GICD_INT_DEF_PRI <= GIC_PRIO_IRQOFF);
167 gic_write_pmr(GIC_PRIO_IRQOFF);
170 static inline void gic_arch_enable_irqs(void)
172 asm volatile ("msr daifclr, #2" : : : "memory");
175 #endif /* __ASSEMBLY__ */
176 #endif /* __ASM_ARCH_GICV3_H */