1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
5 * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "k3-j784s4.dtsi"
15 compatible = "ti,j784s4-evm", "ti,j784s4";
16 model = "Texas Instruments J784S4 EVM";
19 stdout-path = "serial2:115200n8";
23 serial0 = &wkup_uart0;
25 serial2 = &main_uart8;
33 device_type = "memory";
36 reg = <0x00 0x80000000 0x00 0x80000000>,
37 <0x08 0x80000000 0x07 0x80000000>;
40 reserved_memory: reserved-memory {
45 secure_ddr: optee@9e800000 {
46 reg = <0x00 0x9e800000 0x00 0x01800000>;
50 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
51 compatible = "shared-dma-pool";
52 reg = <0x00 0xa0000000 0x00 0x100000>;
56 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
57 compatible = "shared-dma-pool";
58 reg = <0x00 0xa0100000 0x00 0xf00000>;
62 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
63 compatible = "shared-dma-pool";
64 reg = <0x00 0xa1000000 0x00 0x100000>;
68 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
69 compatible = "shared-dma-pool";
70 reg = <0x00 0xa1100000 0x00 0xf00000>;
74 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
75 compatible = "shared-dma-pool";
76 reg = <0x00 0xa2000000 0x00 0x100000>;
80 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
81 compatible = "shared-dma-pool";
82 reg = <0x00 0xa2100000 0x00 0xf00000>;
86 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
87 compatible = "shared-dma-pool";
88 reg = <0x00 0xa3000000 0x00 0x100000>;
92 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
93 compatible = "shared-dma-pool";
94 reg = <0x00 0xa3100000 0x00 0xf00000>;
98 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
99 compatible = "shared-dma-pool";
100 reg = <0x00 0xa4000000 0x00 0x100000>;
104 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
105 compatible = "shared-dma-pool";
106 reg = <0x00 0xa4100000 0x00 0xf00000>;
110 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
111 compatible = "shared-dma-pool";
112 reg = <0x00 0xa5000000 0x00 0x100000>;
116 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
117 compatible = "shared-dma-pool";
118 reg = <0x00 0xa5100000 0x00 0xf00000>;
122 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
123 compatible = "shared-dma-pool";
124 reg = <0x00 0xa6000000 0x00 0x100000>;
128 main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
129 compatible = "shared-dma-pool";
130 reg = <0x00 0xa6100000 0x00 0xf00000>;
134 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
135 compatible = "shared-dma-pool";
136 reg = <0x00 0xa7000000 0x00 0x100000>;
140 main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
141 compatible = "shared-dma-pool";
142 reg = <0x00 0xa7100000 0x00 0xf00000>;
146 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
147 compatible = "shared-dma-pool";
148 reg = <0x00 0xa8000000 0x00 0x100000>;
152 c71_0_memory_region: c71-memory@a8100000 {
153 compatible = "shared-dma-pool";
154 reg = <0x00 0xa8100000 0x00 0xf00000>;
158 c71_1_dma_memory_region: c71-dma-memory@a9000000 {
159 compatible = "shared-dma-pool";
160 reg = <0x00 0xa9000000 0x00 0x100000>;
164 c71_1_memory_region: c71-memory@a9100000 {
165 compatible = "shared-dma-pool";
166 reg = <0x00 0xa9100000 0x00 0xf00000>;
170 c71_2_dma_memory_region: c71-dma-memory@aa000000 {
171 compatible = "shared-dma-pool";
172 reg = <0x00 0xaa000000 0x00 0x100000>;
176 c71_2_memory_region: c71-memory@aa100000 {
177 compatible = "shared-dma-pool";
178 reg = <0x00 0xaa100000 0x00 0xf00000>;
182 c71_3_dma_memory_region: c71-dma-memory@ab000000 {
183 compatible = "shared-dma-pool";
184 reg = <0x00 0xab000000 0x00 0x100000>;
188 c71_3_memory_region: c71-memory@ab100000 {
189 compatible = "shared-dma-pool";
190 reg = <0x00 0xab100000 0x00 0xf00000>;
195 evm_12v0: regulator-evm12v0 {
197 compatible = "regulator-fixed";
198 regulator-name = "evm_12v0";
199 regulator-min-microvolt = <12000000>;
200 regulator-max-microvolt = <12000000>;
205 vsys_3v3: regulator-vsys3v3 {
206 /* Output of LM5140 */
207 compatible = "regulator-fixed";
208 regulator-name = "vsys_3v3";
209 regulator-min-microvolt = <3300000>;
210 regulator-max-microvolt = <3300000>;
211 vin-supply = <&evm_12v0>;
216 vsys_5v0: regulator-vsys5v0 {
217 /* Output of LM5140 */
218 compatible = "regulator-fixed";
219 regulator-name = "vsys_5v0";
220 regulator-min-microvolt = <5000000>;
221 regulator-max-microvolt = <5000000>;
222 vin-supply = <&evm_12v0>;
227 vdd_mmc1: regulator-sd {
228 /* Output of TPS22918 */
229 compatible = "regulator-fixed";
230 regulator-name = "vdd_mmc1";
231 regulator-min-microvolt = <3300000>;
232 regulator-max-microvolt = <3300000>;
235 vin-supply = <&vsys_3v3>;
236 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
239 vdd_sd_dv: regulator-TLV71033 {
240 /* Output of TLV71033 */
241 compatible = "regulator-gpio";
242 regulator-name = "tlv71033";
243 pinctrl-names = "default";
244 pinctrl-0 = <&vdd_sd_dv_pins_default>;
245 regulator-min-microvolt = <1800000>;
246 regulator-max-microvolt = <3300000>;
248 vin-supply = <&vsys_5v0>;
249 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
250 states = <1800000 0x0>,
254 dp0_pwr_3v3: regulator-dp0-prw {
255 compatible = "regulator-fixed";
256 regulator-name = "dp0-pwr";
257 regulator-min-microvolt = <3300000>;
258 regulator-max-microvolt = <3300000>;
259 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>;
264 compatible = "dp-connector";
267 dp-pwr-supply = <&dp0_pwr_3v3>;
270 dp0_connector_in: endpoint {
271 remote-endpoint = <&dp0_out>;
283 main_uart8_pins_default: main-uart8-default-pins {
285 pinctrl-single,pins = <
286 J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */
287 J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */
288 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
289 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
293 main_i2c0_pins_default: main-i2c0-default-pins {
294 pinctrl-single,pins = <
295 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */
296 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
300 main_i2c5_pins_default: main-i2c5-default-pins {
301 pinctrl-single,pins = <
302 J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */
303 J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */
307 main_mmc1_pins_default: main-mmc1-default-pins {
309 pinctrl-single,pins = <
310 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
311 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
312 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */
313 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */
314 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */
315 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */
316 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */
317 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
321 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
322 pinctrl-single,pins = <
323 J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
327 dp0_pins_default: dp0-default-pins {
328 pinctrl-single,pins = <
329 J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */
333 main_i2c4_pins_default: main-i2c4-default-pins {
334 pinctrl-single,pins = <
335 J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */
336 J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
343 wkup_uart0_pins_default: wkup-uart0-default-pins {
345 pinctrl-single,pins = <
346 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */
347 J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */
351 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
353 pinctrl-single,pins = <
354 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
355 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
359 mcu_uart0_pins_default: mcu-uart0-default-pins {
361 pinctrl-single,pins = <
362 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */
363 J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */
364 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */
365 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */
369 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
370 pinctrl-single,pins = <
371 J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
372 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
373 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
374 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
375 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
376 J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
377 J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
378 J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
379 J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
380 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
381 J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
382 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
386 mcu_mdio_pins_default: mcu-mdio-default-pins {
387 pinctrl-single,pins = <
388 J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
389 J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
393 mcu_adc0_pins_default: mcu-adc0-default-pins {
394 pinctrl-single,pins = <
395 J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */
396 J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */
397 J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */
398 J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */
399 J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */
400 J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */
401 J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */
402 J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */
406 mcu_adc1_pins_default: mcu-adc1-default-pins {
407 pinctrl-single,pins = <
408 J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */
409 J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */
410 J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */
411 J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */
412 J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */
413 J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */
414 J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */
415 J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */
423 pmic_irq_pins_default: pmic-irq-default-pins {
424 pinctrl-single,pins = <
425 /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */
426 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7)
433 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
435 pinctrl-single,pins = <
436 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */
437 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */
438 J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */
439 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */
440 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */
441 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */
442 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */
443 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */
444 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */
445 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */
446 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */
453 mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins {
455 pinctrl-single,pins = <
456 J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */
457 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */
461 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
463 pinctrl-single,pins = <
464 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */
465 J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */
466 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */
467 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */
468 J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */
469 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */
470 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */
471 J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */
479 pinctrl-names = "default";
480 pinctrl-0 = <&wkup_uart0_pins_default>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&wkup_i2c0_pins_default>;
488 clock-frequency = <400000>;
491 /* CAV24C256WE-GT3 */
492 compatible = "atmel,24c256";
497 compatible = "ti,tps6594-q1";
499 system-power-controller;
500 pinctrl-names = "default";
501 pinctrl-0 = <&pmic_irq_pins_default>;
502 interrupt-parent = <&wkup_gpio0>;
503 interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
507 buck12-supply = <&vsys_3v3>;
508 buck3-supply = <&vsys_3v3>;
509 buck4-supply = <&vsys_3v3>;
510 buck5-supply = <&vsys_3v3>;
511 ldo1-supply = <&vsys_3v3>;
512 ldo2-supply = <&vsys_3v3>;
513 ldo3-supply = <&vsys_3v3>;
514 ldo4-supply = <&vsys_3v3>;
518 regulator-name = "vdd_ddr_1v1";
519 regulator-min-microvolt = <1100000>;
520 regulator-max-microvolt = <1100000>;
526 regulator-name = "vdd_ram_0v85";
527 regulator-min-microvolt = <850000>;
528 regulator-max-microvolt = <850000>;
534 regulator-name = "vdd_io_1v8";
535 regulator-min-microvolt = <1800000>;
536 regulator-max-microvolt = <1800000>;
542 regulator-name = "vdd_mcu_0v85";
543 regulator-min-microvolt = <850000>;
544 regulator-max-microvolt = <850000>;
550 regulator-name = "vdd_mcuio_1v8";
551 regulator-min-microvolt = <1800000>;
552 regulator-max-microvolt = <1800000>;
558 regulator-name = "vdd_mcuio_3v3";
559 regulator-min-microvolt = <3300000>;
560 regulator-max-microvolt = <3300000>;
566 regulator-name = "vds_dll_0v8";
567 regulator-min-microvolt = <800000>;
568 regulator-max-microvolt = <800000>;
574 regulator-name = "vda_mcu_1v8";
575 regulator-min-microvolt = <1800000>;
576 regulator-max-microvolt = <1800000>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&mcu_uart0_pins_default>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&main_uart8_pins_default>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>;
615 compatible = "jedec,spi-nor";
617 spi-tx-bus-width = <8>;
618 spi-rx-bus-width = <8>;
619 spi-max-frequency = <25000000>;
620 cdns,tshsl-ns = <60>;
621 cdns,tsd2d-ns = <60>;
622 cdns,tchsh-ns = <60>;
623 cdns,tslch-ns = <60>;
624 cdns,read-delay = <4>;
627 compatible = "fixed-partitions";
628 #address-cells = <1>;
632 label = "ospi.tiboot3";
637 label = "ospi.tispl";
638 reg = <0x80000 0x200000>;
642 label = "ospi.u-boot";
643 reg = <0x280000 0x400000>;
648 reg = <0x680000 0x40000>;
652 label = "ospi.env.backup";
653 reg = <0x6c0000 0x40000>;
657 label = "ospi.rootfs";
658 reg = <0x800000 0x37c0000>;
663 label = "ospi.phypattern";
664 reg = <0x3fc0000 0x40000>;
673 pinctrl-names = "default";
674 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
678 compatible = "jedec,spi-nor";
680 spi-tx-bus-width = <1>;
681 spi-rx-bus-width = <4>;
682 spi-max-frequency = <40000000>;
683 cdns,tshsl-ns = <60>;
684 cdns,tsd2d-ns = <60>;
685 cdns,tchsh-ns = <60>;
686 cdns,tslch-ns = <60>;
687 cdns,read-delay = <2>;
690 compatible = "fixed-partitions";
691 #address-cells = <1>;
695 label = "qspi.tiboot3";
700 label = "qspi.tispl";
701 reg = <0x80000 0x200000>;
705 label = "qspi.u-boot";
706 reg = <0x280000 0x400000>;
711 reg = <0x680000 0x40000>;
715 label = "qspi.env.backup";
716 reg = <0x6c0000 0x40000>;
720 label = "qspi.rootfs";
721 reg = <0x800000 0x37c0000>;
726 label = "qspi.phypattern";
727 reg = <0x3fc0000 0x40000>;
736 pinctrl-names = "default";
737 pinctrl-0 = <&main_i2c0_pins_default>;
739 clock-frequency = <400000>;
742 compatible = "ti,tca6416";
746 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ",
747 "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ",
748 "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#",
749 "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3",
750 "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ";
754 compatible = "ti,tca6424";
758 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN",
759 "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0",
760 "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#",
761 "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ",
762 "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1",
763 "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ",
764 "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ",
765 "USER_INPUT1", "USER_LED1", "USER_LED2";
770 pinctrl-names = "default";
771 pinctrl-0 = <&main_i2c5_pins_default>;
772 clock-frequency = <400000>;
776 compatible = "ti,tca6408";
780 gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0",
781 "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3",
782 "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2",
783 "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4";
792 ti,driver-strength-ohm = <50>;
800 pinctrl-0 = <&main_mmc1_pins_default>;
801 pinctrl-names = "default";
803 vmmc-supply = <&vdd_mmc1>;
804 vqmmc-supply = <&vdd_sd_dv>;
813 pinctrl-names = "default";
814 pinctrl-0 = <&mcu_cpsw_pins_default>;
818 pinctrl-names = "default";
819 pinctrl-0 = <&mcu_mdio_pins_default>;
821 mcu_phy0: ethernet-phy@0 {
823 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
824 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
825 ti,min-output-impedance;
831 phy-mode = "rgmii-rxid";
832 phy-handle = <&mcu_phy0>;
839 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
840 ti,mbox-rx = <0 0 0>;
841 ti,mbox-tx = <1 0 0>;
844 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
845 ti,mbox-rx = <2 0 0>;
846 ti,mbox-tx = <3 0 0>;
854 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
855 ti,mbox-rx = <0 0 0>;
856 ti,mbox-tx = <1 0 0>;
859 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
860 ti,mbox-rx = <2 0 0>;
861 ti,mbox-tx = <3 0 0>;
869 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
870 ti,mbox-rx = <0 0 0>;
871 ti,mbox-tx = <1 0 0>;
874 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
875 ti,mbox-rx = <2 0 0>;
876 ti,mbox-tx = <3 0 0>;
884 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
885 ti,mbox-rx = <0 0 0>;
886 ti,mbox-tx = <1 0 0>;
889 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
890 ti,mbox-rx = <2 0 0>;
891 ti,mbox-tx = <3 0 0>;
899 mbox_c71_0: mbox-c71-0 {
900 ti,mbox-rx = <0 0 0>;
901 ti,mbox-tx = <1 0 0>;
904 mbox_c71_1: mbox-c71-1 {
905 ti,mbox-rx = <2 0 0>;
906 ti,mbox-tx = <3 0 0>;
914 mbox_c71_2: mbox-c71-2 {
915 ti,mbox-rx = <0 0 0>;
916 ti,mbox-tx = <1 0 0>;
919 mbox_c71_3: mbox-c71-3 {
920 ti,mbox-rx = <2 0 0>;
921 ti,mbox-tx = <3 0 0>;
927 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
928 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
929 <&mcu_r5fss0_core0_memory_region>;
934 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
935 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
936 <&mcu_r5fss0_core1_memory_region>;
941 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
942 memory-region = <&main_r5fss0_core0_dma_memory_region>,
943 <&main_r5fss0_core0_memory_region>;
948 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
949 memory-region = <&main_r5fss0_core1_dma_memory_region>,
950 <&main_r5fss0_core1_memory_region>;
955 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
956 memory-region = <&main_r5fss1_core0_dma_memory_region>,
957 <&main_r5fss1_core0_memory_region>;
962 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
963 memory-region = <&main_r5fss1_core1_dma_memory_region>,
964 <&main_r5fss1_core1_memory_region>;
969 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>;
970 memory-region = <&main_r5fss2_core0_dma_memory_region>,
971 <&main_r5fss2_core0_memory_region>;
976 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>;
977 memory-region = <&main_r5fss2_core1_dma_memory_region>,
978 <&main_r5fss2_core1_memory_region>;
983 mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
984 memory-region = <&c71_0_dma_memory_region>,
985 <&c71_0_memory_region>;
990 mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
991 memory-region = <&c71_1_dma_memory_region>,
992 <&c71_1_memory_region>;
997 mboxes = <&mailbox0_cluster5 &mbox_c71_2>;
998 memory-region = <&c71_2_dma_memory_region>,
999 <&c71_2_memory_region>;
1004 mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
1005 memory-region = <&c71_3_dma_memory_region>,
1006 <&c71_3_memory_region>;
1010 pinctrl-0 = <&mcu_adc0_pins_default>;
1011 pinctrl-names = "default";
1014 ti,adc-channels = <0 1 2 3 4 5 6 7>;
1019 pinctrl-0 = <&mcu_adc1_pins_default>;
1020 pinctrl-names = "default";
1023 ti,adc-channels = <0 1 2 3 4 5 6 7>;
1029 clock-frequency = <100000000>;
1034 assigned-clocks = <&k3_clks 218 2>,
1038 assigned-clock-parents = <&k3_clks 218 3>,
1050 serdes4_dp_link: phy@0 {
1052 cdns,num-lanes = <4>;
1054 cdns,phy-type = <PHY_TYPE_DP>;
1055 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
1056 <&serdes_wiz4 3>, <&serdes_wiz4 4>;
1062 pinctrl-names = "default";
1063 pinctrl-0 = <&dp0_pins_default>;
1064 phys = <&serdes4_dp_link>;
1065 phy-names = "dpphy";
1071 dpi0_out: endpoint {
1072 remote-endpoint = <&dp0_in>;
1079 pinctrl-names = "default";
1080 pinctrl-0 = <&main_i2c4_pins_default>;
1081 clock-frequency = <400000>;
1084 compatible = "ti,tca6408";
1096 remote-endpoint = <&dpi0_out>;
1104 remote-endpoint = <&dp0_connector_in>;