arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J721S2 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_main {
   9         msmc_ram: sram@70000000 {
  10                 compatible = "mmio-sram";
  11                 reg = <0x0 0x70000000 0x0 0x400000>;
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 ranges = <0x0 0x0 0x70000000 0x400000>;
  15
  16                 atf-sram@0 {
  17                         reg = <0x0 0x20000>;
  18                 };
  19
  20                 tifs-sram@1f0000 {
  21                         reg = <0x1f0000 0x10000>;
  22                 };
  23
  24                 l3cache-sram@200000 {
  25                         reg = <0x200000 0x200000>;
  26                 };
  27         };
  28
  29         gic500: interrupt-controller@1800000 {
  30                 compatible = "arm,gic-v3";
  31                 #address-cells = <2>;
  32                 #size-cells = <2>;
  33                 ranges;
  34                 #interrupt-cells = <3>;
  35                 interrupt-controller;
  36                 reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
  37                       <0x00 0x01900000 0x00 0x100000>, /* GICR */
  38                       <0x00 0x6f000000 0x00 0x2000>,   /* GICC */
  39                       <0x00 0x6f010000 0x00 0x1000>,   /* GICH */
  40                       <0x00 0x6f020000 0x00 0x2000>;   /* GICV */
  41
  42                 /* vcpumntirq: virtual CPU interface maintenance interrupt */
  43                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  44
  45                 gic_its: msi-controller@1820000 {
  46                         compatible = "arm,gic-v3-its";
  47                         reg = <0x00 0x01820000 0x00 0x10000>;
  48                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  49                         msi-controller;
  50                         #msi-cells = <1>;
  51                 };
  52         };
  53
  54         main_gpio_intr: interrupt-controller@a00000 {
  55                 compatible = "ti,sci-intr";
  56                 reg = <0x00 0x00a00000 0x00 0x800>;
  57                 ti,intr-trigger-type = <1>;
  58                 interrupt-controller;
  59                 interrupt-parent = <&gic500>;
  60                 #interrupt-cells = <1>;
  61                 ti,sci = <&sms>;
  62                 ti,sci-dev-id = <148>;
  63                 ti,interrupt-ranges = <8 360 56>;
  64         };
  65
  66         main_pmx0: pinctrl@11c000 {
  67                 compatible = "pinctrl-single";
  68                 /* Proxy 0 addressing */
  69                 reg = <0x0 0x11c000 0x0 0x120>;
  70                 #pinctrl-cells = <1>;
  71                 pinctrl-single,register-width = <32>;
  72                 pinctrl-single,function-mask = <0xffffffff>;
  73         };
  74
  75         main_uart0: serial@2800000 {
  76                 compatible = "ti,j721e-uart", "ti,am654-uart";
  77                 reg = <0x00 0x02800000 0x00 0x200>;
  78                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
  79                 current-speed = <115200>;
  80                 clocks = <&k3_clks 146 3>;
  81                 clock-names = "fclk";
  82                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
  83         };
  84
  85         main_uart1: serial@2810000 {
  86                 compatible = "ti,j721e-uart", "ti,am654-uart";
  87                 reg = <0x00 0x02810000 0x00 0x200>;
  88                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
  89                 current-speed = <115200>;
  90                 clocks = <&k3_clks 350 3>;
  91                 clock-names = "fclk";
  92                 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
  93         };
  94
  95         main_uart2: serial@2820000 {
  96                 compatible = "ti,j721e-uart", "ti,am654-uart";
  97                 reg = <0x00 0x02820000 0x00 0x200>;
  98                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  99                 current-speed = <115200>;
 100                 clocks = <&k3_clks 351 3>;
 101                 clock-names = "fclk";
 102                 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
 103         };
 104
 105         main_uart3: serial@2830000 {
 106                 compatible = "ti,j721e-uart", "ti,am654-uart";
 107                 reg = <0x00 0x02830000 0x00 0x200>;
 108                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 109                 current-speed = <115200>;
 110                 clocks = <&k3_clks 352 3>;
 111                 clock-names = "fclk";
 112                 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
 113         };
 114
 115         main_uart4: serial@2840000 {
 116                 compatible = "ti,j721e-uart", "ti,am654-uart";
 117                 reg = <0x00 0x02840000 0x00 0x200>;
 118                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 119                 current-speed = <115200>;
 120                 clocks = <&k3_clks 353 3>;
 121                 clock-names = "fclk";
 122                 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
 123         };
 124
 125         main_uart5: serial@2850000 {
 126                 compatible = "ti,j721e-uart", "ti,am654-uart";
 127                 reg = <0x00 0x02850000 0x00 0x200>;
 128                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 129                 current-speed = <115200>;
 130                 clocks = <&k3_clks 354 3>;
 131                 clock-names = "fclk";
 132                 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
 133         };
 134
 135         main_uart6: serial@2860000 {
 136                 compatible = "ti,j721e-uart", "ti,am654-uart";
 137                 reg = <0x00 0x02860000 0x00 0x200>;
 138                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 139                 current-speed = <115200>;
 140                 clocks = <&k3_clks 355 3>;
 141                 clock-names = "fclk";
 142                 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
 143         };
 144
 145         main_uart7: serial@2870000 {
 146                 compatible = "ti,j721e-uart", "ti,am654-uart";
 147                 reg = <0x00 0x02870000 0x00 0x200>;
 148                 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 149                 current-speed = <115200>;
 150                 clocks = <&k3_clks 356 3>;
 151                 clock-names = "fclk";
 152                 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
 153         };
 154
 155         main_uart8: serial@2880000 {
 156                 compatible = "ti,j721e-uart", "ti,am654-uart";
 157                 reg = <0x00 0x02880000 0x00 0x200>;
 158                 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 159                 current-speed = <115200>;
 160                 clocks = <&k3_clks 357 3>;
 161                 clock-names = "fclk";
 162                 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
 163         };
 164
 165         main_uart9: serial@2890000 {
 166                 compatible = "ti,j721e-uart", "ti,am654-uart";
 167                 reg = <0x00 0x02890000 0x00 0x200>;
 168                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 169                 current-speed = <115200>;
 170                 clocks = <&k3_clks 358 3>;
 171                 clock-names = "fclk";
 172                 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
 173         };
 174
 175         main_gpio0: gpio@600000 {
 176                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 177                 reg = <0x00 0x00600000 0x00 0x100>;
 178                 gpio-controller;
 179                 #gpio-cells = <2>;
 180                 interrupt-parent = <&main_gpio_intr>;
 181                 interrupts = <145>, <146>, <147>, <148>, <149>;
 182                 interrupt-controller;
 183                 #interrupt-cells = <2>;
 184                 ti,ngpio = <66>;
 185                 ti,davinci-gpio-unbanked = <0>;
 186                 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
 187                 clocks = <&k3_clks 111 0>;
 188                 clock-names = "gpio";
 189         };
 190
 191         main_gpio2: gpio@610000 {
 192                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 193                 reg = <0x00 0x00610000 0x00 0x100>;
 194                 gpio-controller;
 195                 #gpio-cells = <2>;
 196                 interrupt-parent = <&main_gpio_intr>;
 197                 interrupts = <154>, <155>, <156>, <157>, <158>;
 198                 interrupt-controller;
 199                 #interrupt-cells = <2>;
 200                 ti,ngpio = <66>;
 201                 ti,davinci-gpio-unbanked = <0>;
 202                 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
 203                 clocks = <&k3_clks 112 0>;
 204                 clock-names = "gpio";
 205         };
 206
 207         main_gpio4: gpio@620000 {
 208                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 209                 reg = <0x00 0x00620000 0x00 0x100>;
 210                 gpio-controller;
 211                 #gpio-cells = <2>;
 212                 interrupt-parent = <&main_gpio_intr>;
 213                 interrupts = <163>, <164>, <165>, <166>, <167>;
 214                 interrupt-controller;
 215                 #interrupt-cells = <2>;
 216                 ti,ngpio = <66>;
 217                 ti,davinci-gpio-unbanked = <0>;
 218                 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
 219                 clocks = <&k3_clks 113 0>;
 220                 clock-names = "gpio";
 221         };
 222
 223         main_gpio6: gpio@630000 {
 224                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 225                 reg = <0x00 0x00630000 0x00 0x100>;
 226                 gpio-controller;
 227                 #gpio-cells = <2>;
 228                 interrupt-parent = <&main_gpio_intr>;
 229                 interrupts = <172>, <173>, <174>, <175>, <176>;
 230                 interrupt-controller;
 231                 #interrupt-cells = <2>;
 232                 ti,ngpio = <66>;
 233                 ti,davinci-gpio-unbanked = <0>;
 234                 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
 235                 clocks = <&k3_clks 114 0>;
 236                 clock-names = "gpio";
 237         };
 238
 239         main_i2c0: i2c@2000000 {
 240                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 241                 reg = <0x00 0x02000000 0x00 0x100>;
 242                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 243                 #address-cells = <1>;
 244                 #size-cells = <0>;
 245                 clocks = <&k3_clks 214 1>;
 246                 clock-names = "fck";
 247                 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
 248         };
 249
 250         main_i2c1: i2c@2010000 {
 251                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 252                 reg = <0x00 0x02010000 0x00 0x100>;
 253                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 254                 #address-cells = <1>;
 255                 #size-cells = <0>;
 256                 clocks = <&k3_clks 215 1>;
 257                 clock-names = "fck";
 258                 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
 259         };
 260
 261         main_i2c2: i2c@2020000 {
 262                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 263                 reg = <0x00 0x02020000 0x00 0x100>;
 264                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 265                 #address-cells = <1>;
 266                 #size-cells = <0>;
 267                 clocks = <&k3_clks 216 1>;
 268                 clock-names = "fck";
 269                 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
 270         };
 271
 272         main_i2c3: i2c@2030000 {
 273                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 274                 reg = <0x00 0x02030000 0x00 0x100>;
 275                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 276                 #address-cells = <1>;
 277                 #size-cells = <0>;
 278                 clocks = <&k3_clks 217 1>;
 279                 clock-names = "fck";
 280                 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
 281         };
 282
 283         main_i2c4: i2c@2040000 {
 284                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 285                 reg = <0x00 0x02040000 0x00 0x100>;
 286                 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 287                 #address-cells = <1>;
 288                 #size-cells = <0>;
 289                 clocks = <&k3_clks 218 1>;
 290                 clock-names = "fck";
 291                 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
 292         };
 293
 294         main_i2c5: i2c@2050000 {
 295                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 296                 reg = <0x00 0x02050000 0x00 0x100>;
 297                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 298                 #address-cells = <1>;
 299                 #size-cells = <0>;
 300                 clocks = <&k3_clks 219 1>;
 301                 clock-names = "fck";
 302                 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
 303         };
 304
 305         main_i2c6: i2c@2060000 {
 306                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 307                 reg = <0x00 0x02060000 0x00 0x100>;
 308                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 309                 #address-cells = <1>;
 310                 #size-cells = <0>;
 311                 clocks = <&k3_clks 220 1>;
 312                 clock-names = "fck";
 313                 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
 314         };
 315
 316         main_sdhci0: mmc@4f80000 {
 317                 compatible = "ti,j721e-sdhci-8bit";
 318                 reg = <0x00 0x04f80000 0x00 0x1000>,
 319                       <0x00 0x04f88000 0x00 0x400>;
 320                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 321                 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
 322                 clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
 323                 clock-names = "clk_ahb", "clk_xin";
 324                 assigned-clocks = <&k3_clks 98 1>;
 325                 assigned-clock-parents = <&k3_clks 98 2>;
 326                 bus-width = <8>;
 327                 ti,otap-del-sel-legacy = <0x0>;
 328                 ti,otap-del-sel-mmc-hs = <0x0>;
 329                 ti,otap-del-sel-ddr52 = <0x6>;
 330                 ti,otap-del-sel-hs200 = <0x8>;
 331                 ti,otap-del-sel-hs400 = <0x5>;
 332                 ti,itap-del-sel-legacy = <0x10>;
 333                 ti,itap-del-sel-mmc-hs = <0xa>;
 334                 ti,strobe-sel = <0x77>;
 335                 ti,clkbuf-sel = <0x7>;
 336                 ti,trm-icp = <0x8>;
 337                 mmc-ddr-1_8v;
 338                 mmc-hs200-1_8v;
 339                 mmc-hs400-1_8v;
 340                 dma-coherent;
 341         };
 342
 343         main_sdhci1: mmc@4fb0000 {
 344                 compatible = "ti,j721e-sdhci-4bit";
 345                 reg = <0x00 0x04fb0000 0x00 0x1000>,
 346                       <0x00 0x04fb8000 0x00 0x400>;
 347                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 348                 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
 349                 clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
 350                 clock-names = "clk_ahb", "clk_xin";
 351                 assigned-clocks = <&k3_clks 99 1>;
 352                 assigned-clock-parents = <&k3_clks 99 2>;
 353                 bus-width = <4>;
 354                 ti,otap-del-sel-legacy = <0x0>;
 355                 ti,otap-del-sel-sd-hs = <0x0>;
 356                 ti,otap-del-sel-sdr12 = <0xf>;
 357                 ti,otap-del-sel-sdr25 = <0xf>;
 358                 ti,otap-del-sel-sdr50 = <0xc>;
 359                 ti,otap-del-sel-sdr104 = <0x5>;
 360                 ti,otap-del-sel-ddr50 = <0xc>;
 361                 ti,itap-del-sel-legacy = <0x0>;
 362                 ti,itap-del-sel-sd-hs = <0x0>;
 363                 ti,itap-del-sel-sdr12 = <0x0>;
 364                 ti,itap-del-sel-sdr25 = <0x0>;
 365                 ti,clkbuf-sel = <0x7>;
 366                 ti,trm-icp = <0x8>;
 367                 dma-coherent;
 368                 /* Masking support for SDR104 capability */
 369                 sdhci-caps-mask = <0x00000003 0x00000000>;
 370         };
 371
 372         main_navss: bus@30000000 {
 373                 compatible = "simple-mfd";
 374                 #address-cells = <2>;
 375                 #size-cells = <2>;
 376                 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
 377                 ti,sci-dev-id = <224>;
 378                 dma-coherent;
 379                 dma-ranges;
 380
 381                 main_navss_intr: interrupt-controller@310e0000 {
 382                         compatible = "ti,sci-intr";
 383                         reg = <0x00 0x310e0000 0x00 0x4000>;
 384                         ti,intr-trigger-type = <4>;
 385                         interrupt-controller;
 386                         interrupt-parent = <&gic500>;
 387                         #interrupt-cells = <1>;
 388                         ti,sci = <&sms>;
 389                         ti,sci-dev-id = <227>;
 390                         ti,interrupt-ranges = <0 64 64>,
 391                                               <64 448 64>,
 392                                               <128 672 64>;
 393                 };
 394
 395                 main_udmass_inta: msi-controller@33d00000 {
 396                         compatible = "ti,sci-inta";
 397                         reg = <0x00 0x33d00000 0x00 0x100000>;
 398                         interrupt-controller;
 399                         #interrupt-cells = <0>;
 400                         interrupt-parent = <&main_navss_intr>;
 401                         msi-controller;
 402                         ti,sci = <&sms>;
 403                         ti,sci-dev-id = <265>;
 404                         ti,interrupt-ranges = <0 0 256>;
 405                 };
 406
 407                 secure_proxy_main: mailbox@32c00000 {
 408                         compatible = "ti,am654-secure-proxy";
 409                         #mbox-cells = <1>;
 410                         reg-names = "target_data", "rt", "scfg";
 411                         reg = <0x00 0x32c00000 0x00 0x100000>,
 412                               <0x00 0x32400000 0x00 0x100000>,
 413                               <0x00 0x32800000 0x00 0x100000>;
 414                         interrupt-names = "rx_011";
 415                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 416                 };
 417
 418                 hwspinlock: spinlock@30e00000 {
 419                         compatible = "ti,am654-hwspinlock";
 420                         reg = <0x00 0x30e00000 0x00 0x1000>;
 421                         #hwlock-cells = <1>;
 422                 };
 423
 424                 mailbox0_cluster0: mailbox@31f80000 {
 425                         compatible = "ti,am654-mailbox";
 426                         reg = <0x00 0x31f80000 0x00 0x200>;
 427                         #mbox-cells = <1>;
 428                         ti,mbox-num-users = <4>;
 429                         ti,mbox-num-fifos = <16>;
 430                         interrupt-parent = <&main_navss_intr>;
 431                 };
 432
 433                 mailbox0_cluster1: mailbox@31f81000 {
 434                         compatible = "ti,am654-mailbox";
 435                         reg = <0x00 0x31f81000 0x00 0x200>;
 436                         #mbox-cells = <1>;
 437                         ti,mbox-num-users = <4>;
 438                         ti,mbox-num-fifos = <16>;
 439                         interrupt-parent = <&main_navss_intr>;
 440                 };
 441
 442                 mailbox0_cluster2: mailbox@31f82000 {
 443                         compatible = "ti,am654-mailbox";
 444                         reg = <0x00 0x31f82000 0x00 0x200>;
 445                         #mbox-cells = <1>;
 446                         ti,mbox-num-users = <4>;
 447                         ti,mbox-num-fifos = <16>;
 448                         interrupt-parent = <&main_navss_intr>;
 449                 };
 450
 451                 mailbox0_cluster3: mailbox@31f83000 {
 452                         compatible = "ti,am654-mailbox";
 453                         reg = <0x00 0x31f83000 0x00 0x200>;
 454                         #mbox-cells = <1>;
 455                         ti,mbox-num-users = <4>;
 456                         ti,mbox-num-fifos = <16>;
 457                         interrupt-parent = <&main_navss_intr>;
 458                 };
 459
 460                 mailbox0_cluster4: mailbox@31f84000 {
 461                         compatible = "ti,am654-mailbox";
 462                         reg = <0x00 0x31f84000 0x00 0x200>;
 463                         #mbox-cells = <1>;
 464                         ti,mbox-num-users = <4>;
 465                         ti,mbox-num-fifos = <16>;
 466                         interrupt-parent = <&main_navss_intr>;
 467                 };
 468
 469                 mailbox0_cluster5: mailbox@31f85000 {
 470                         compatible = "ti,am654-mailbox";
 471                         reg = <0x00 0x31f85000 0x00 0x200>;
 472                         #mbox-cells = <1>;
 473                         ti,mbox-num-users = <4>;
 474                         ti,mbox-num-fifos = <16>;
 475                         interrupt-parent = <&main_navss_intr>;
 476                 };
 477
 478                 mailbox0_cluster6: mailbox@31f86000 {
 479                         compatible = "ti,am654-mailbox";
 480                         reg = <0x00 0x31f86000 0x00 0x200>;
 481                         #mbox-cells = <1>;
 482                         ti,mbox-num-users = <4>;
 483                         ti,mbox-num-fifos = <16>;
 484                         interrupt-parent = <&main_navss_intr>;
 485                 };
 486
 487                 mailbox0_cluster7: mailbox@31f87000 {
 488                         compatible = "ti,am654-mailbox";
 489                         reg = <0x00 0x31f87000 0x00 0x200>;
 490                         #mbox-cells = <1>;
 491                         ti,mbox-num-users = <4>;
 492                         ti,mbox-num-fifos = <16>;
 493                         interrupt-parent = <&main_navss_intr>;
 494                 };
 495
 496                 mailbox0_cluster8: mailbox@31f88000 {
 497                         compatible = "ti,am654-mailbox";
 498                         reg = <0x00 0x31f88000 0x00 0x200>;
 499                         #mbox-cells = <1>;
 500                         ti,mbox-num-users = <4>;
 501                         ti,mbox-num-fifos = <16>;
 502                         interrupt-parent = <&main_navss_intr>;
 503                 };
 504
 505                 mailbox0_cluster9: mailbox@31f89000 {
 506                         compatible = "ti,am654-mailbox";
 507                         reg = <0x00 0x31f89000 0x00 0x200>;
 508                         #mbox-cells = <1>;
 509                         ti,mbox-num-users = <4>;
 510                         ti,mbox-num-fifos = <16>;
 511                         interrupt-parent = <&main_navss_intr>;
 512                 };
 513
 514                 mailbox0_cluster10: mailbox@31f8a000 {
 515                         compatible = "ti,am654-mailbox";
 516                         reg = <0x00 0x31f8a000 0x00 0x200>;
 517                         #mbox-cells = <1>;
 518                         ti,mbox-num-users = <4>;
 519                         ti,mbox-num-fifos = <16>;
 520                         interrupt-parent = <&main_navss_intr>;
 521                 };
 522
 523                 mailbox0_cluster11: mailbox@31f8b000 {
 524                         compatible = "ti,am654-mailbox";
 525                         reg = <0x00 0x31f8b000 0x00 0x200>;
 526                         #mbox-cells = <1>;
 527                         ti,mbox-num-users = <4>;
 528                         ti,mbox-num-fifos = <16>;
 529                         interrupt-parent = <&main_navss_intr>;
 530                 };
 531
 532                 mailbox1_cluster0: mailbox@31f90000 {
 533                         compatible = "ti,am654-mailbox";
 534                         reg = <0x00 0x31f90000 0x00 0x200>;
 535                         #mbox-cells = <1>;
 536                         ti,mbox-num-users = <4>;
 537                         ti,mbox-num-fifos = <16>;
 538                         interrupt-parent = <&main_navss_intr>;
 539                 };
 540
 541                 mailbox1_cluster1: mailbox@31f91000 {
 542                         compatible = "ti,am654-mailbox";
 543                         reg = <0x00 0x31f91000 0x00 0x200>;
 544                         #mbox-cells = <1>;
 545                         ti,mbox-num-users = <4>;
 546                         ti,mbox-num-fifos = <16>;
 547                         interrupt-parent = <&main_navss_intr>;
 548                 };
 549
 550                 mailbox1_cluster2: mailbox@31f92000 {
 551                         compatible = "ti,am654-mailbox";
 552                         reg = <0x00 0x31f92000 0x00 0x200>;
 553                         #mbox-cells = <1>;
 554                         ti,mbox-num-users = <4>;
 555                         ti,mbox-num-fifos = <16>;
 556                         interrupt-parent = <&main_navss_intr>;
 557                 };
 558
 559                 mailbox1_cluster3: mailbox@31f93000 {
 560                         compatible = "ti,am654-mailbox";
 561                         reg = <0x00 0x31f93000 0x00 0x200>;
 562                         #mbox-cells = <1>;
 563                         ti,mbox-num-users = <4>;
 564                         ti,mbox-num-fifos = <16>;
 565                         interrupt-parent = <&main_navss_intr>;
 566                 };
 567
 568                 mailbox1_cluster4: mailbox@31f94000 {
 569                         compatible = "ti,am654-mailbox";
 570                         reg = <0x00 0x31f94000 0x00 0x200>;
 571                         #mbox-cells = <1>;
 572                         ti,mbox-num-users = <4>;
 573                         ti,mbox-num-fifos = <16>;
 574                         interrupt-parent = <&main_navss_intr>;
 575                 };
 576
 577                 mailbox1_cluster5: mailbox@31f95000 {
 578                         compatible = "ti,am654-mailbox";
 579                         reg = <0x00 0x31f95000 0x00 0x200>;
 580                         #mbox-cells = <1>;
 581                         ti,mbox-num-users = <4>;
 582                         ti,mbox-num-fifos = <16>;
 583                         interrupt-parent = <&main_navss_intr>;
 584                 };
 585
 586                 mailbox1_cluster6: mailbox@31f96000 {
 587                         compatible = "ti,am654-mailbox";
 588                         reg = <0x00 0x31f96000 0x00 0x200>;
 589                         #mbox-cells = <1>;
 590                         ti,mbox-num-users = <4>;
 591                         ti,mbox-num-fifos = <16>;
 592                         interrupt-parent = <&main_navss_intr>;
 593                 };
 594
 595                 mailbox1_cluster7: mailbox@31f97000 {
 596                         compatible = "ti,am654-mailbox";
 597                         reg = <0x00 0x31f97000 0x00 0x200>;
 598                         #mbox-cells = <1>;
 599                         ti,mbox-num-users = <4>;
 600                         ti,mbox-num-fifos = <16>;
 601                         interrupt-parent = <&main_navss_intr>;
 602                 };
 603
 604                 mailbox1_cluster8: mailbox@31f98000 {
 605                         compatible = "ti,am654-mailbox";
 606                         reg = <0x00 0x31f98000 0x00 0x200>;
 607                         #mbox-cells = <1>;
 608                         ti,mbox-num-users = <4>;
 609                         ti,mbox-num-fifos = <16>;
 610                         interrupt-parent = <&main_navss_intr>;
 611                 };
 612
 613                 mailbox1_cluster9: mailbox@31f99000 {
 614                         compatible = "ti,am654-mailbox";
 615                         reg = <0x00 0x31f99000 0x00 0x200>;
 616                         #mbox-cells = <1>;
 617                         ti,mbox-num-users = <4>;
 618                         ti,mbox-num-fifos = <16>;
 619                         interrupt-parent = <&main_navss_intr>;
 620                 };
 621
 622                 mailbox1_cluster10: mailbox@31f9a000 {
 623                         compatible = "ti,am654-mailbox";
 624                         reg = <0x00 0x31f9a000 0x00 0x200>;
 625                         #mbox-cells = <1>;
 626                         ti,mbox-num-users = <4>;
 627                         ti,mbox-num-fifos = <16>;
 628                         interrupt-parent = <&main_navss_intr>;
 629                 };
 630
 631                 mailbox1_cluster11: mailbox@31f9b000 {
 632                         compatible = "ti,am654-mailbox";
 633                         reg = <0x00 0x31f9b000 0x00 0x200>;
 634                         #mbox-cells = <1>;
 635                         ti,mbox-num-users = <4>;
 636                         ti,mbox-num-fifos = <16>;
 637                         interrupt-parent = <&main_navss_intr>;
 638                 };
 639
 640                 main_ringacc: ringacc@3c000000 {
 641                         compatible = "ti,am654-navss-ringacc";
 642                         reg = <0x0 0x3c000000 0x0 0x400000>,
 643                               <0x0 0x38000000 0x0 0x400000>,
 644                               <0x0 0x31120000 0x0 0x100>,
 645                               <0x0 0x33000000 0x0 0x40000>;
 646                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 647                         ti,num-rings = <1024>;
 648                         ti,sci-rm-range-gp-rings = <0x1>;
 649                         ti,sci = <&sms>;
 650                         ti,sci-dev-id = <259>;
 651                         msi-parent = <&main_udmass_inta>;
 652                 };
 653
 654                 main_udmap: dma-controller@31150000 {
 655                         compatible = "ti,j721e-navss-main-udmap";
 656                         reg = <0x0 0x31150000 0x0 0x100>,
 657                               <0x0 0x34000000 0x0 0x80000>,
 658                               <0x0 0x35000000 0x0 0x200000>;
 659                         reg-names = "gcfg", "rchanrt", "tchanrt";
 660                         msi-parent = <&main_udmass_inta>;
 661                         #dma-cells = <1>;
 662
 663                         ti,sci = <&sms>;
 664                         ti,sci-dev-id = <263>;
 665                         ti,ringacc = <&main_ringacc>;
 666
 667                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
 668                                                 <0x0f>, /* TX_HCHAN */
 669                                                 <0x10>; /* TX_UHCHAN */
 670                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 671                                                 <0x0b>, /* RX_HCHAN */
 672                                                 <0x0c>; /* RX_UHCHAN */
 673                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 674                 };
 675
 676                 cpts@310d0000 {
 677                         compatible = "ti,j721e-cpts";
 678                         reg = <0x0 0x310d0000 0x0 0x400>;
 679                         reg-names = "cpts";
 680                         clocks = <&k3_clks 226 5>;
 681                         clock-names = "cpts";
 682                         interrupts-extended = <&main_navss_intr 391>;
 683                         interrupt-names = "cpts";
 684                         ti,cpts-periodic-outputs = <6>;
 685                         ti,cpts-ext-ts-inputs = <8>;
 686                 };
 687         };
 688
 689         main_mcan0: can@2701000 {
 690                 compatible = "bosch,m_can";
 691                 reg = <0x00 0x02701000 0x00 0x200>,
 692                       <0x00 0x02708000 0x00 0x8000>;
 693                 reg-names = "m_can", "message_ram";
 694                 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
 695                 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
 696                 clock-names = "hclk", "cclk";
 697                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 698                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 699                 interrupt-names = "int0", "int1";
 700                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 701         };
 702
 703         main_mcan1: can@2711000 {
 704                 compatible = "bosch,m_can";
 705                 reg = <0x00 0x02711000 0x00 0x200>,
 706                       <0x00 0x02718000 0x00 0x8000>;
 707                 reg-names = "m_can", "message_ram";
 708                 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
 709                 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
 710                 clock-names = "hclk", "cclk";
 711                 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 712                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 713                 interrupt-names = "int0", "int1";
 714                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 715         };
 716
 717         main_mcan2: can@2721000 {
 718                 compatible = "bosch,m_can";
 719                 reg = <0x00 0x02721000 0x00 0x200>,
 720                       <0x00 0x02728000 0x00 0x8000>;
 721                 reg-names = "m_can", "message_ram";
 722                 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
 723                 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
 724                 clock-names = "hclk", "cclk";
 725                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 726                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 727                 interrupt-names = "int0", "int1";
 728                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 729         };
 730
 731         main_mcan3: can@2731000 {
 732                 compatible = "bosch,m_can";
 733                 reg = <0x00 0x02731000 0x00 0x200>,
 734                       <0x00 0x02738000 0x00 0x8000>;
 735                 reg-names = "m_can", "message_ram";
 736                 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
 737                 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
 738                 clock-names = "hclk", "cclk";
 739                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 740                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 741                 interrupt-names = "int0", "int1";
 742                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 743         };
 744
 745         main_mcan4: can@2741000 {
 746                 compatible = "bosch,m_can";
 747                 reg = <0x00 0x02741000 0x00 0x200>,
 748                       <0x00 0x02748000 0x00 0x8000>;
 749                 reg-names = "m_can", "message_ram";
 750                 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
 751                 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
 752                 clock-names = "hclk", "cclk";
 753                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 754                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 755                 interrupt-names = "int0", "int1";
 756                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 757         };
 758
 759         main_mcan5: can@2751000 {
 760                 compatible = "bosch,m_can";
 761                 reg = <0x00 0x02751000 0x00 0x200>,
 762                       <0x00 0x02758000 0x00 0x8000>;
 763                 reg-names = "m_can", "message_ram";
 764                 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
 765                 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
 766                 clock-names = "hclk", "cclk";
 767                 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 768                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 769                 interrupt-names = "int0", "int1";
 770                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 771         };
 772
 773         main_mcan6: can@2761000 {
 774                 compatible = "bosch,m_can";
 775                 reg = <0x00 0x02761000 0x00 0x200>,
 776                       <0x00 0x02768000 0x00 0x8000>;
 777                 reg-names = "m_can", "message_ram";
 778                 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
 779                 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
 780                 clock-names = "hclk", "cclk";
 781                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 782                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 783                 interrupt-names = "int0", "int1";
 784                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 785         };
 786
 787         main_mcan7: can@2771000 {
 788                 compatible = "bosch,m_can";
 789                 reg = <0x00 0x02771000 0x00 0x200>,
 790                       <0x00 0x02778000 0x00 0x8000>;
 791                 reg-names = "m_can", "message_ram";
 792                 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
 793                 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
 794                 clock-names = "hclk", "cclk";
 795                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 796                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 797                 interrupt-names = "int0", "int1";
 798                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 799         };
 800
 801         main_mcan8: can@2781000 {
 802                 compatible = "bosch,m_can";
 803                 reg = <0x00 0x02781000 0x00 0x200>,
 804                       <0x00 0x02788000 0x00 0x8000>;
 805                 reg-names = "m_can", "message_ram";
 806                 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
 807                 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
 808                 clock-names = "hclk", "cclk";
 809                 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
 810                              <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
 811                 interrupt-names = "int0", "int1";
 812                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 813         };
 814
 815         main_mcan9: can@2791000 {
 816                 compatible = "bosch,m_can";
 817                 reg = <0x00 0x02791000 0x00 0x200>,
 818                       <0x00 0x02798000 0x00 0x8000>;
 819                 reg-names = "m_can", "message_ram";
 820                 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
 821                 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
 822                 clock-names = "hclk", "cclk";
 823                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
 824                              <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
 825                 interrupt-names = "int0", "int1";
 826                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 827         };
 828
 829         main_mcan10: can@27a1000 {
 830                 compatible = "bosch,m_can";
 831                 reg = <0x00 0x027a1000 0x00 0x200>,
 832                       <0x00 0x027a8000 0x00 0x8000>;
 833                 reg-names = "m_can", "message_ram";
 834                 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
 835                 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
 836                 clock-names = "hclk", "cclk";
 837                 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
 838                              <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 839                 interrupt-names = "int0", "int1";
 840                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 841         };
 842
 843         main_mcan11: can@27b1000 {
 844                 compatible = "bosch,m_can";
 845                 reg = <0x00 0x027b1000 0x00 0x200>,
 846                       <0x00 0x027b8000 0x00 0x8000>;
 847                 reg-names = "m_can", "message_ram";
 848                 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
 849                 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
 850                 clock-names = "hclk", "cclk";
 851                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
 852                              <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 853                 interrupt-names = "int0", "int1";
 854                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 855         };
 856
 857         main_mcan12: can@27c1000 {
 858                 compatible = "bosch,m_can";
 859                 reg = <0x00 0x027c1000 0x00 0x200>,
 860                       <0x00 0x027c8000 0x00 0x8000>;
 861                 reg-names = "m_can", "message_ram";
 862                 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
 863                 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
 864                 clock-names = "hclk", "cclk";
 865                 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 866                              <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
 867                 interrupt-names = "int0", "int1";
 868                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 869         };
 870
 871         main_mcan13: can@27d1000 {
 872                 compatible = "bosch,m_can";
 873                 reg = <0x00 0x027d1000 0x00 0x200>,
 874                       <0x00 0x027d8000 0x00 0x8000>;
 875                 reg-names = "m_can", "message_ram";
 876                 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
 877                 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
 878                 clock-names = "hclk", "cclk";
 879                 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 880                              <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
 881                 interrupt-names = "int0", "int1";
 882                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 883         };
 884
 885         main_mcan14: can@2681000 {
 886                 compatible = "bosch,m_can";
 887                 reg = <0x00 0x02681000 0x00 0x200>,
 888                       <0x00 0x02688000 0x00 0x8000>;
 889                 reg-names = "m_can", "message_ram";
 890                 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
 891                 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
 892                 clock-names = "hclk", "cclk";
 893                 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 894                              <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
 895                 interrupt-names = "int0", "int1";
 896                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 897         };
 898
 899         main_mcan15: can@2691000 {
 900                 compatible = "bosch,m_can";
 901                 reg = <0x00 0x02691000 0x00 0x200>,
 902                       <0x00 0x02698000 0x00 0x8000>;
 903                 reg-names = "m_can", "message_ram";
 904                 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
 905                 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
 906                 clock-names = "hclk", "cclk";
 907                 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 908                              <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
 909                 interrupt-names = "int0", "int1";
 910                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 911         };
 912
 913         main_mcan16: can@26a1000 {
 914                 compatible = "bosch,m_can";
 915                 reg = <0x00 0x026a1000 0x00 0x200>,
 916                       <0x00 0x026a8000 0x00 0x8000>;
 917                 reg-names = "m_can", "message_ram";
 918                 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
 919                 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
 920                 clock-names = "hclk", "cclk";
 921                 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
 922                              <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
 923                 interrupt-names = "int0", "int1";
 924                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 925         };
 926
 927         main_mcan17: can@26b1000 {
 928                 compatible = "bosch,m_can";
 929                 reg = <0x00 0x026b1000 0x00 0x200>,
 930                       <0x00 0x026b8000 0x00 0x8000>;
 931                 reg-names = "m_can", "message_ram";
 932                 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
 933                 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
 934                 clock-names = "hclk", "cclk";
 935                 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
 936                              <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
 937                 interrupt-names = "int0", "int1";
 938                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 939         };
 940 };