arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
   4  *
   5  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_mcu_wakeup {
   9         dmsc: system-controller@44083000 {
  10                 compatible = "ti,k2g-sci";
  11                 ti,host-id = <12>;
  12
  13                 mbox-names = "rx", "tx";
  14
  15                 mboxes = <&secure_proxy_main 11>,
  16                          <&secure_proxy_main 13>;
  17
  18                 reg-names = "debug_messages";
  19                 reg = <0x00 0x44083000 0x00 0x1000>;
  20
  21                 k3_pds: power-controller {
  22                         compatible = "ti,sci-pm-domain";
  23                         #power-domain-cells = <2>;
  24                 };
  25
  26                 k3_clks: clock-controller {
  27                         compatible = "ti,k2g-sci-clk";
  28                         #clock-cells = <2>;
  29                 };
  30
  31                 k3_reset: reset-controller {
  32                         compatible = "ti,sci-reset";
  33                         #reset-cells = <2>;
  34                 };
  35         };
  36
  37         mcu_timer0: timer@40400000 {
  38                 status = "reserved";
  39                 compatible = "ti,am654-timer";
  40                 reg = <0x00 0x40400000 0x00 0x400>;
  41                 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
  42                 clocks = <&k3_clks 35 1>;
  43                 clock-names = "fck";
  44                 assigned-clocks = <&k3_clks 35 1>;
  45                 assigned-clock-parents = <&k3_clks 35 2>;
  46                 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
  47                 ti,timer-pwm;
  48         };
  49
  50         mcu_timer1: timer@40410000 {
  51                 status = "reserved";
  52                 compatible = "ti,am654-timer";
  53                 reg = <0x00 0x40410000 0x00 0x400>;
  54                 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
  55                 clocks = <&k3_clks 71 1>;
  56                 clock-names = "fck";
  57                 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
  58                 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>;
  59                 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
  60                 ti,timer-pwm;
  61         };
  62
  63         mcu_timer2: timer@40420000 {
  64                 status = "reserved";
  65                 compatible = "ti,am654-timer";
  66                 reg = <0x00 0x40420000 0x00 0x400>;
  67                 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
  68                 clocks = <&k3_clks 72 1>;
  69                 clock-names = "fck";
  70                 assigned-clocks = <&k3_clks 72 1>;
  71                 assigned-clock-parents = <&k3_clks 72 2>;
  72                 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
  73                 ti,timer-pwm;
  74         };
  75
  76         mcu_timer3: timer@40430000 {
  77                 status = "reserved";
  78                 compatible = "ti,am654-timer";
  79                 reg = <0x00 0x40430000 0x00 0x400>;
  80                 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
  81                 clocks = <&k3_clks 73 1>;
  82                 clock-names = "fck";
  83                 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
  84                 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>;
  85                 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
  86                 ti,timer-pwm;
  87         };
  88
  89         mcu_timer4: timer@40440000 {
  90                 status = "reserved";
  91                 compatible = "ti,am654-timer";
  92                 reg = <0x00 0x40440000 0x00 0x400>;
  93                 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
  94                 clocks = <&k3_clks 74 1>;
  95                 clock-names = "fck";
  96                 assigned-clocks = <&k3_clks 74 1>;
  97                 assigned-clock-parents = <&k3_clks 74 2>;
  98                 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
  99                 ti,timer-pwm;
 100         };
 101
 102         mcu_timer5: timer@40450000 {
 103                 status = "reserved";
 104                 compatible = "ti,am654-timer";
 105                 reg = <0x00 0x40450000 0x00 0x400>;
 106                 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
 107                 clocks = <&k3_clks 75 1>;
 108                 clock-names = "fck";
 109                 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
 110                 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>;
 111                 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
 112                 ti,timer-pwm;
 113         };
 114
 115         mcu_timer6: timer@40460000 {
 116                 status = "reserved";
 117                 compatible = "ti,am654-timer";
 118                 reg = <0x00 0x40460000 0x00 0x400>;
 119                 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
 120                 clocks = <&k3_clks 76 1>;
 121                 clock-names = "fck";
 122                 assigned-clocks = <&k3_clks 76 1>;
 123                 assigned-clock-parents = <&k3_clks 76 2>;
 124                 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
 125                 ti,timer-pwm;
 126         };
 127
 128         mcu_timer7: timer@40470000 {
 129                 status = "reserved";
 130                 compatible = "ti,am654-timer";
 131                 reg = <0x00 0x40470000 0x00 0x400>;
 132                 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
 133                 clocks = <&k3_clks 77 1>;
 134                 clock-names = "fck";
 135                 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>;
 136                 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>;
 137                 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
 138                 ti,timer-pwm;
 139         };
 140
 141         mcu_timer8: timer@40480000 {
 142                 status = "reserved";
 143                 compatible = "ti,am654-timer";
 144                 reg = <0x00 0x40480000 0x00 0x400>;
 145                 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
 146                 clocks = <&k3_clks 78 1>;
 147                 clock-names = "fck";
 148                 assigned-clocks = <&k3_clks 78 1>;
 149                 assigned-clock-parents = <&k3_clks 78 2>;
 150                 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
 151                 ti,timer-pwm;
 152         };
 153
 154         mcu_timer9: timer@40490000 {
 155                 status = "reserved";
 156                 compatible = "ti,am654-timer";
 157                 reg = <0x00 0x40490000 0x00 0x400>;
 158                 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
 159                 clocks = <&k3_clks 79 1>;
 160                 clock-names = "fck";
 161                 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>;
 162                 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>;
 163                 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
 164                 ti,timer-pwm;
 165         };
 166
 167         mcu_conf: syscon@40f00000 {
 168                 compatible = "syscon", "simple-mfd";
 169                 reg = <0x00 0x40f00000 0x00 0x20000>;
 170                 #address-cells = <1>;
 171                 #size-cells = <1>;
 172                 ranges = <0x00 0x00 0x40f00000 0x20000>;
 173
 174                 phy_gmii_sel: phy@4040 {
 175                         compatible = "ti,am654-phy-gmii-sel";
 176                         reg = <0x4040 0x4>;
 177                         #phy-cells = <1>;
 178                 };
 179         };
 180
 181         wkup_conf: bus@43000000 {
 182                 compatible = "simple-bus";
 183                 #address-cells = <1>;
 184                 #size-cells = <1>;
 185                 ranges = <0x0 0x00 0x43000000 0x20000>;
 186
 187                 chipid: chipid@14 {
 188                         compatible = "ti,am654-chipid";
 189                         reg = <0x14 0x4>;
 190                 };
 191         };
 192
 193         /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
 194         mcu_timerio_input: pinctrl@40f04200 {
 195                 compatible = "pinctrl-single";
 196                 reg = <0x0 0x40f04200 0x0 0x28>;
 197                 #pinctrl-cells = <1>;
 198                 pinctrl-single,register-width = <32>;
 199                 pinctrl-single,function-mask = <0x0000000F>;
 200                 status = "reserved";
 201         };
 202
 203         /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
 204         mcu_timerio_output: pinctrl@40f04280 {
 205                 compatible = "pinctrl-single";
 206                 reg = <0x0 0x40f04280 0x0 0x28>;
 207                 #pinctrl-cells = <1>;
 208                 pinctrl-single,register-width = <32>;
 209                 pinctrl-single,function-mask = <0x0000000F>;
 210                 status = "reserved";
 211         };
 212
 213         wkup_pmx0: pinctrl@4301c000 {
 214                 compatible = "pinctrl-single";
 215                 /* Proxy 0 addressing */
 216                 reg = <0x00 0x4301c000 0x00 0x34>;
 217                 #pinctrl-cells = <1>;
 218                 pinctrl-single,register-width = <32>;
 219                 pinctrl-single,function-mask = <0xffffffff>;
 220         };
 221
 222         wkup_pmx1: pinctrl@4301c038 {
 223                 compatible = "pinctrl-single";
 224                 /* Proxy 0 addressing */
 225                 reg = <0x00 0x4301c038 0x00 0x8>;
 226                 #pinctrl-cells = <1>;
 227                 pinctrl-single,register-width = <32>;
 228                 pinctrl-single,function-mask = <0xffffffff>;
 229         };
 230
 231         wkup_pmx2: pinctrl@4301c068 {
 232                 compatible = "pinctrl-single";
 233                 /* Proxy 0 addressing */
 234                 reg = <0x00 0x4301c068 0x00 0xec>;
 235                 #pinctrl-cells = <1>;
 236                 pinctrl-single,register-width = <32>;
 237                 pinctrl-single,function-mask = <0xffffffff>;
 238         };
 239
 240         wkup_pmx3: pinctrl@4301c174 {
 241                 compatible = "pinctrl-single";
 242                 /* Proxy 0 addressing */
 243                 reg = <0x00 0x4301c174 0x00 0x20>;
 244                 #pinctrl-cells = <1>;
 245                 pinctrl-single,register-width = <32>;
 246                 pinctrl-single,function-mask = <0xffffffff>;
 247         };
 248
 249         mcu_ram: sram@41c00000 {
 250                 compatible = "mmio-sram";
 251                 reg = <0x00 0x41c00000 0x00 0x100000>;
 252                 ranges = <0x00 0x00 0x41c00000 0x100000>;
 253                 #address-cells = <1>;
 254                 #size-cells = <1>;
 255         };
 256
 257         wkup_uart0: serial@42300000 {
 258                 compatible = "ti,j721e-uart", "ti,am654-uart";
 259                 reg = <0x00 0x42300000 0x00 0x100>;
 260                 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
 261                 clock-frequency = <48000000>;
 262                 current-speed = <115200>;
 263                 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
 264                 clocks = <&k3_clks 287 2>;
 265                 clock-names = "fclk";
 266                 status = "disabled";
 267         };
 268
 269         mcu_uart0: serial@40a00000 {
 270                 compatible = "ti,j721e-uart", "ti,am654-uart";
 271                 reg = <0x00 0x40a00000 0x00 0x100>;
 272                 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
 273                 clock-frequency = <96000000>;
 274                 current-speed = <115200>;
 275                 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
 276                 clocks = <&k3_clks 149 2>;
 277                 clock-names = "fclk";
 278                 status = "disabled";
 279         };
 280
 281         wkup_gpio_intr: interrupt-controller@42200000 {
 282                 compatible = "ti,sci-intr";
 283                 reg = <0x00 0x42200000 0x00 0x400>;
 284                 ti,intr-trigger-type = <1>;
 285                 interrupt-controller;
 286                 interrupt-parent = <&gic500>;
 287                 #interrupt-cells = <1>;
 288                 ti,sci = <&dmsc>;
 289                 ti,sci-dev-id = <137>;
 290                 ti,interrupt-ranges = <16 960 16>;
 291         };
 292
 293         wkup_gpio0: gpio@42110000 {
 294                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 295                 reg = <0x00 0x42110000 0x00 0x100>;
 296                 gpio-controller;
 297                 #gpio-cells = <2>;
 298                 interrupt-parent = <&wkup_gpio_intr>;
 299                 interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
 300                 interrupt-controller;
 301                 #interrupt-cells = <2>;
 302                 ti,ngpio = <85>;
 303                 ti,davinci-gpio-unbanked = <0>;
 304                 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
 305                 clocks = <&k3_clks 113 0>;
 306                 clock-names = "gpio";
 307                 status = "disabled";
 308         };
 309
 310         wkup_gpio1: gpio@42100000 {
 311                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 312                 reg = <0x00 0x42100000 0x00 0x100>;
 313                 gpio-controller;
 314                 #gpio-cells = <2>;
 315                 interrupt-parent = <&wkup_gpio_intr>;
 316                 interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
 317                 interrupt-controller;
 318                 #interrupt-cells = <2>;
 319                 ti,ngpio = <85>;
 320                 ti,davinci-gpio-unbanked = <0>;
 321                 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
 322                 clocks = <&k3_clks 114 0>;
 323                 clock-names = "gpio";
 324                 status = "disabled";
 325         };
 326
 327         mcu_navss: bus@28380000 {
 328                 compatible = "simple-bus";
 329                 #address-cells = <2>;
 330                 #size-cells = <2>;
 331                 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
 332                 dma-coherent;
 333                 dma-ranges;
 334                 ti,sci-dev-id = <232>;
 335
 336                 mcu_ringacc: ringacc@2b800000 {
 337                         compatible = "ti,am654-navss-ringacc";
 338                         reg = <0x00 0x2b800000 0x00 0x400000>,
 339                               <0x00 0x2b000000 0x00 0x400000>,
 340                               <0x00 0x28590000 0x00 0x100>,
 341                               <0x00 0x2a500000 0x00 0x40000>,
 342                               <0x00 0x28440000 0x00 0x40000>;
 343                         reg-names = "rt", "fifos", "proxy_gcfg",
 344                                     "proxy_target", "cfg";
 345                         ti,num-rings = <286>;
 346                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 347                         ti,sci = <&dmsc>;
 348                         ti,sci-dev-id = <235>;
 349                         msi-parent = <&main_udmass_inta>;
 350                 };
 351
 352                 mcu_udmap: dma-controller@285c0000 {
 353                         compatible = "ti,j721e-navss-mcu-udmap";
 354                         reg = <0x00 0x285c0000 0x00 0x100>,
 355                               <0x00 0x2a800000 0x00 0x40000>,
 356                               <0x00 0x2aa00000 0x00 0x40000>;
 357                         reg-names = "gcfg", "rchanrt", "tchanrt";
 358                         msi-parent = <&main_udmass_inta>;
 359                         #dma-cells = <1>;
 360
 361                         ti,sci = <&dmsc>;
 362                         ti,sci-dev-id = <236>;
 363                         ti,ringacc = <&mcu_ringacc>;
 364
 365                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
 366                                                 <0x0f>; /* TX_HCHAN */
 367                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 368                                                 <0x0b>; /* RX_HCHAN */
 369                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 370                 };
 371         };
 372
 373         secure_proxy_mcu: mailbox@2a480000 {
 374                 compatible = "ti,am654-secure-proxy";
 375                 #mbox-cells = <1>;
 376                 reg-names = "target_data", "rt", "scfg";
 377                 reg = <0x0 0x2a480000 0x0 0x80000>,
 378                       <0x0 0x2a380000 0x0 0x80000>,
 379                       <0x0 0x2a400000 0x0 0x80000>;
 380                 /*
 381                  * Marked Disabled:
 382                  * Node is incomplete as it is meant for bootloaders and
 383                  * firmware on non-MPU processors
 384                  */
 385                 status = "disabled";
 386         };
 387
 388         mcu_cpsw: ethernet@46000000 {
 389                 compatible = "ti,j721e-cpsw-nuss";
 390                 #address-cells = <2>;
 391                 #size-cells = <2>;
 392                 reg = <0x00 0x46000000 0x00 0x200000>;
 393                 reg-names = "cpsw_nuss";
 394                 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
 395                 dma-coherent;
 396                 clocks = <&k3_clks 18 21>;
 397                 clock-names = "fck";
 398                 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
 399
 400                 dmas = <&mcu_udmap 0xf000>,
 401                        <&mcu_udmap 0xf001>,
 402                        <&mcu_udmap 0xf002>,
 403                        <&mcu_udmap 0xf003>,
 404                        <&mcu_udmap 0xf004>,
 405                        <&mcu_udmap 0xf005>,
 406                        <&mcu_udmap 0xf006>,
 407                        <&mcu_udmap 0xf007>,
 408                        <&mcu_udmap 0x7000>;
 409                 dma-names = "tx0", "tx1", "tx2", "tx3",
 410                             "tx4", "tx5", "tx6", "tx7",
 411                             "rx";
 412
 413                 ethernet-ports {
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416
 417                         cpsw_port1: port@1 {
 418                                 reg = <1>;
 419                                 ti,mac-only;
 420                                 label = "port1";
 421                                 ti,syscon-efuse = <&mcu_conf 0x200>;
 422                                 phys = <&phy_gmii_sel 1>;
 423                         };
 424                 };
 425
 426                 davinci_mdio: mdio@f00 {
 427                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 428                         reg = <0x00 0xf00 0x00 0x100>;
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                         clocks = <&k3_clks 18 21>;
 432                         clock-names = "fck";
 433                         bus_freq = <1000000>;
 434                 };
 435
 436                 cpts@3d000 {
 437                         compatible = "ti,am65-cpts";
 438                         reg = <0x00 0x3d000 0x00 0x400>;
 439                         clocks = <&k3_clks 18 2>;
 440                         clock-names = "cpts";
 441                         interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
 442                         interrupt-names = "cpts";
 443                         ti,cpts-ext-ts-inputs = <4>;
 444                         ti,cpts-periodic-outputs = <2>;
 445                 };
 446         };
 447
 448         mcu_i2c0: i2c@40b00000 {
 449                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 450                 reg = <0x00 0x40b00000 0x00 0x100>;
 451                 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
 452                 #address-cells = <1>;
 453                 #size-cells = <0>;
 454                 clock-names = "fck";
 455                 clocks = <&k3_clks 194 1>;
 456                 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
 457                 status = "disabled";
 458         };
 459
 460         mcu_i2c1: i2c@40b10000 {
 461                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 462                 reg = <0x00 0x40b10000 0x00 0x100>;
 463                 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
 464                 #address-cells = <1>;
 465                 #size-cells = <0>;
 466                 clock-names = "fck";
 467                 clocks = <&k3_clks 195 1>;
 468                 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
 469                 status = "disabled";
 470         };
 471
 472         wkup_i2c0: i2c@42120000 {
 473                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 474                 reg = <0x00 0x42120000 0x00 0x100>;
 475                 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
 476                 #address-cells = <1>;
 477                 #size-cells = <0>;
 478                 clock-names = "fck";
 479                 clocks = <&k3_clks 197 1>;
 480                 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
 481                 status = "disabled";
 482         };
 483
 484         mcu_spi0: spi@40300000 {
 485                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
 486                 reg = <0x00 0x040300000 0x00 0x400>;
 487                 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
 491                 clocks = <&k3_clks 274 0>;
 492                 status = "disabled";
 493         };
 494
 495         mcu_spi1: spi@40310000 {
 496                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
 497                 reg = <0x00 0x040310000 0x00 0x400>;
 498                 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501                 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
 502                 clocks = <&k3_clks 275 0>;
 503                 status = "disabled";
 504         };
 505
 506         mcu_spi2: spi@40320000 {
 507                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
 508                 reg = <0x00 0x040320000 0x00 0x400>;
 509                 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
 510                 #address-cells = <1>;
 511                 #size-cells = <0>;
 512                 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
 513                 clocks = <&k3_clks 276 0>;
 514                 status = "disabled";
 515         };
 516
 517         fss: syscon@47000000 {
 518                 compatible = "syscon", "simple-mfd";
 519                 reg = <0x00 0x47000000 0x00 0x100>;
 520                 #address-cells = <2>;
 521                 #size-cells = <2>;
 522                 ranges;
 523
 524                 hbmc_mux: hbmc-mux {
 525                         compatible = "mmio-mux";
 526                         #mux-control-cells = <1>;
 527                         mux-reg-masks = <0x4 0x2>; /* HBMC select */
 528                 };
 529
 530                 hbmc: hyperbus@47034000 {
 531                         compatible = "ti,am654-hbmc";
 532                         reg = <0x00 0x47034000 0x00 0x100>,
 533                                 <0x05 0x00000000 0x01 0x0000000>;
 534                         power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 535                         clocks = <&k3_clks 102 0>;
 536                         assigned-clocks = <&k3_clks 102 5>;
 537                         assigned-clock-rates = <333333333>;
 538                         #address-cells = <2>;
 539                         #size-cells = <1>;
 540                         mux-controls = <&hbmc_mux 0>;
 541                 };
 542
 543                 ospi0: spi@47040000 {
 544                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 545                         reg = <0x0 0x47040000 0x0 0x100>,
 546                               <0x5 0x00000000 0x1 0x0000000>;
 547                         interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
 548                         cdns,fifo-depth = <256>;
 549                         cdns,fifo-width = <4>;
 550                         cdns,trigger-address = <0x0>;
 551                         clocks = <&k3_clks 103 0>;
 552                         assigned-clocks = <&k3_clks 103 0>;
 553                         assigned-clock-parents = <&k3_clks 103 2>;
 554                         assigned-clock-rates = <166666666>;
 555                         power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
 556                         #address-cells = <1>;
 557                         #size-cells = <0>;
 558                         status = "disabled";
 559                 };
 560         };
 561
 562         tscadc0: tscadc@40200000 {
 563                 compatible = "ti,am3359-tscadc";
 564                 reg = <0x00 0x40200000 0x00 0x1000>;
 565                 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
 566                 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
 567                 clocks = <&k3_clks 0 1>;
 568                 assigned-clocks = <&k3_clks 0 3>;
 569                 assigned-clock-rates = <60000000>;
 570                 clock-names = "fck";
 571                 dmas = <&main_udmap 0x7400>,
 572                         <&main_udmap 0x7401>;
 573                 dma-names = "fifo0", "fifo1";
 574
 575                 adc {
 576                         #io-channel-cells = <1>;
 577                         compatible = "ti,am3359-adc";
 578                 };
 579         };
 580
 581         mcu_r5fss0: r5fss@41000000 {
 582                 compatible = "ti,j7200-r5fss";
 583                 ti,cluster-mode = <1>;
 584                 #address-cells = <1>;
 585                 #size-cells = <1>;
 586                 ranges = <0x41000000 0x00 0x41000000 0x20000>,
 587                          <0x41400000 0x00 0x41400000 0x20000>;
 588                 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
 589
 590                 mcu_r5fss0_core0: r5f@41000000 {
 591                         compatible = "ti,j7200-r5f";
 592                         reg = <0x41000000 0x00010000>,
 593                               <0x41010000 0x00010000>;
 594                         reg-names = "atcm", "btcm";
 595                         ti,sci = <&dmsc>;
 596                         ti,sci-dev-id = <250>;
 597                         ti,sci-proc-ids = <0x01 0xff>;
 598                         resets = <&k3_reset 250 1>;
 599                         firmware-name = "j7200-mcu-r5f0_0-fw";
 600                         ti,atcm-enable = <1>;
 601                         ti,btcm-enable = <1>;
 602                         ti,loczrama = <1>;
 603                 };
 604
 605                 mcu_r5fss0_core1: r5f@41400000 {
 606                         compatible = "ti,j7200-r5f";
 607                         reg = <0x41400000 0x00008000>,
 608                               <0x41410000 0x00008000>;
 609                         reg-names = "atcm", "btcm";
 610                         ti,sci = <&dmsc>;
 611                         ti,sci-dev-id = <251>;
 612                         ti,sci-proc-ids = <0x02 0xff>;
 613                         resets = <&k3_reset 251 1>;
 614                         firmware-name = "j7200-mcu-r5f0_1-fw";
 615                         ti,atcm-enable = <1>;
 616                         ti,btcm-enable = <1>;
 617                         ti,loczrama = <1>;
 618                 };
 619         };
 620
 621         mcu_crypto: crypto@40900000 {
 622                 compatible = "ti,j721e-sa2ul";
 623                 reg = <0x00 0x40900000 0x00 0x1200>;
 624                 power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
 625                 #address-cells = <2>;
 626                 #size-cells = <2>;
 627                 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
 628                 dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
 629                        <&mcu_udmap 0x7503>;
 630                 dma-names = "tx", "rx1", "rx2";
 631
 632                 rng: rng@40910000 {
 633                         compatible = "inside-secure,safexcel-eip76";
 634                         reg = <0x00 0x40910000 0x00 0x7d>;
 635                         interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
 636                         status = "disabled"; /* Used by OP-TEE */
 637                 };
 638         };
 639
 640         wkup_vtm0: temperature-sensor@42040000 {
 641                 compatible = "ti,j7200-vtm";
 642                 reg = <0x00 0x42040000 0x00 0x350>,
 643                       <0x00 0x42050000 0x00 0x350>;
 644                 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
 645                 #thermal-sensor-cells = <1>;
 646         };
 647
 648         mcu_esm: esm@40800000 {
 649                 compatible = "ti,j721e-esm";
 650                 reg = <0x00 0x40800000 0x00 0x1000>;
 651                 ti,esm-pins = <95>;
 652                 bootph-pre-ram;
 653         };
 654 };