1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
6 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
12 #include <dt-bindings/gpio/gpio.h>
14 #include "k3-pinctrl.h"
15 #include "k3-serdes.h"
19 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
20 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
21 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
22 ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
32 phy-handle = <&cpsw5g_phy0>;
34 mac-address = [00 00 00 00 00 00];
35 phys = <&cpsw0_phy_gmii_sel 1>;
40 phy-handle = <&cpsw5g_phy1>;
42 mac-address = [00 00 00 00 00 00];
43 phys = <&cpsw0_phy_gmii_sel 2>;
48 phy-handle = <&cpsw5g_phy2>;
50 mac-address = [00 00 00 00 00 00];
51 phys = <&cpsw0_phy_gmii_sel 3>;
56 phy-handle = <&cpsw5g_phy3>;
58 mac-address = [00 00 00 00 00 00];
59 phys = <&cpsw0_phy_gmii_sel 4>;
64 pinctrl-names = "default";
65 pinctrl-0 = <&mdio0_pins_default>;
66 reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
67 reset-post-delay-us = <120000>;
71 cpsw5g_phy0: ethernet-phy@16 {
74 cpsw5g_phy1: ethernet-phy@17 {
77 cpsw5g_phy2: ethernet-phy@18 {
80 cpsw5g_phy3: ethernet-phy@19 {
88 gpios = <16 GPIO_ACTIVE_HIGH>;
90 line-name = "qsgmii-pwrdn-line";
95 mdio0_pins_default: mdio0-default-pins {
96 pinctrl-single,pins = <
97 J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */
98 J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */