1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for the AM62P5 SoC family (quad core)
4 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
6 * TRM: https://www.ti.com/lit/pdf/spruj83
11 #include "k3-am62p.dtsi"
39 compatible = "arm,cortex-a53";
42 enable-method = "psci";
43 i-cache-size = <0x8000>;
44 i-cache-line-size = <64>;
46 d-cache-size = <0x8000>;
47 d-cache-line-size = <64>;
49 next-level-cache = <&l2_0>;
50 clocks = <&k3_clks 135 0>;
54 compatible = "arm,cortex-a53";
57 enable-method = "psci";
58 i-cache-size = <0x8000>;
59 i-cache-line-size = <64>;
61 d-cache-size = <0x8000>;
62 d-cache-line-size = <64>;
64 next-level-cache = <&l2_0>;
65 clocks = <&k3_clks 136 0>;
69 compatible = "arm,cortex-a53";
72 enable-method = "psci";
73 i-cache-size = <0x8000>;
74 i-cache-line-size = <64>;
76 d-cache-size = <0x8000>;
77 d-cache-line-size = <64>;
79 next-level-cache = <&l2_0>;
80 clocks = <&k3_clks 137 0>;
84 compatible = "arm,cortex-a53";
87 enable-method = "psci";
88 i-cache-size = <0x8000>;
89 i-cache-line-size = <64>;
91 d-cache-size = <0x8000>;
92 d-cache-line-size = <64>;
94 next-level-cache = <&l2_0>;
95 clocks = <&k3_clks 138 0>;
100 compatible = "cache";
103 cache-size = <0x80000>;
104 cache-line-size = <64>;