arch/arm64/boot/dts/ti/k3-am62-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM625 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_main {
   9         oc_sram: sram@70000000 {
  10                 compatible = "mmio-sram";
  11                 reg = <0x00 0x70000000 0x00 0x10000>;
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 ranges = <0x0 0x00 0x70000000 0x10000>;
  15         };
  16
  17         gic500: interrupt-controller@1800000 {
  18                 compatible = "arm,gic-v3";
  19                 #address-cells = <2>;
  20                 #size-cells = <2>;
  21                 ranges;
  22                 #interrupt-cells = <3>;
  23                 interrupt-controller;
  24                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  25                       <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
  26                       <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
  27                       <0x01 0x00000000 0x00 0x2000>,    /* GICC */
  28                       <0x01 0x00010000 0x00 0x1000>,    /* GICH */
  29                       <0x01 0x00020000 0x00 0x2000>;    /* GICV */
  30                 /*
  31                  * vcpumntirq:
  32                  * virtual CPU interface maintenance interrupt
  33                  */
  34                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  35
  36                 gic_its: msi-controller@1820000 {
  37                         compatible = "arm,gic-v3-its";
  38                         reg = <0x00 0x01820000 0x00 0x10000>;
  39                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  40                         msi-controller;
  41                         #msi-cells = <1>;
  42                 };
  43         };
  44
  45         main_conf: syscon@100000 {
  46                 compatible = "syscon", "simple-mfd";
  47                 reg = <0x00 0x00100000 0x00 0x20000>;
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 ranges = <0x0 0x00 0x00100000 0x20000>;
  51
  52                 phy_gmii_sel: phy@4044 {
  53                         compatible = "ti,am654-phy-gmii-sel";
  54                         reg = <0x4044 0x8>;
  55                         #phy-cells = <1>;
  56                 };
  57
  58                 epwm_tbclk: clock-controller@4130 {
  59                         compatible = "ti,am62-epwm-tbclk";
  60                         reg = <0x4130 0x4>;
  61                         #clock-cells = <1>;
  62                 };
  63
  64                 audio_refclk0: clock-controller@82e0 {
  65                         compatible = "ti,am62-audio-refclk";
  66                         reg = <0x82e0 0x4>;
  67                         clocks = <&k3_clks 157 0>;
  68                         assigned-clocks = <&k3_clks 157 0>;
  69                         assigned-clock-parents = <&k3_clks 157 8>;
  70                         #clock-cells = <0>;
  71                 };
  72
  73                 audio_refclk1: clock-controller@82e4 {
  74                         compatible = "ti,am62-audio-refclk";
  75                         reg = <0x82e4 0x4>;
  76                         clocks = <&k3_clks 157 10>;
  77                         assigned-clocks = <&k3_clks 157 10>;
  78                         assigned-clock-parents = <&k3_clks 157 18>;
  79                         #clock-cells = <0>;
  80                 };
  81         };
  82
  83         dmss: bus@48000000 {
  84                 bootph-all;
  85                 compatible = "simple-bus";
  86                 #address-cells = <2>;
  87                 #size-cells = <2>;
  88                 dma-ranges;
  89                 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
  90
  91                 ti,sci-dev-id = <25>;
  92
  93                 secure_proxy_main: mailbox@4d000000 {
  94                         bootph-all;
  95                         compatible = "ti,am654-secure-proxy";
  96                         #mbox-cells = <1>;
  97                         reg-names = "target_data", "rt", "scfg";
  98                         reg = <0x00 0x4d000000 0x00 0x80000>,
  99                               <0x00 0x4a600000 0x00 0x80000>,
 100                               <0x00 0x4a400000 0x00 0x80000>;
 101                         interrupt-names = "rx_012";
 102                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 103                 };
 104
 105                 inta_main_dmss: interrupt-controller@48000000 {
 106                         compatible = "ti,sci-inta";
 107                         reg = <0x00 0x48000000 0x00 0x100000>;
 108                         #interrupt-cells = <0>;
 109                         interrupt-controller;
 110                         interrupt-parent = <&gic500>;
 111                         msi-controller;
 112                         ti,sci = <&dmsc>;
 113                         ti,sci-dev-id = <28>;
 114                         ti,interrupt-ranges = <4 68 36>;
 115                         ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
 116                 };
 117
 118                 main_bcdma: dma-controller@485c0100 {
 119                         compatible = "ti,am64-dmss-bcdma";
 120                         reg = <0x00 0x485c0100 0x00 0x100>,
 121                               <0x00 0x4c000000 0x00 0x20000>,
 122                               <0x00 0x4a820000 0x00 0x20000>,
 123                               <0x00 0x4aa40000 0x00 0x20000>,
 124                               <0x00 0x4bc00000 0x00 0x100000>,
 125                               <0x00 0x48600000 0x00 0x8000>,
 126                               <0x00 0x484a4000 0x00 0x2000>,
 127                               <0x00 0x484c2000 0x00 0x2000>,
 128                               <0x00 0x48420000 0x00 0x2000>;
 129                         reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
 130                                     "ring", "tchan", "rchan", "bchan";
 131                         msi-parent = <&inta_main_dmss>;
 132                         #dma-cells = <3>;
 133
 134                         ti,sci = <&dmsc>;
 135                         ti,sci-dev-id = <26>;
 136                         ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
 137                         ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
 138                         ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
 139                 };
 140
 141                 main_pktdma: dma-controller@485c0000 {
 142                         compatible = "ti,am64-dmss-pktdma";
 143                         reg = <0x00 0x485c0000 0x00 0x100>,
 144                               <0x00 0x4a800000 0x00 0x20000>,
 145                               <0x00 0x4aa00000 0x00 0x40000>,
 146                               <0x00 0x4b800000 0x00 0x400000>,
 147                               <0x00 0x485e0000 0x00 0x10000>,
 148                               <0x00 0x484a0000 0x00 0x2000>,
 149                               <0x00 0x484c0000 0x00 0x2000>,
 150                               <0x00 0x48430000 0x00 0x1000>;
 151                         reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
 152                                     "ring", "tchan", "rchan", "rflow";
 153                         msi-parent = <&inta_main_dmss>;
 154                         #dma-cells = <2>;
 155
 156                         ti,sci = <&dmsc>;
 157                         ti,sci-dev-id = <30>;
 158                         ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
 159                                                 <0x24>, /* CPSW_TX_CHAN */
 160                                                 <0x25>, /* SAUL_TX_0_CHAN */
 161                                                 <0x26>; /* SAUL_TX_1_CHAN */
 162                         ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
 163                                                 <0x11>, /* RING_CPSW_TX_CHAN */
 164                                                 <0x12>, /* RING_SAUL_TX_0_CHAN */
 165                                                 <0x13>; /* RING_SAUL_TX_1_CHAN */
 166                         ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
 167                                                 <0x2b>, /* CPSW_RX_CHAN */
 168                                                 <0x2d>, /* SAUL_RX_0_CHAN */
 169                                                 <0x2f>, /* SAUL_RX_1_CHAN */
 170                                                 <0x31>, /* SAUL_RX_2_CHAN */
 171                                                 <0x33>; /* SAUL_RX_3_CHAN */
 172                         ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
 173                                                 <0x2c>, /* FLOW_CPSW_RX_CHAN */
 174                                                 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
 175                                                 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
 176                 };
 177         };
 178
 179         dmsc: system-controller@44043000 {
 180                 bootph-all;
 181                 compatible = "ti,k2g-sci";
 182                 ti,host-id = <12>;
 183                 mbox-names = "rx", "tx";
 184                 mboxes = <&secure_proxy_main 12>,
 185                          <&secure_proxy_main 13>;
 186                 reg-names = "debug_messages";
 187                 reg = <0x00 0x44043000 0x00 0xfe0>;
 188
 189                 k3_pds: power-controller {
 190                         bootph-all;
 191                         compatible = "ti,sci-pm-domain";
 192                         #power-domain-cells = <2>;
 193                 };
 194
 195                 k3_clks: clock-controller {
 196                         bootph-all;
 197                         compatible = "ti,k2g-sci-clk";
 198                         #clock-cells = <2>;
 199                 };
 200
 201                 k3_reset: reset-controller {
 202                         bootph-all;
 203                         compatible = "ti,sci-reset";
 204                         #reset-cells = <2>;
 205                 };
 206         };
 207
 208         crypto: crypto@40900000 {
 209                 compatible = "ti,am62-sa3ul";
 210                 reg = <0x00 0x40900000 0x00 0x1200>;
 211                 #address-cells = <2>;
 212                 #size-cells = <2>;
 213                 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
 214
 215                 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
 216                        <&main_pktdma 0x7507 0>;
 217                 dma-names = "tx", "rx1", "rx2";
 218         };
 219
 220         secure_proxy_sa3: mailbox@43600000 {
 221                 bootph-pre-ram;
 222                 compatible = "ti,am654-secure-proxy";
 223                 #mbox-cells = <1>;
 224                 reg-names = "target_data", "rt", "scfg";
 225                 reg = <0x00 0x43600000 0x00 0x10000>,
 226                       <0x00 0x44880000 0x00 0x20000>,
 227                       <0x00 0x44860000 0x00 0x20000>;
 228                 /*
 229                  * Marked Disabled:
 230                  * Node is incomplete as it is meant for bootloaders and
 231                  * firmware on non-MPU processors
 232                  */
 233                 status = "disabled";
 234         };
 235
 236         main_pmx0: pinctrl@f4000 {
 237                 bootph-all;
 238                 compatible = "pinctrl-single";
 239                 reg = <0x00 0xf4000 0x00 0x2ac>;
 240                 #pinctrl-cells = <1>;
 241                 pinctrl-single,register-width = <32>;
 242                 pinctrl-single,function-mask = <0xffffffff>;
 243         };
 244
 245         main_esm: esm@420000 {
 246                 bootph-pre-ram;
 247                 compatible = "ti,j721e-esm";
 248                 reg = <0x00 0x420000 0x00 0x1000>;
 249                 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
 250         };
 251
 252         main_timer0: timer@2400000 {
 253                 bootph-all;
 254                 compatible = "ti,am654-timer";
 255                 reg = <0x00 0x2400000 0x00 0x400>;
 256                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 257                 clocks = <&k3_clks 36 2>;
 258                 clock-names = "fck";
 259                 assigned-clocks = <&k3_clks 36 2>;
 260                 assigned-clock-parents = <&k3_clks 36 3>;
 261                 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
 262                 ti,timer-pwm;
 263         };
 264
 265         main_timer1: timer@2410000 {
 266                 compatible = "ti,am654-timer";
 267                 reg = <0x00 0x2410000 0x00 0x400>;
 268                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&k3_clks 37 2>;
 270                 clock-names = "fck";
 271                 assigned-clocks = <&k3_clks 37 2>;
 272                 assigned-clock-parents = <&k3_clks 37 3>;
 273                 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
 274                 ti,timer-pwm;
 275         };
 276
 277         main_timer2: timer@2420000 {
 278                 compatible = "ti,am654-timer";
 279                 reg = <0x00 0x2420000 0x00 0x400>;
 280                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 281                 clocks = <&k3_clks 38 2>;
 282                 clock-names = "fck";
 283                 assigned-clocks = <&k3_clks 38 2>;
 284                 assigned-clock-parents = <&k3_clks 38 3>;
 285                 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
 286                 ti,timer-pwm;
 287         };
 288
 289         main_timer3: timer@2430000 {
 290                 compatible = "ti,am654-timer";
 291                 reg = <0x00 0x2430000 0x00 0x400>;
 292                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 293                 clocks = <&k3_clks 39 2>;
 294                 clock-names = "fck";
 295                 assigned-clocks = <&k3_clks 39 2>;
 296                 assigned-clock-parents = <&k3_clks 39 3>;
 297                 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
 298                 ti,timer-pwm;
 299         };
 300
 301         main_timer4: timer@2440000 {
 302                 compatible = "ti,am654-timer";
 303                 reg = <0x00 0x2440000 0x00 0x400>;
 304                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 305                 clocks = <&k3_clks 40 2>;
 306                 clock-names = "fck";
 307                 assigned-clocks = <&k3_clks 40 2>;
 308                 assigned-clock-parents = <&k3_clks 40 3>;
 309                 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
 310                 ti,timer-pwm;
 311         };
 312
 313         main_timer5: timer@2450000 {
 314                 compatible = "ti,am654-timer";
 315                 reg = <0x00 0x2450000 0x00 0x400>;
 316                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 317                 clocks = <&k3_clks 41 2>;
 318                 clock-names = "fck";
 319                 assigned-clocks = <&k3_clks 41 2>;
 320                 assigned-clock-parents = <&k3_clks 41 3>;
 321                 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
 322                 ti,timer-pwm;
 323         };
 324
 325         main_timer6: timer@2460000 {
 326                 compatible = "ti,am654-timer";
 327                 reg = <0x00 0x2460000 0x00 0x400>;
 328                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 329                 clocks = <&k3_clks 42 2>;
 330                 clock-names = "fck";
 331                 assigned-clocks = <&k3_clks 42 2>;
 332                 assigned-clock-parents = <&k3_clks 42 3>;
 333                 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
 334                 ti,timer-pwm;
 335         };
 336
 337         main_timer7: timer@2470000 {
 338                 compatible = "ti,am654-timer";
 339                 reg = <0x00 0x2470000 0x00 0x400>;
 340                 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 341                 clocks = <&k3_clks 43 2>;
 342                 clock-names = "fck";
 343                 assigned-clocks = <&k3_clks 43 2>;
 344                 assigned-clock-parents = <&k3_clks 43 3>;
 345                 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
 346                 ti,timer-pwm;
 347         };
 348
 349         main_uart0: serial@2800000 {
 350                 compatible = "ti,am64-uart", "ti,am654-uart";
 351                 reg = <0x00 0x02800000 0x00 0x100>;
 352                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 353                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 354                 clocks = <&k3_clks 146 0>;
 355                 clock-names = "fclk";
 356                 status = "disabled";
 357         };
 358
 359         main_uart1: serial@2810000 {
 360                 compatible = "ti,am64-uart", "ti,am654-uart";
 361                 reg = <0x00 0x02810000 0x00 0x100>;
 362                 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 363                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
 364                 clocks = <&k3_clks 152 0>;
 365                 clock-names = "fclk";
 366                 status = "disabled";
 367         };
 368
 369         main_uart2: serial@2820000 {
 370                 compatible = "ti,am64-uart", "ti,am654-uart";
 371                 reg = <0x00 0x02820000 0x00 0x100>;
 372                 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 373                 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
 374                 clocks = <&k3_clks 153 0>;
 375                 clock-names = "fclk";
 376                 status = "disabled";
 377         };
 378
 379         main_uart3: serial@2830000 {
 380                 compatible = "ti,am64-uart", "ti,am654-uart";
 381                 reg = <0x00 0x02830000 0x00 0x100>;
 382                 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
 383                 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
 384                 clocks = <&k3_clks 154 0>;
 385                 clock-names = "fclk";
 386                 status = "disabled";
 387         };
 388
 389         main_uart4: serial@2840000 {
 390                 compatible = "ti,am64-uart", "ti,am654-uart";
 391                 reg = <0x00 0x02840000 0x00 0x100>;
 392                 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
 393                 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
 394                 clocks = <&k3_clks 155 0>;
 395                 clock-names = "fclk";
 396                 status = "disabled";
 397         };
 398
 399         main_uart5: serial@2850000 {
 400                 compatible = "ti,am64-uart", "ti,am654-uart";
 401                 reg = <0x00 0x02850000 0x00 0x100>;
 402                 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 403                 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
 404                 clocks = <&k3_clks 156 0>;
 405                 clock-names = "fclk";
 406                 status = "disabled";
 407         };
 408
 409         main_uart6: serial@2860000 {
 410                 compatible = "ti,am64-uart", "ti,am654-uart";
 411                 reg = <0x00 0x02860000 0x00 0x100>;
 412                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 413                 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
 414                 clocks = <&k3_clks 158 0>;
 415                 clock-names = "fclk";
 416                 status = "disabled";
 417         };
 418
 419         main_i2c0: i2c@20000000 {
 420                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 421                 reg = <0x00 0x20000000 0x00 0x100>;
 422                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 423                 #address-cells = <1>;
 424                 #size-cells = <0>;
 425                 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 426                 clocks = <&k3_clks 102 2>;
 427                 clock-names = "fck";
 428                 status = "disabled";
 429         };
 430
 431         main_i2c1: i2c@20010000 {
 432                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 433                 reg = <0x00 0x20010000 0x00 0x100>;
 434                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 435                 #address-cells = <1>;
 436                 #size-cells = <0>;
 437                 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
 438                 clocks = <&k3_clks 103 2>;
 439                 clock-names = "fck";
 440                 status = "disabled";
 441         };
 442
 443         main_i2c2: i2c@20020000 {
 444                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 445                 reg = <0x00 0x20020000 0x00 0x100>;
 446                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
 450                 clocks = <&k3_clks 104 2>;
 451                 clock-names = "fck";
 452                 status = "disabled";
 453         };
 454
 455         main_i2c3: i2c@20030000 {
 456                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 457                 reg = <0x00 0x20030000 0x00 0x100>;
 458                 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 462                 clocks = <&k3_clks 105 2>;
 463                 clock-names = "fck";
 464                 status = "disabled";
 465         };
 466
 467         main_spi0: spi@20100000 {
 468                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
 469                 reg = <0x00 0x20100000 0x00 0x400>;
 470                 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 471                 #address-cells = <1>;
 472                 #size-cells = <0>;
 473                 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
 474                 clocks = <&k3_clks 141 0>;
 475                 status = "disabled";
 476         };
 477
 478         main_spi1: spi@20110000 {
 479                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 480                 reg = <0x00 0x20110000 0x00 0x400>;
 481                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 482                 #address-cells = <1>;
 483                 #size-cells = <0>;
 484                 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
 485                 clocks = <&k3_clks 142 0>;
 486                 status = "disabled";
 487         };
 488
 489         main_spi2: spi@20120000 {
 490                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 491                 reg = <0x00 0x20120000 0x00 0x400>;
 492                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 493                 #address-cells = <1>;
 494                 #size-cells = <0>;
 495                 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
 496                 clocks = <&k3_clks 143 0>;
 497                 status = "disabled";
 498         };
 499
 500         main_gpio_intr: interrupt-controller@a00000 {
 501                 compatible = "ti,sci-intr";
 502                 reg = <0x00 0x00a00000 0x00 0x800>;
 503                 ti,intr-trigger-type = <1>;
 504                 interrupt-controller;
 505                 interrupt-parent = <&gic500>;
 506                 #interrupt-cells = <1>;
 507                 ti,sci = <&dmsc>;
 508                 ti,sci-dev-id = <3>;
 509                 ti,interrupt-ranges = <0 32 16>;
 510         };
 511
 512         main_gpio0: gpio@600000 {
 513                 compatible = "ti,am64-gpio", "ti,keystone-gpio";
 514                 reg = <0x0 0x00600000 0x0 0x100>;
 515                 gpio-ranges = <&main_pmx0  0  0 32>,
 516                               <&main_pmx0 32 33 38>,
 517                               <&main_pmx0 70 72 22>;
 518                 gpio-controller;
 519                 #gpio-cells = <2>;
 520                 interrupt-parent = <&main_gpio_intr>;
 521                 interrupts = <190>, <191>, <192>,
 522                              <193>, <194>, <195>;
 523                 interrupt-controller;
 524                 #interrupt-cells = <2>;
 525                 ti,ngpio = <92>;
 526                 ti,davinci-gpio-unbanked = <0>;
 527                 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
 528                 clocks = <&k3_clks 77 0>;
 529                 clock-names = "gpio";
 530         };
 531
 532         main_gpio1: gpio@601000 {
 533                 compatible = "ti,am64-gpio", "ti,keystone-gpio";
 534                 reg = <0x0 0x00601000 0x0 0x100>;
 535                 gpio-controller;
 536                 gpio-ranges = <&main_pmx0  0  94 41>,
 537                               <&main_pmx0 41 136  6>,
 538                               <&main_pmx0 47 143  3>,
 539                               <&main_pmx0 50 149  2>;
 540                 #gpio-cells = <2>;
 541                 interrupt-parent = <&main_gpio_intr>;
 542                 interrupts = <180>, <181>, <182>,
 543                              <183>, <184>, <185>;
 544                 interrupt-controller;
 545                 #interrupt-cells = <2>;
 546                 ti,ngpio = <52>;
 547                 ti,davinci-gpio-unbanked = <0>;
 548                 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
 549                 clocks = <&k3_clks 78 0>;
 550                 clock-names = "gpio";
 551         };
 552
 553         sdhci0: mmc@fa10000 {
 554                 compatible = "ti,am62-sdhci";
 555                 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
 556                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 557                 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
 558                 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
 559                 clock-names = "clk_ahb", "clk_xin";
 560                 assigned-clocks = <&k3_clks 57 6>;
 561                 assigned-clock-parents = <&k3_clks 57 8>;
 562                 mmc-ddr-1_8v;
 563                 mmc-hs200-1_8v;
 564                 ti,trm-icp = <0x2>;
 565                 bus-width = <8>;
 566                 ti,clkbuf-sel = <0x7>;
 567                 ti,otap-del-sel-legacy = <0x0>;
 568                 ti,otap-del-sel-mmc-hs = <0x0>;
 569                 ti,otap-del-sel-ddr52 = <0x5>;
 570                 ti,otap-del-sel-hs200 = <0x5>;
 571                 ti,itap-del-sel-legacy = <0xa>;
 572                 ti,itap-del-sel-mmc-hs = <0x1>;
 573                 status = "disabled";
 574         };
 575
 576         sdhci1: mmc@fa00000 {
 577                 compatible = "ti,am62-sdhci";
 578                 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
 579                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 580                 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
 581                 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
 582                 clock-names = "clk_ahb", "clk_xin";
 583                 ti,trm-icp = <0x2>;
 584                 ti,otap-del-sel-legacy = <0x8>;
 585                 ti,otap-del-sel-sd-hs = <0x0>;
 586                 ti,otap-del-sel-sdr12 = <0x0>;
 587                 ti,otap-del-sel-sdr25 = <0x0>;
 588                 ti,otap-del-sel-sdr50 = <0x8>;
 589                 ti,otap-del-sel-sdr104 = <0x7>;
 590                 ti,otap-del-sel-ddr50 = <0x4>;
 591                 ti,itap-del-sel-legacy = <0xa>;
 592                 ti,itap-del-sel-sd-hs = <0x1>;
 593                 ti,itap-del-sel-sdr12 = <0xa>;
 594                 ti,itap-del-sel-sdr25 = <0x1>;
 595                 ti,clkbuf-sel = <0x7>;
 596                 bus-width = <4>;
 597                 status = "disabled";
 598         };
 599
 600         sdhci2: mmc@fa20000 {
 601                 compatible = "ti,am62-sdhci";
 602                 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
 603                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 604                 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
 605                 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
 606                 clock-names = "clk_ahb", "clk_xin";
 607                 ti,trm-icp = <0x2>;
 608                 ti,otap-del-sel-legacy = <0x8>;
 609                 ti,otap-del-sel-sd-hs = <0x0>;
 610                 ti,otap-del-sel-sdr12 = <0x0>;
 611                 ti,otap-del-sel-sdr25 = <0x0>;
 612                 ti,otap-del-sel-sdr50 = <0x8>;
 613                 ti,otap-del-sel-sdr104 = <0x7>;
 614                 ti,otap-del-sel-ddr50 = <0x8>;
 615                 ti,itap-del-sel-legacy = <0xa>;
 616                 ti,itap-del-sel-sd-hs = <0xa>;
 617                 ti,itap-del-sel-sdr12 = <0xa>;
 618                 ti,itap-del-sel-sdr25 = <0x1>;
 619                 ti,clkbuf-sel = <0x7>;
 620                 status = "disabled";
 621         };
 622
 623         usbss0: dwc3-usb@f900000 {
 624                 compatible = "ti,am62-usb";
 625                 reg = <0x00 0x0f900000 0x00 0x800>;
 626                 clocks = <&k3_clks 161 3>;
 627                 clock-names = "ref";
 628                 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
 629                 #address-cells = <2>;
 630                 #size-cells = <2>;
 631                 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
 632                 ranges;
 633                 status = "disabled";
 634
 635                 usb0: usb@31000000 {
 636                         compatible = "snps,dwc3";
 637                         reg = <0x00 0x31000000 0x00 0x50000>;
 638                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
 639                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
 640                         interrupt-names = "host", "peripheral";
 641                         maximum-speed = "high-speed";
 642                         dr_mode = "otg";
 643                 };
 644         };
 645
 646         usbss1: dwc3-usb@f910000 {
 647                 compatible = "ti,am62-usb";
 648                 reg = <0x00 0x0f910000 0x00 0x800>;
 649                 clocks = <&k3_clks 162 3>;
 650                 clock-names = "ref";
 651                 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
 652                 #address-cells = <2>;
 653                 #size-cells = <2>;
 654                 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
 655                 ranges;
 656                 status = "disabled";
 657
 658                 usb1: usb@31100000 {
 659                         compatible = "snps,dwc3";
 660                         reg = <0x00 0x31100000 0x00 0x50000>;
 661                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
 662                                      <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
 663                         interrupt-names = "host", "peripheral";
 664                         maximum-speed = "high-speed";
 665                         dr_mode = "otg";
 666                 };
 667         };
 668
 669         fss: bus@fc00000 {
 670                 compatible = "simple-bus";
 671                 reg = <0x00 0x0fc00000 0x00 0x70000>;
 672                 #address-cells = <2>;
 673                 #size-cells = <2>;
 674                 ranges;
 675
 676                 ospi0: spi@fc40000 {
 677                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 678                         reg = <0x00 0x0fc40000 0x00 0x100>,
 679                               <0x05 0x00000000 0x01 0x00000000>;
 680                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 681                         cdns,fifo-depth = <256>;
 682                         cdns,fifo-width = <4>;
 683                         cdns,trigger-address = <0x0>;
 684                         clocks = <&k3_clks 75 7>;
 685                         assigned-clocks = <&k3_clks 75 7>;
 686                         assigned-clock-parents = <&k3_clks 75 8>;
 687                         assigned-clock-rates = <166666666>;
 688                         power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
 689                         #address-cells = <1>;
 690                         #size-cells = <0>;
 691                         status = "disabled";
 692                 };
 693         };
 694
 695         gpu: gpu@fd00000 {
 696                 compatible = "ti,am62-gpu", "img,img-axe";
 697                 reg = <0x00 0x0fd00000 0x00 0x20000>;
 698                 clocks = <&k3_clks 187 0>;
 699                 clock-names = "core";
 700                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 701                 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
 702         };
 703
 704         cpsw3g: ethernet@8000000 {
 705                 compatible = "ti,am642-cpsw-nuss";
 706                 #address-cells = <2>;
 707                 #size-cells = <2>;
 708                 reg = <0x00 0x08000000 0x00 0x200000>;
 709                 reg-names = "cpsw_nuss";
 710                 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
 711                 clocks = <&k3_clks 13 0>;
 712                 assigned-clocks = <&k3_clks 13 3>;
 713                 assigned-clock-parents = <&k3_clks 13 11>;
 714                 clock-names = "fck";
 715                 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
 716
 717                 dmas = <&main_pktdma 0xc600 15>,
 718                        <&main_pktdma 0xc601 15>,
 719                        <&main_pktdma 0xc602 15>,
 720                        <&main_pktdma 0xc603 15>,
 721                        <&main_pktdma 0xc604 15>,
 722                        <&main_pktdma 0xc605 15>,
 723                        <&main_pktdma 0xc606 15>,
 724                        <&main_pktdma 0xc607 15>,
 725                        <&main_pktdma 0x4600 15>;
 726                 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
 727                             "tx7", "rx";
 728
 729                 ethernet-ports {
 730                         #address-cells = <1>;
 731                         #size-cells = <0>;
 732
 733                         cpsw_port1: port@1 {
 734                                 reg = <1>;
 735                                 ti,mac-only;
 736                                 label = "port1";
 737                                 phys = <&phy_gmii_sel 1>;
 738                                 mac-address = [00 00 00 00 00 00];
 739                                 ti,syscon-efuse = <&wkup_conf 0x200>;
 740                         };
 741
 742                         cpsw_port2: port@2 {
 743                                 reg = <2>;
 744                                 ti,mac-only;
 745                                 label = "port2";
 746                                 phys = <&phy_gmii_sel 2>;
 747                                 mac-address = [00 00 00 00 00 00];
 748                         };
 749                 };
 750
 751                 cpsw3g_mdio: mdio@f00 {
 752                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 753                         reg = <0x00 0xf00 0x00 0x100>;
 754                         #address-cells = <1>;
 755                         #size-cells = <0>;
 756                         clocks = <&k3_clks 13 0>;
 757                         clock-names = "fck";
 758                         bus_freq = <1000000>;
 759                         status = "disabled";
 760                 };
 761
 762                 cpts@3d000 {
 763                         compatible = "ti,j721e-cpts";
 764                         reg = <0x00 0x3d000 0x00 0x400>;
 765                         clocks = <&k3_clks 13 3>;
 766                         clock-names = "cpts";
 767                         interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 768                         interrupt-names = "cpts";
 769                         ti,cpts-ext-ts-inputs = <4>;
 770                         ti,cpts-periodic-outputs = <2>;
 771                 };
 772         };
 773
 774         dss: dss@30200000 {
 775                 compatible = "ti,am625-dss";
 776                 reg = <0x00 0x30200000 0x00 0x1000>, /* common */
 777                       <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
 778                       <0x00 0x30206000 0x00 0x1000>, /* vid */
 779                       <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
 780                       <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
 781                       <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
 782                       <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */
 783                 reg-names = "common", "vidl1", "vid",
 784                             "ovr1", "ovr2", "vp1", "vp2";
 785                 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
 786                 clocks = <&k3_clks 186 6>,
 787                          <&dss_vp1_clk>,
 788                          <&k3_clks 186 2>;
 789                 clock-names = "fck", "vp1", "vp2";
 790                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 791                 status = "disabled";
 792
 793                 dss_ports: ports {
 794                         #address-cells = <1>;
 795                         #size-cells = <0>;
 796                 };
 797         };
 798
 799         hwspinlock: spinlock@2a000000 {
 800                 compatible = "ti,am64-hwspinlock";
 801                 reg = <0x00 0x2a000000 0x00 0x1000>;
 802                 #hwlock-cells = <1>;
 803         };
 804
 805         mailbox0_cluster0: mailbox@29000000 {
 806                 compatible = "ti,am64-mailbox";
 807                 reg = <0x00 0x29000000 0x00 0x200>;
 808                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 809                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 810                 #mbox-cells = <1>;
 811                 ti,mbox-num-users = <4>;
 812                 ti,mbox-num-fifos = <16>;
 813         };
 814
 815         ecap0: pwm@23100000 {
 816                 compatible = "ti,am3352-ecap";
 817                 #pwm-cells = <3>;
 818                 reg = <0x00 0x23100000 0x00 0x100>;
 819                 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
 820                 clocks = <&k3_clks 51 0>;
 821                 clock-names = "fck";
 822                 status = "disabled";
 823         };
 824
 825         ecap1: pwm@23110000 {
 826                 compatible = "ti,am3352-ecap";
 827                 #pwm-cells = <3>;
 828                 reg = <0x00 0x23110000 0x00 0x100>;
 829                 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
 830                 clocks = <&k3_clks 52 0>;
 831                 clock-names = "fck";
 832                 status = "disabled";
 833         };
 834
 835         ecap2: pwm@23120000 {
 836                 compatible = "ti,am3352-ecap";
 837                 #pwm-cells = <3>;
 838                 reg = <0x00 0x23120000 0x00 0x100>;
 839                 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
 840                 clocks = <&k3_clks 53 0>;
 841                 clock-names = "fck";
 842                 status = "disabled";
 843         };
 844
 845         main_mcan0: can@20701000 {
 846                 compatible = "bosch,m_can";
 847                 reg = <0x00 0x20701000 0x00 0x200>,
 848                       <0x00 0x20708000 0x00 0x8000>;
 849                 reg-names = "m_can", "message_ram";
 850                 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
 851                 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
 852                 clock-names = "hclk", "cclk";
 853                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 854                              <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 855                 interrupt-names = "int0", "int1";
 856                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 857                 status = "disabled";
 858         };
 859
 860         main_rti0: watchdog@e000000 {
 861                 compatible = "ti,j7-rti-wdt";
 862                 reg = <0x00 0x0e000000 0x00 0x100>;
 863                 clocks = <&k3_clks 125 0>;
 864                 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
 865                 assigned-clocks = <&k3_clks 125 0>;
 866                 assigned-clock-parents = <&k3_clks 125 2>;
 867         };
 868
 869         main_rti1: watchdog@e010000 {
 870                 compatible = "ti,j7-rti-wdt";
 871                 reg = <0x00 0x0e010000 0x00 0x100>;
 872                 clocks = <&k3_clks 126 0>;
 873                 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
 874                 assigned-clocks = <&k3_clks 126 0>;
 875                 assigned-clock-parents = <&k3_clks 126 2>;
 876         };
 877
 878         main_rti2: watchdog@e020000 {
 879                 compatible = "ti,j7-rti-wdt";
 880                 reg = <0x00 0x0e020000 0x00 0x100>;
 881                 clocks = <&k3_clks 127 0>;
 882                 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
 883                 assigned-clocks = <&k3_clks 127 0>;
 884                 assigned-clock-parents = <&k3_clks 127 2>;
 885         };
 886
 887         main_rti3: watchdog@e030000 {
 888                 compatible = "ti,j7-rti-wdt";
 889                 reg = <0x00 0x0e030000 0x00 0x100>;
 890                 clocks = <&k3_clks 128 0>;
 891                 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
 892                 assigned-clocks = <&k3_clks 128 0>;
 893                 assigned-clock-parents = <&k3_clks 128 2>;
 894         };
 895
 896         main_rti15: watchdog@e0f0000 {
 897                 compatible = "ti,j7-rti-wdt";
 898                 reg = <0x00 0x0e0f0000 0x00 0x100>;
 899                 clocks = <&k3_clks 130 0>;
 900                 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>;
 901                 assigned-clocks = <&k3_clks 130 0>;
 902                 assigned-clock-parents = <&k3_clks 130 2>;
 903         };
 904
 905         epwm0: pwm@23000000 {
 906                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 907                 #pwm-cells = <3>;
 908                 reg = <0x00 0x23000000 0x00 0x100>;
 909                 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
 910                 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
 911                 clock-names = "tbclk", "fck";
 912                 status = "disabled";
 913         };
 914
 915         epwm1: pwm@23010000 {
 916                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 917                 #pwm-cells = <3>;
 918                 reg = <0x00 0x23010000 0x00 0x100>;
 919                 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
 920                 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
 921                 clock-names = "tbclk", "fck";
 922                 status = "disabled";
 923         };
 924
 925         epwm2: pwm@23020000 {
 926                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 927                 #pwm-cells = <3>;
 928                 reg = <0x00 0x23020000 0x00 0x100>;
 929                 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
 930                 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
 931                 clock-names = "tbclk", "fck";
 932                 status = "disabled";
 933         };
 934
 935         mcasp0: audio-controller@2b00000 {
 936                 compatible = "ti,am33xx-mcasp-audio";
 937                 reg = <0x00 0x02b00000 0x00 0x2000>,
 938                       <0x00 0x02b08000 0x00 0x400>;
 939                 reg-names = "mpu", "dat";
 940                 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
 941                              <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
 942                 interrupt-names = "tx", "rx";
 943
 944                 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
 945                 dma-names = "tx", "rx";
 946
 947                 clocks = <&k3_clks 190 0>;
 948                 clock-names = "fck";
 949                 assigned-clocks = <&k3_clks 190 0>;
 950                 assigned-clock-parents = <&k3_clks 190 2>;
 951                 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
 952                 status = "disabled";
 953         };
 954
 955         mcasp1: audio-controller@2b10000 {
 956                 compatible = "ti,am33xx-mcasp-audio";
 957                 reg = <0x00 0x02b10000 0x00 0x2000>,
 958                       <0x00 0x02b18000 0x00 0x400>;
 959                 reg-names = "mpu", "dat";
 960                 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 961                              <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
 962                 interrupt-names = "tx", "rx";
 963
 964                 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
 965                 dma-names = "tx", "rx";
 966
 967                 clocks = <&k3_clks 191 0>;
 968                 clock-names = "fck";
 969                 assigned-clocks = <&k3_clks 191 0>;
 970                 assigned-clock-parents = <&k3_clks 191 2>;
 971                 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
 972                 status = "disabled";
 973         };
 974
 975         mcasp2: audio-controller@2b20000 {
 976                 compatible = "ti,am33xx-mcasp-audio";
 977                 reg = <0x00 0x02b20000 0x00 0x2000>,
 978                       <0x00 0x02b28000 0x00 0x400>;
 979                 reg-names = "mpu", "dat";
 980                 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
 981                              <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 982                 interrupt-names = "tx", "rx";
 983
 984                 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
 985                 dma-names = "tx", "rx";
 986
 987                 clocks = <&k3_clks 192 0>;
 988                 clock-names = "fck";
 989                 assigned-clocks = <&k3_clks 192 0>;
 990                 assigned-clock-parents = <&k3_clks 192 2>;
 991                 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
 992                 status = "disabled";
 993         };
 994
 995         ti_csi2rx0: ticsi2rx@30102000 {
 996                 compatible = "ti,j721e-csi2rx-shim";
 997                 dmas = <&main_bcdma 0 0x4700 0>;
 998                 dma-names = "rx0";
 999                 reg = <0x00 0x30102000 0x00 0x1000>;
1000                 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1001                 #address-cells = <2>;
1002                 #size-cells = <2>;
1003                 ranges;
1004                 status = "disabled";
1005
1006                 cdns_csi2rx0: csi-bridge@30101000 {
1007                         compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1008                         reg = <0x00 0x30101000 0x00 0x1000>;
1009                         clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
1010                                 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
1011                         clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1012                                 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
1013                         phys = <&dphy0>;
1014                         phy-names = "dphy";
1015
1016                         ports {
1017                                 #address-cells = <1>;
1018                                 #size-cells = <0>;
1019
1020                                 csi0_port0: port@0 {
1021                                         reg = <0>;
1022                                         status = "disabled";
1023                                 };
1024
1025                                 csi0_port1: port@1 {
1026                                         reg = <1>;
1027                                         status = "disabled";
1028                                 };
1029
1030                                 csi0_port2: port@2 {
1031                                         reg = <2>;
1032                                         status = "disabled";
1033                                 };
1034
1035                                 csi0_port3: port@3 {
1036                                         reg = <3>;
1037                                         status = "disabled";
1038                                 };
1039
1040                                 csi0_port4: port@4 {
1041                                         reg = <4>;
1042                                         status = "disabled";
1043                                 };
1044                         };
1045                 };
1046         };
1047
1048         dphy0: phy@30110000 {
1049                 compatible = "cdns,dphy-rx";
1050                 reg = <0x00 0x30110000 0x00 0x1100>;
1051                 #phy-cells = <0>;
1052                 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1053                 status = "disabled";
1054         };
1055
1056 };