2 * Device Tree Source for UniPhier PH1-LD20 SoC
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 /memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
48 compatible = "socionext,ph1-ld20";
51 interrupt-parent = <&gic>;
79 compatible = "arm,cortex-a72", "arm,armv8";
81 enable-method = "spin-table";
82 cpu-release-addr = <0 0x80000000>;
87 compatible = "arm,cortex-a72", "arm,armv8";
89 enable-method = "spin-table";
90 cpu-release-addr = <0 0x80000000>;
95 compatible = "arm,cortex-a53", "arm,armv8";
97 enable-method = "spin-table";
98 cpu-release-addr = <0 0x80000000>;
103 compatible = "arm,cortex-a53", "arm,armv8";
105 enable-method = "spin-table";
106 cpu-release-addr = <0 0x80000000>;
112 compatible = "fixed-clock";
114 clock-frequency = <25000000>;
119 compatible = "fixed-clock";
120 clock-frequency = <58820000>;
125 compatible = "fixed-clock";
126 clock-frequency = <50000000>;
131 compatible = "arm,armv8-timer";
132 interrupts = <1 13 4>,
139 compatible = "simple-bus";
140 #address-cells = <1>;
142 ranges = <0 0 0 0xffffffff>;
144 serial0: serial@54006800 {
145 compatible = "socionext,uniphier-uart";
147 reg = <0x54006800 0x40>;
148 interrupts = <0 33 4>;
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_uart0>;
151 clocks = <&uart_clk>;
154 serial1: serial@54006900 {
155 compatible = "socionext,uniphier-uart";
157 reg = <0x54006900 0x40>;
158 interrupts = <0 35 4>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_uart1>;
161 clocks = <&uart_clk>;
164 serial2: serial@54006a00 {
165 compatible = "socionext,uniphier-uart";
167 reg = <0x54006a00 0x40>;
168 interrupts = <0 37 4>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_uart2>;
171 clocks = <&uart_clk>;
174 serial3: serial@54006b00 {
175 compatible = "socionext,uniphier-uart";
177 reg = <0x54006b00 0x40>;
178 interrupts = <0 177 4>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_uart3>;
181 clocks = <&uart_clk>;
185 compatible = "socionext,uniphier-fi2c";
187 reg = <0x58780000 0x80>;
188 #address-cells = <1>;
190 interrupts = <0 41 4>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_i2c0>;
194 clock-frequency = <100000>;
198 compatible = "socionext,uniphier-fi2c";
200 reg = <0x58781000 0x80>;
201 #address-cells = <1>;
203 interrupts = <0 42 4>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_i2c1>;
207 clock-frequency = <100000>;
211 compatible = "socionext,uniphier-fi2c";
212 reg = <0x58782000 0x80>;
213 #address-cells = <1>;
215 interrupts = <0 43 4>;
217 clock-frequency = <400000>;
221 compatible = "socionext,uniphier-fi2c";
223 reg = <0x58783000 0x80>;
224 #address-cells = <1>;
226 interrupts = <0 44 4>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_i2c3>;
230 clock-frequency = <100000>;
234 compatible = "socionext,uniphier-fi2c";
236 reg = <0x58784000 0x80>;
237 #address-cells = <1>;
239 interrupts = <0 45 4>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_i2c4>;
243 clock-frequency = <100000>;
247 compatible = "socionext,uniphier-fi2c";
248 reg = <0x58785000 0x80>;
249 #address-cells = <1>;
251 interrupts = <0 25 4>;
253 clock-frequency = <400000>;
256 system_bus: system-bus@58c00000 {
257 compatible = "socionext,uniphier-system-bus";
259 reg = <0x58c00000 0x400>;
260 #address-cells = <2>;
265 compatible = "socionext,uniphier-smpctrl";
266 reg = <0x59801000 0x400>;
270 compatible = "simple-mfd", "syscon";
271 reg = <0x5f800000 0x2000>;
274 compatible = "socionext,uniphier-ld20-pinctrl";
278 gic: interrupt-controller@5fe00000 {
279 compatible = "arm,gic-v3";
280 reg = <0x5fe00000 0x10000>, /* GICD */
281 <0x5fe80000 0x80000>; /* GICR */
282 interrupt-controller;
283 #interrupt-cells = <3>;
284 interrupts = <1 9 4>;
289 /include/ "uniphier-pinctrl.dtsi"