1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD11 SoC
5 // Copyright (C) 2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
11 /memreserve/ 0x80000000 0x02000000;
14 compatible = "socionext,uniphier-ld11";
17 interrupt-parent = <&gic>;
36 compatible = "arm,cortex-a53", "arm,armv8";
38 clocks = <&sys_clk 33>;
39 enable-method = "psci";
40 operating-points-v2 = <&cluster0_opp>;
45 compatible = "arm,cortex-a53", "arm,armv8";
47 clocks = <&sys_clk 33>;
48 enable-method = "psci";
49 operating-points-v2 = <&cluster0_opp>;
53 cluster0_opp: opp-table {
54 compatible = "operating-points-v2";
58 opp-hz = /bits/ 64 <245000000>;
59 clock-latency-ns = <300>;
62 opp-hz = /bits/ 64 <250000000>;
63 clock-latency-ns = <300>;
66 opp-hz = /bits/ 64 <490000000>;
67 clock-latency-ns = <300>;
70 opp-hz = /bits/ 64 <500000000>;
71 clock-latency-ns = <300>;
74 opp-hz = /bits/ 64 <653334000>;
75 clock-latency-ns = <300>;
78 opp-hz = /bits/ 64 <666667000>;
79 clock-latency-ns = <300>;
82 opp-hz = /bits/ 64 <980000000>;
83 clock-latency-ns = <300>;
88 compatible = "arm,psci-1.0";
94 compatible = "fixed-clock";
96 clock-frequency = <25000000>;
100 emmc_pwrseq: emmc-pwrseq {
101 compatible = "mmc-pwrseq-emmc";
102 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
106 compatible = "arm,armv8-timer";
107 interrupts = <1 13 4>,
114 compatible = "simple-bus";
115 #address-cells = <1>;
117 ranges = <0 0 0 0xffffffff>;
119 serial0: serial@54006800 {
120 compatible = "socionext,uniphier-uart";
122 reg = <0x54006800 0x40>;
123 interrupts = <0 33 4>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_uart0>;
126 clocks = <&peri_clk 0>;
127 resets = <&peri_rst 0>;
130 serial1: serial@54006900 {
131 compatible = "socionext,uniphier-uart";
133 reg = <0x54006900 0x40>;
134 interrupts = <0 35 4>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_uart1>;
137 clocks = <&peri_clk 1>;
138 resets = <&peri_rst 1>;
141 serial2: serial@54006a00 {
142 compatible = "socionext,uniphier-uart";
144 reg = <0x54006a00 0x40>;
145 interrupts = <0 37 4>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_uart2>;
148 clocks = <&peri_clk 2>;
149 resets = <&peri_rst 2>;
152 serial3: serial@54006b00 {
153 compatible = "socionext,uniphier-uart";
155 reg = <0x54006b00 0x40>;
156 interrupts = <0 177 4>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_uart3>;
159 clocks = <&peri_clk 3>;
160 resets = <&peri_rst 3>;
163 gpio: gpio@55000000 {
164 compatible = "socionext,uniphier-gpio";
165 reg = <0x55000000 0x200>;
166 interrupt-parent = <&aidet>;
167 interrupt-controller;
168 #interrupt-cells = <2>;
171 gpio-ranges = <&pinctrl 0 0 0>,
177 gpio-ranges-group-names = "gpio_range0",
184 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
189 compatible = "socionext,uniphier-ld11-aio";
190 reg = <0x56000000 0x80000>;
191 interrupts = <0 144 4>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_aout1>,
196 clocks = <&sys_clk 40>;
198 resets = <&sys_rst 40>;
199 #sound-dai-cells = <1>;
200 socionext,syscon = <&soc_glue>;
208 i2s_pcmin2: endpoint {
215 remote-endpoint = <&evea_line>;
220 i2s_hpcmout1: endpoint {
227 remote-endpoint = <&evea_hp>;
231 spdif_port0: port@5 {
232 spdif_hiecout1: endpoint {
237 i2s_epcmout2: endpoint {
242 i2s_epcmout3: endpoint {
246 comp_spdif_port0: port@8 {
247 comp_spdif_hiecout1: endpoint {
253 compatible = "socionext,uniphier-evea";
254 reg = <0x57900000 0x1000>;
255 clock-names = "evea", "exiv";
256 clocks = <&sys_clk 41>, <&sys_clk 42>;
257 reset-names = "evea", "exiv", "adamv";
258 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
259 #sound-dai-cells = <1>;
262 evea_line: endpoint {
263 remote-endpoint = <&i2s_line>;
269 remote-endpoint = <&i2s_hp>;
275 compatible = "socionext,uniphier-ld11-adamv",
276 "simple-mfd", "syscon";
277 reg = <0x57920000 0x1000>;
280 compatible = "socionext,uniphier-ld11-adamv-reset";
286 compatible = "socionext,uniphier-fi2c";
288 reg = <0x58780000 0x80>;
289 #address-cells = <1>;
291 interrupts = <0 41 4>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_i2c0>;
294 clocks = <&peri_clk 4>;
295 resets = <&peri_rst 4>;
296 clock-frequency = <100000>;
300 compatible = "socionext,uniphier-fi2c";
302 reg = <0x58781000 0x80>;
303 #address-cells = <1>;
305 interrupts = <0 42 4>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_i2c1>;
308 clocks = <&peri_clk 5>;
309 resets = <&peri_rst 5>;
310 clock-frequency = <100000>;
314 compatible = "socionext,uniphier-fi2c";
315 reg = <0x58782000 0x80>;
316 #address-cells = <1>;
318 interrupts = <0 43 4>;
319 clocks = <&peri_clk 6>;
320 resets = <&peri_rst 6>;
321 clock-frequency = <400000>;
325 compatible = "socionext,uniphier-fi2c";
327 reg = <0x58783000 0x80>;
328 #address-cells = <1>;
330 interrupts = <0 44 4>;
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_i2c3>;
333 clocks = <&peri_clk 7>;
334 resets = <&peri_rst 7>;
335 clock-frequency = <100000>;
339 compatible = "socionext,uniphier-fi2c";
341 reg = <0x58784000 0x80>;
342 #address-cells = <1>;
344 interrupts = <0 45 4>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_i2c4>;
347 clocks = <&peri_clk 8>;
348 resets = <&peri_rst 8>;
349 clock-frequency = <100000>;
353 compatible = "socionext,uniphier-fi2c";
354 reg = <0x58785000 0x80>;
355 #address-cells = <1>;
357 interrupts = <0 25 4>;
358 clocks = <&peri_clk 9>;
359 resets = <&peri_rst 9>;
360 clock-frequency = <400000>;
363 system_bus: system-bus@58c00000 {
364 compatible = "socionext,uniphier-system-bus";
366 reg = <0x58c00000 0x400>;
367 #address-cells = <2>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_system_bus>;
374 compatible = "socionext,uniphier-smpctrl";
375 reg = <0x59801000 0x400>;
379 compatible = "socionext,uniphier-ld11-sdctrl",
380 "simple-mfd", "syscon";
381 reg = <0x59810000 0x400>;
384 compatible = "socionext,uniphier-ld11-sd-reset";
390 compatible = "socionext,uniphier-ld11-perictrl",
391 "simple-mfd", "syscon";
392 reg = <0x59820000 0x200>;
395 compatible = "socionext,uniphier-ld11-peri-clock";
400 compatible = "socionext,uniphier-ld11-peri-reset";
405 emmc: sdhc@5a000000 {
406 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
407 reg = <0x5a000000 0x400>;
408 interrupts = <0 78 4>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_emmc>;
411 clocks = <&sys_clk 4>;
412 resets = <&sys_rst 4>;
416 mmc-pwrseq = <&emmc_pwrseq>;
417 cdns,phy-input-delay-legacy = <9>;
418 cdns,phy-input-delay-mmc-highspeed = <2>;
419 cdns,phy-input-delay-mmc-ddr = <3>;
420 cdns,phy-dll-delay-sdclk = <21>;
421 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
425 compatible = "socionext,uniphier-ehci", "generic-ehci";
427 reg = <0x5a800100 0x100>;
428 interrupts = <0 243 4>;
429 pinctrl-names = "default";
430 pinctrl-0 = <&pinctrl_usb0>;
431 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
433 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
435 has-transaction-translator;
439 compatible = "socionext,uniphier-ehci", "generic-ehci";
441 reg = <0x5a810100 0x100>;
442 interrupts = <0 244 4>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_usb1>;
445 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
447 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
449 has-transaction-translator;
453 compatible = "socionext,uniphier-ehci", "generic-ehci";
455 reg = <0x5a820100 0x100>;
456 interrupts = <0 245 4>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&pinctrl_usb2>;
459 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
461 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
463 has-transaction-translator;
467 compatible = "socionext,uniphier-ld11-mioctrl",
468 "simple-mfd", "syscon";
469 reg = <0x5b3e0000 0x800>;
472 compatible = "socionext,uniphier-ld11-mio-clock";
477 compatible = "socionext,uniphier-ld11-mio-reset";
479 resets = <&sys_rst 7>;
483 soc_glue: soc-glue@5f800000 {
484 compatible = "socionext,uniphier-ld11-soc-glue",
485 "simple-mfd", "syscon";
486 reg = <0x5f800000 0x2000>;
489 compatible = "socionext,uniphier-ld11-pinctrl";
494 compatible = "socionext,uniphier-ld11-soc-glue-debug",
496 #address-cells = <1>;
498 ranges = <0 0x5f900000 0x2000>;
501 compatible = "socionext,uniphier-efuse";
506 compatible = "socionext,uniphier-efuse";
511 aidet: aidet@5fc20000 {
512 compatible = "socionext,uniphier-ld11-aidet";
513 reg = <0x5fc20000 0x200>;
514 interrupt-controller;
515 #interrupt-cells = <2>;
518 gic: interrupt-controller@5fe00000 {
519 compatible = "arm,gic-v3";
520 reg = <0x5fe00000 0x10000>, /* GICD */
521 <0x5fe40000 0x80000>; /* GICR */
522 interrupt-controller;
523 #interrupt-cells = <3>;
524 interrupts = <1 9 4>;
528 compatible = "socionext,uniphier-ld11-sysctrl",
529 "simple-mfd", "syscon";
530 reg = <0x61840000 0x10000>;
533 compatible = "socionext,uniphier-ld11-clock";
538 compatible = "socionext,uniphier-ld11-reset";
543 compatible = "socionext,uniphier-wdt";
547 eth: ethernet@65000000 {
548 compatible = "socionext,uniphier-ld11-ave4";
550 reg = <0x65000000 0x8500>;
551 interrupts = <0 66 4>;
552 clock-names = "ether";
553 clocks = <&sys_clk 6>;
554 reset-names = "ether";
555 resets = <&sys_rst 6>;
556 phy-mode = "internal";
557 local-mac-address = [00 00 00 00 00 00];
558 socionext,syscon-phy-mode = <&soc_glue 0>;
561 #address-cells = <1>;
566 nand: nand@68000000 {
567 compatible = "socionext,uniphier-denali-nand-v5b";
569 reg-names = "nand_data", "denali_reg";
570 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
571 interrupts = <0 65 4>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&pinctrl_nand>;
574 clocks = <&sys_clk 2>;
575 resets = <&sys_rst 2>;
580 #include "uniphier-pinctrl.dtsi"
583 drive-strength = <4>; /* default: 4mA */
587 drive-strength = <8>; /* 8mA */