1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 compatible = "rockchip,rk3328";
18 interrupt-parent = <&gic>;
31 ethernet1 = &gmac2phy;
40 compatible = "arm,cortex-a53", "arm,armv8";
42 clocks = <&cru ARMCLK>;
44 dynamic-power-coefficient = <120>;
45 enable-method = "psci";
46 next-level-cache = <&l2>;
47 operating-points-v2 = <&cpu0_opp_table>;
52 compatible = "arm,cortex-a53", "arm,armv8";
54 clocks = <&cru ARMCLK>;
56 dynamic-power-coefficient = <120>;
57 enable-method = "psci";
58 next-level-cache = <&l2>;
59 operating-points-v2 = <&cpu0_opp_table>;
64 compatible = "arm,cortex-a53", "arm,armv8";
66 clocks = <&cru ARMCLK>;
68 dynamic-power-coefficient = <120>;
69 enable-method = "psci";
70 next-level-cache = <&l2>;
71 operating-points-v2 = <&cpu0_opp_table>;
76 compatible = "arm,cortex-a53", "arm,armv8";
78 clocks = <&cru ARMCLK>;
80 dynamic-power-coefficient = <120>;
81 enable-method = "psci";
82 next-level-cache = <&l2>;
83 operating-points-v2 = <&cpu0_opp_table>;
91 cpu0_opp_table: opp_table0 {
92 compatible = "operating-points-v2";
96 opp-hz = /bits/ 64 <408000000>;
97 opp-microvolt = <950000>;
98 clock-latency-ns = <40000>;
102 opp-hz = /bits/ 64 <600000000>;
103 opp-microvolt = <950000>;
104 clock-latency-ns = <40000>;
107 opp-hz = /bits/ 64 <816000000>;
108 opp-microvolt = <1000000>;
109 clock-latency-ns = <40000>;
112 opp-hz = /bits/ 64 <1008000000>;
113 opp-microvolt = <1100000>;
114 clock-latency-ns = <40000>;
117 opp-hz = /bits/ 64 <1200000000>;
118 opp-microvolt = <1225000>;
119 clock-latency-ns = <40000>;
122 opp-hz = /bits/ 64 <1296000000>;
123 opp-microvolt = <1300000>;
124 clock-latency-ns = <40000>;
129 compatible = "simple-bus";
130 #address-cells = <2>;
134 dmac: dmac@ff1f0000 {
135 compatible = "arm,pl330", "arm,primecell";
136 reg = <0x0 0xff1f0000 0x0 0x4000>;
137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&cru ACLK_DMAC>;
140 clock-names = "apb_pclk";
146 compatible = "arm,cortex-a53-pmu";
147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
154 display_subsystem: display-subsystem {
155 compatible = "rockchip,display-subsystem";
160 compatible = "arm,psci-1.0", "arm,psci-0.2";
165 compatible = "arm,armv8-timer";
166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
173 compatible = "fixed-clock";
175 clock-frequency = <24000000>;
176 clock-output-names = "xin24m";
180 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
181 reg = <0x0 0xff000000 0x0 0x1000>;
182 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
184 clock-names = "i2s_clk", "i2s_hclk";
185 dmas = <&dmac 11>, <&dmac 12>;
186 dma-names = "tx", "rx";
191 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
192 reg = <0x0 0xff010000 0x0 0x1000>;
193 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
195 clock-names = "i2s_clk", "i2s_hclk";
196 dmas = <&dmac 14>, <&dmac 15>;
197 dma-names = "tx", "rx";
202 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
203 reg = <0x0 0xff020000 0x0 0x1000>;
204 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
206 clock-names = "i2s_clk", "i2s_hclk";
207 dmas = <&dmac 0>, <&dmac 1>;
208 dma-names = "tx", "rx";
212 spdif: spdif@ff030000 {
213 compatible = "rockchip,rk3328-spdif";
214 reg = <0x0 0xff030000 0x0 0x1000>;
215 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
217 clock-names = "mclk", "hclk";
220 pinctrl-names = "default";
221 pinctrl-0 = <&spdifm2_tx>;
226 compatible = "rockchip,pdm";
227 reg = <0x0 0xff040000 0x0 0x1000>;
228 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
229 clock-names = "pdm_clk", "pdm_hclk";
232 pinctrl-names = "default", "sleep";
233 pinctrl-0 = <&pdmm0_clk
238 pinctrl-1 = <&pdmm0_clk_sleep
246 grf: syscon@ff100000 {
247 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
248 reg = <0x0 0xff100000 0x0 0x1000>;
249 #address-cells = <1>;
252 io_domains: io-domains {
253 compatible = "rockchip,rk3328-io-voltage-domain";
258 compatible = "rockchip,rk3328-grf-gpio";
263 power: power-controller {
264 compatible = "rockchip,rk3328-power-controller";
265 #power-domain-cells = <1>;
266 #address-cells = <1>;
269 pd_hevc@RK3328_PD_HEVC {
270 reg = <RK3328_PD_HEVC>;
272 pd_video@RK3328_PD_VIDEO {
273 reg = <RK3328_PD_VIDEO>;
275 pd_vpu@RK3328_PD_VPU {
276 reg = <RK3328_PD_VPU>;
281 compatible = "syscon-reboot-mode";
283 mode-normal = <BOOT_NORMAL>;
284 mode-recovery = <BOOT_RECOVERY>;
285 mode-bootloader = <BOOT_FASTBOOT>;
286 mode-loader = <BOOT_BL_DOWNLOAD>;
290 uart0: serial@ff110000 {
291 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
292 reg = <0x0 0xff110000 0x0 0x100>;
293 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
295 clock-names = "baudclk", "apb_pclk";
296 dmas = <&dmac 2>, <&dmac 3>;
297 dma-names = "tx", "rx";
298 pinctrl-names = "default";
299 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
305 uart1: serial@ff120000 {
306 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
307 reg = <0x0 0xff120000 0x0 0x100>;
308 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
310 clock-names = "baudclk", "apb_pclk";
311 dmas = <&dmac 4>, <&dmac 5>;
312 dma-names = "tx", "rx";
313 pinctrl-names = "default";
314 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
320 uart2: serial@ff130000 {
321 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
322 reg = <0x0 0xff130000 0x0 0x100>;
323 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
325 clock-names = "baudclk", "apb_pclk";
326 dmas = <&dmac 6>, <&dmac 7>;
327 dma-names = "tx", "rx";
328 pinctrl-names = "default";
329 pinctrl-0 = <&uart2m1_xfer>;
336 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
337 reg = <0x0 0xff150000 0x0 0x1000>;
338 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
339 #address-cells = <1>;
341 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
342 clock-names = "i2c", "pclk";
343 pinctrl-names = "default";
344 pinctrl-0 = <&i2c0_xfer>;
349 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
350 reg = <0x0 0xff160000 0x0 0x1000>;
351 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
352 #address-cells = <1>;
354 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
355 clock-names = "i2c", "pclk";
356 pinctrl-names = "default";
357 pinctrl-0 = <&i2c1_xfer>;
362 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
363 reg = <0x0 0xff170000 0x0 0x1000>;
364 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
365 #address-cells = <1>;
367 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
368 clock-names = "i2c", "pclk";
369 pinctrl-names = "default";
370 pinctrl-0 = <&i2c2_xfer>;
375 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
376 reg = <0x0 0xff180000 0x0 0x1000>;
377 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
380 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
381 clock-names = "i2c", "pclk";
382 pinctrl-names = "default";
383 pinctrl-0 = <&i2c3_xfer>;
388 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
389 reg = <0x0 0xff190000 0x0 0x1000>;
390 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
391 #address-cells = <1>;
393 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
394 clock-names = "spiclk", "apb_pclk";
395 dmas = <&dmac 8>, <&dmac 9>;
396 dma-names = "tx", "rx";
397 pinctrl-names = "default";
398 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
402 wdt: watchdog@ff1a0000 {
403 compatible = "snps,dw-wdt";
404 reg = <0x0 0xff1a0000 0x0 0x100>;
405 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
409 compatible = "rockchip,rk3328-pwm";
410 reg = <0x0 0xff1b0000 0x0 0x10>;
411 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
412 clock-names = "pwm", "pclk";
413 pinctrl-names = "default";
414 pinctrl-0 = <&pwm0_pin>;
420 compatible = "rockchip,rk3328-pwm";
421 reg = <0x0 0xff1b0010 0x0 0x10>;
422 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
423 clock-names = "pwm", "pclk";
424 pinctrl-names = "default";
425 pinctrl-0 = <&pwm1_pin>;
431 compatible = "rockchip,rk3328-pwm";
432 reg = <0x0 0xff1b0020 0x0 0x10>;
433 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
434 clock-names = "pwm", "pclk";
435 pinctrl-names = "default";
436 pinctrl-0 = <&pwm2_pin>;
442 compatible = "rockchip,rk3328-pwm";
443 reg = <0x0 0xff1b0030 0x0 0x10>;
444 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
446 clock-names = "pwm", "pclk";
447 pinctrl-names = "default";
448 pinctrl-0 = <&pwmir_pin>;
454 soc_thermal: soc-thermal {
455 polling-delay-passive = <20>;
456 polling-delay = <1000>;
457 sustainable-power = <1000>;
459 thermal-sensors = <&tsadc 0>;
462 threshold: trip-point0 {
463 temperature = <70000>;
467 target: trip-point1 {
468 temperature = <85000>;
473 temperature = <95000>;
482 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
483 contribution = <4096>;
490 tsadc: tsadc@ff250000 {
491 compatible = "rockchip,rk3328-tsadc";
492 reg = <0x0 0xff250000 0x0 0x100>;
493 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
494 assigned-clocks = <&cru SCLK_TSADC>;
495 assigned-clock-rates = <50000>;
496 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
497 clock-names = "tsadc", "apb_pclk";
498 pinctrl-names = "init", "default", "sleep";
499 pinctrl-0 = <&otp_gpio>;
500 pinctrl-1 = <&otp_out>;
501 pinctrl-2 = <&otp_gpio>;
502 resets = <&cru SRST_TSADC>;
503 reset-names = "tsadc-apb";
504 rockchip,grf = <&grf>;
505 rockchip,hw-tshut-temp = <100000>;
506 #thermal-sensor-cells = <1>;
510 efuse: efuse@ff260000 {
511 compatible = "rockchip,rk3328-efuse";
512 reg = <0x0 0xff260000 0x0 0x50>;
513 #address-cells = <1>;
515 clocks = <&cru SCLK_EFUSE>;
516 clock-names = "pclk_efuse";
517 rockchip,efuse-size = <0x20>;
523 cpu_leakage: cpu-leakage@17 {
526 logic_leakage: logic-leakage@19 {
529 efuse_cpu_version: cpu-version@1a {
535 saradc: adc@ff280000 {
536 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
537 reg = <0x0 0xff280000 0x0 0x100>;
538 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
539 #io-channel-cells = <1>;
540 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
541 clock-names = "saradc", "apb_pclk";
542 resets = <&cru SRST_SARADC_P>;
543 reset-names = "saradc-apb";
548 compatible = "rockchip,rk3328-mali", "arm,mali-450";
549 reg = <0x0 0xff300000 0x0 0x40000>;
550 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
557 interrupt-names = "gp",
564 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
565 clock-names = "bus", "core";
566 resets = <&cru SRST_GPU_A>;
569 h265e_mmu: iommu@ff330200 {
570 compatible = "rockchip,iommu";
571 reg = <0x0 0xff330200 0 0x100>;
572 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
573 interrupt-names = "h265e_mmu";
574 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
575 clock-names = "aclk", "iface";
580 vepu_mmu: iommu@ff340800 {
581 compatible = "rockchip,iommu";
582 reg = <0x0 0xff340800 0x0 0x40>;
583 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
584 interrupt-names = "vepu_mmu";
585 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
586 clock-names = "aclk", "iface";
591 vpu_mmu: iommu@ff350800 {
592 compatible = "rockchip,iommu";
593 reg = <0x0 0xff350800 0x0 0x40>;
594 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
595 interrupt-names = "vpu_mmu";
596 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
597 clock-names = "aclk", "iface";
602 rkvdec_mmu: iommu@ff360480 {
603 compatible = "rockchip,iommu";
604 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
605 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
606 interrupt-names = "rkvdec_mmu";
607 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
608 clock-names = "aclk", "iface";
614 compatible = "rockchip,rk3328-vop";
615 reg = <0x0 0xff370000 0x0 0x3efc>;
616 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
618 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
619 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
620 reset-names = "axi", "ahb", "dclk";
625 #address-cells = <1>;
628 vop_out_hdmi: endpoint@0 {
630 remote-endpoint = <&hdmi_in_vop>;
635 vop_mmu: iommu@ff373f00 {
636 compatible = "rockchip,iommu";
637 reg = <0x0 0xff373f00 0x0 0x100>;
638 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
639 interrupt-names = "vop_mmu";
640 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
641 clock-names = "aclk", "iface";
646 hdmi: hdmi@ff3c0000 {
647 compatible = "rockchip,rk3328-dw-hdmi";
648 reg = <0x0 0xff3c0000 0x0 0x20000>;
650 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&cru PCLK_HDMI>,
653 <&cru SCLK_HDMI_SFC>;
654 clock-names = "iahb",
658 pinctrl-names = "default";
659 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
660 rockchip,grf = <&grf>;
665 hdmi_in_vop: endpoint {
666 remote-endpoint = <&vop_out_hdmi>;
672 hdmiphy: phy@ff430000 {
673 compatible = "rockchip,rk3328-hdmi-phy";
674 reg = <0x0 0xff430000 0x0 0x10000>;
675 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
677 clock-names = "sysclk", "refoclk", "refpclk";
678 clock-output-names = "hdmi_phy";
680 nvmem-cells = <&efuse_cpu_version>;
681 nvmem-cell-names = "cpu-version";
686 cru: clock-controller@ff440000 {
687 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
688 reg = <0x0 0xff440000 0x0 0x1000>;
689 rockchip,grf = <&grf>;
694 * CPLL should run at 1200, but that is to high for
695 * the initial dividers of most of its children.
696 * We need set cpll child clk div first,
697 * and then set the cpll frequency.
699 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
700 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
701 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
702 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
703 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
704 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
705 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
706 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
707 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
708 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
709 <&cru SCLK_WIFI>, <&cru ARMCLK>,
710 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
711 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
712 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
713 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
715 assigned-clock-parents =
716 <&cru HDMIPHY>, <&cru PLL_APLL>,
717 <&cru PLL_GPLL>, <&xin24m>,
718 <&xin24m>, <&xin24m>;
719 assigned-clock-rates =
722 <24000000>, <24000000>,
723 <15000000>, <15000000>,
724 <100000000>, <100000000>,
725 <100000000>, <100000000>,
726 <50000000>, <100000000>,
727 <100000000>, <100000000>,
728 <50000000>, <50000000>,
729 <50000000>, <50000000>,
730 <24000000>, <600000000>,
731 <491520000>, <1200000000>,
732 <150000000>, <75000000>,
733 <75000000>, <150000000>,
734 <75000000>, <75000000>,
738 usb2phy_grf: syscon@ff450000 {
739 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
741 reg = <0x0 0xff450000 0x0 0x10000>;
742 #address-cells = <1>;
745 u2phy: usb2-phy@100 {
746 compatible = "rockchip,rk3328-usb2phy";
749 clock-names = "phyclk";
750 clock-output-names = "usb480m_phy";
752 assigned-clocks = <&cru USB480M>;
753 assigned-clock-parents = <&u2phy>;
756 u2phy_otg: otg-port {
758 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
761 interrupt-names = "otg-bvalid", "otg-id",
766 u2phy_host: host-port {
768 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
769 interrupt-names = "linestate";
775 sdmmc: dwmmc@ff500000 {
776 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
777 reg = <0x0 0xff500000 0x0 0x4000>;
778 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
780 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
781 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
782 fifo-depth = <0x100>;
786 sdio: dwmmc@ff510000 {
787 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
788 reg = <0x0 0xff510000 0x0 0x4000>;
789 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
791 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
792 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
793 fifo-depth = <0x100>;
797 emmc: dwmmc@ff520000 {
798 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
799 reg = <0x0 0xff520000 0x0 0x4000>;
800 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
802 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
803 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
804 fifo-depth = <0x100>;
808 gmac2io: ethernet@ff540000 {
809 compatible = "rockchip,rk3328-gmac";
810 reg = <0x0 0xff540000 0x0 0x10000>;
811 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
812 interrupt-names = "macirq";
813 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
814 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
815 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
817 clock-names = "stmmaceth", "mac_clk_rx",
818 "mac_clk_tx", "clk_mac_ref",
819 "clk_mac_refout", "aclk_mac",
821 resets = <&cru SRST_GMAC2IO_A>;
822 reset-names = "stmmaceth";
823 rockchip,grf = <&grf>;
827 gmac2phy: ethernet@ff550000 {
828 compatible = "rockchip,rk3328-gmac";
829 reg = <0x0 0xff550000 0x0 0x10000>;
830 rockchip,grf = <&grf>;
831 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
832 interrupt-names = "macirq";
833 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
834 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
835 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
836 <&cru SCLK_MAC2PHY_OUT>;
837 clock-names = "stmmaceth", "mac_clk_rx",
838 "mac_clk_tx", "clk_mac_ref",
839 "aclk_mac", "pclk_mac",
841 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
842 reset-names = "stmmaceth", "mac-phy";
848 compatible = "snps,dwmac-mdio";
849 #address-cells = <1>;
853 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
855 clocks = <&cru SCLK_MAC2PHY_OUT>;
856 resets = <&cru SRST_MACPHY>;
857 pinctrl-names = "default";
858 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
864 usb20_otg: usb@ff580000 {
865 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
867 reg = <0x0 0xff580000 0x0 0x40000>;
868 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
869 clocks = <&cru HCLK_OTG>;
872 g-np-tx-fifo-size = <16>;
873 g-rx-fifo-size = <280>;
874 g-tx-fifo-size = <256 128 128 64 32 16>;
877 phy-names = "usb2-phy";
881 usb_host0_ehci: usb@ff5c0000 {
882 compatible = "generic-ehci";
883 reg = <0x0 0xff5c0000 0x0 0x10000>;
884 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&cru HCLK_HOST0>, <&u2phy>;
886 clock-names = "usbhost", "utmi";
887 phys = <&u2phy_host>;
892 usb_host0_ohci: usb@ff5d0000 {
893 compatible = "generic-ohci";
894 reg = <0x0 0xff5d0000 0x0 0x10000>;
895 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&cru HCLK_HOST0>, <&u2phy>;
897 clock-names = "usbhost", "utmi";
898 phys = <&u2phy_host>;
903 gic: interrupt-controller@ff811000 {
904 compatible = "arm,gic-400";
905 #interrupt-cells = <3>;
906 #address-cells = <0>;
907 interrupt-controller;
908 reg = <0x0 0xff811000 0 0x1000>,
909 <0x0 0xff812000 0 0x2000>,
910 <0x0 0xff814000 0 0x2000>,
911 <0x0 0xff816000 0 0x2000>;
912 interrupts = <GIC_PPI 9
913 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
917 compatible = "rockchip,rk3328-pinctrl";
918 rockchip,grf = <&grf>;
919 #address-cells = <2>;
923 gpio0: gpio0@ff210000 {
924 compatible = "rockchip,gpio-bank";
925 reg = <0x0 0xff210000 0x0 0x100>;
926 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&cru PCLK_GPIO0>;
932 interrupt-controller;
933 #interrupt-cells = <2>;
936 gpio1: gpio1@ff220000 {
937 compatible = "rockchip,gpio-bank";
938 reg = <0x0 0xff220000 0x0 0x100>;
939 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
940 clocks = <&cru PCLK_GPIO1>;
945 interrupt-controller;
946 #interrupt-cells = <2>;
949 gpio2: gpio2@ff230000 {
950 compatible = "rockchip,gpio-bank";
951 reg = <0x0 0xff230000 0x0 0x100>;
952 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
953 clocks = <&cru PCLK_GPIO2>;
958 interrupt-controller;
959 #interrupt-cells = <2>;
962 gpio3: gpio3@ff240000 {
963 compatible = "rockchip,gpio-bank";
964 reg = <0x0 0xff240000 0x0 0x100>;
965 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&cru PCLK_GPIO3>;
971 interrupt-controller;
972 #interrupt-cells = <2>;
975 pcfg_pull_up: pcfg-pull-up {
979 pcfg_pull_down: pcfg-pull-down {
983 pcfg_pull_none: pcfg-pull-none {
987 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
989 drive-strength = <2>;
992 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
994 drive-strength = <2>;
997 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
999 drive-strength = <4>;
1002 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1004 drive-strength = <4>;
1007 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1009 drive-strength = <4>;
1012 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1014 drive-strength = <8>;
1017 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1019 drive-strength = <8>;
1022 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1024 drive-strength = <12>;
1027 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1029 drive-strength = <12>;
1032 pcfg_output_high: pcfg-output-high {
1036 pcfg_output_low: pcfg-output-low {
1040 pcfg_input_high: pcfg-input-high {
1045 pcfg_input: pcfg-input {
1050 i2c0_xfer: i2c0-xfer {
1051 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1052 <2 RK_PD1 1 &pcfg_pull_none>;
1057 i2c1_xfer: i2c1-xfer {
1058 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1059 <2 RK_PA5 2 &pcfg_pull_none>;
1064 i2c2_xfer: i2c2-xfer {
1065 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1066 <2 RK_PB6 1 &pcfg_pull_none>;
1071 i2c3_xfer: i2c3-xfer {
1072 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1073 <0 RK_PA6 2 &pcfg_pull_none>;
1075 i2c3_gpio: i2c3-gpio {
1077 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1078 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1083 hdmii2c_xfer: hdmii2c-xfer {
1084 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1085 <0 RK_PA6 1 &pcfg_pull_none>;
1090 pdmm0_clk: pdmm0-clk {
1091 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1094 pdmm0_fsync: pdmm0-fsync {
1095 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1098 pdmm0_sdi0: pdmm0-sdi0 {
1099 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1102 pdmm0_sdi1: pdmm0-sdi1 {
1103 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1106 pdmm0_sdi2: pdmm0-sdi2 {
1107 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1110 pdmm0_sdi3: pdmm0-sdi3 {
1111 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1114 pdmm0_clk_sleep: pdmm0-clk-sleep {
1116 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1119 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1121 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1124 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1126 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1129 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1131 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1134 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1136 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1139 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1141 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1146 otp_gpio: otp-gpio {
1147 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1151 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1156 uart0_xfer: uart0-xfer {
1157 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1158 <1 RK_PB0 1 &pcfg_pull_none>;
1161 uart0_cts: uart0-cts {
1162 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1165 uart0_rts: uart0-rts {
1166 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1169 uart0_rts_gpio: uart0-rts-gpio {
1170 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1175 uart1_xfer: uart1-xfer {
1176 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1177 <3 RK_PA6 4 &pcfg_pull_none>;
1180 uart1_cts: uart1-cts {
1181 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1184 uart1_rts: uart1-rts {
1185 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1188 uart1_rts_gpio: uart1-rts-gpio {
1189 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1194 uart2m0_xfer: uart2m0-xfer {
1195 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1196 <1 RK_PA1 2 &pcfg_pull_none>;
1201 uart2m1_xfer: uart2m1-xfer {
1202 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1203 <2 RK_PA1 1 &pcfg_pull_none>;
1208 spi0m0_clk: spi0m0-clk {
1209 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1212 spi0m0_cs0: spi0m0-cs0 {
1213 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1216 spi0m0_tx: spi0m0-tx {
1217 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1220 spi0m0_rx: spi0m0-rx {
1221 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1224 spi0m0_cs1: spi0m0-cs1 {
1225 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1230 spi0m1_clk: spi0m1-clk {
1231 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1234 spi0m1_cs0: spi0m1-cs0 {
1235 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1238 spi0m1_tx: spi0m1-tx {
1239 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1242 spi0m1_rx: spi0m1-rx {
1243 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1246 spi0m1_cs1: spi0m1-cs1 {
1247 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1252 spi0m2_clk: spi0m2-clk {
1253 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1256 spi0m2_cs0: spi0m2-cs0 {
1257 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1260 spi0m2_tx: spi0m2-tx {
1261 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1264 spi0m2_rx: spi0m2-rx {
1265 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1270 i2s1_mclk: i2s1-mclk {
1271 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1274 i2s1_sclk: i2s1-sclk {
1275 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1278 i2s1_lrckrx: i2s1-lrckrx {
1279 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1282 i2s1_lrcktx: i2s1-lrcktx {
1283 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1286 i2s1_sdi: i2s1-sdi {
1287 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1290 i2s1_sdo: i2s1-sdo {
1291 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1294 i2s1_sdio1: i2s1-sdio1 {
1295 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1298 i2s1_sdio2: i2s1-sdio2 {
1299 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1302 i2s1_sdio3: i2s1-sdio3 {
1303 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1306 i2s1_sleep: i2s1-sleep {
1308 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1309 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1310 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1311 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1312 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1313 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1314 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1315 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1316 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1321 i2s2m0_mclk: i2s2m0-mclk {
1322 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1325 i2s2m0_sclk: i2s2m0-sclk {
1326 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1329 i2s2m0_lrckrx: i2s2m0-lrckrx {
1330 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1333 i2s2m0_lrcktx: i2s2m0-lrcktx {
1334 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1337 i2s2m0_sdi: i2s2m0-sdi {
1338 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1341 i2s2m0_sdo: i2s2m0-sdo {
1342 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1345 i2s2m0_sleep: i2s2m0-sleep {
1347 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1348 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1349 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1350 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1351 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1352 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1357 i2s2m1_mclk: i2s2m1-mclk {
1358 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1361 i2s2m1_sclk: i2s2m1-sclk {
1362 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1365 i2s2m1_lrckrx: i2sm1-lrckrx {
1366 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1369 i2s2m1_lrcktx: i2s2m1-lrcktx {
1370 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1373 i2s2m1_sdi: i2s2m1-sdi {
1374 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1377 i2s2m1_sdo: i2s2m1-sdo {
1378 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1381 i2s2m1_sleep: i2s2m1-sleep {
1383 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1384 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1385 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1386 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1387 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1392 spdifm0_tx: spdifm0-tx {
1393 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1398 spdifm1_tx: spdifm1-tx {
1399 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1404 spdifm2_tx: spdifm2-tx {
1405 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1410 sdmmc0m0_pwren: sdmmc0m0-pwren {
1411 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1414 sdmmc0m0_gpio: sdmmc0m0-gpio {
1415 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1420 sdmmc0m1_pwren: sdmmc0m1-pwren {
1421 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1424 sdmmc0m1_gpio: sdmmc0m1-gpio {
1425 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1430 sdmmc0_clk: sdmmc0-clk {
1431 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
1434 sdmmc0_cmd: sdmmc0-cmd {
1435 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
1438 sdmmc0_dectn: sdmmc0-dectn {
1439 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1442 sdmmc0_wrprt: sdmmc0-wrprt {
1443 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1446 sdmmc0_bus1: sdmmc0-bus1 {
1447 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
1450 sdmmc0_bus4: sdmmc0-bus4 {
1451 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
1452 <1 RK_PA1 1 &pcfg_pull_up_4ma>,
1453 <1 RK_PA2 1 &pcfg_pull_up_4ma>,
1454 <1 RK_PA3 1 &pcfg_pull_up_4ma>;
1457 sdmmc0_gpio: sdmmc0-gpio {
1459 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1460 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1461 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1462 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1463 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1464 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1465 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1466 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1471 sdmmc0ext_clk: sdmmc0ext-clk {
1472 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1475 sdmmc0ext_cmd: sdmmc0ext-cmd {
1476 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1479 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1480 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1483 sdmmc0ext_dectn: sdmmc0ext-dectn {
1484 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1487 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1488 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1491 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1493 <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1494 <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1495 <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1496 <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1499 sdmmc0ext_gpio: sdmmc0ext-gpio {
1501 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1502 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1503 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1504 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1505 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1506 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1507 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1508 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1513 sdmmc1_clk: sdmmc1-clk {
1514 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1517 sdmmc1_cmd: sdmmc1-cmd {
1518 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1521 sdmmc1_pwren: sdmmc1-pwren {
1522 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1525 sdmmc1_wrprt: sdmmc1-wrprt {
1526 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1529 sdmmc1_dectn: sdmmc1-dectn {
1530 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1533 sdmmc1_bus1: sdmmc1-bus1 {
1534 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1537 sdmmc1_bus4: sdmmc1-bus4 {
1538 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1539 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1540 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1541 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1544 sdmmc1_gpio: sdmmc1-gpio {
1546 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1547 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1548 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1549 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1550 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1551 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1552 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1553 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1554 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1559 emmc_clk: emmc-clk {
1560 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1563 emmc_cmd: emmc-cmd {
1564 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1567 emmc_pwren: emmc-pwren {
1568 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1571 emmc_rstnout: emmc-rstnout {
1572 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1575 emmc_bus1: emmc-bus1 {
1576 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1579 emmc_bus4: emmc-bus4 {
1581 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1582 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1583 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1584 <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1587 emmc_bus8: emmc-bus8 {
1589 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1590 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1591 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1592 <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1593 <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1594 <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1595 <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1596 <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1601 pwm0_pin: pwm0-pin {
1602 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1607 pwm1_pin: pwm1-pin {
1608 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1613 pwm2_pin: pwm2-pin {
1614 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1619 pwmir_pin: pwmir-pin {
1620 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1625 rgmiim1_pins: rgmiim1-pins {
1628 <1 RK_PB4 2 &pcfg_pull_none_12ma>,
1630 <1 RK_PB5 2 &pcfg_pull_none_2ma>,
1632 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1634 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1636 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1638 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1640 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1642 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1644 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1646 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1648 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1650 <1 RK_PB6 2 &pcfg_pull_none_2ma>,
1652 <1 RK_PB7 2 &pcfg_pull_none_2ma>,
1654 <1 RK_PC0 2 &pcfg_pull_none_12ma>,
1656 <1 RK_PC1 2 &pcfg_pull_none_12ma>,
1659 <0 RK_PB0 1 &pcfg_pull_none>,
1661 <0 RK_PB4 1 &pcfg_pull_none>,
1663 <0 RK_PD0 1 &pcfg_pull_none>,
1665 <0 RK_PC0 1 &pcfg_pull_none>,
1667 <0 RK_PC1 1 &pcfg_pull_none>,
1669 <0 RK_PC7 1 &pcfg_pull_none>,
1671 <0 RK_PC6 1 &pcfg_pull_none>;
1674 rmiim1_pins: rmiim1-pins {
1677 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1679 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1681 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1683 <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1685 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1687 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1689 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1691 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1693 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1695 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1698 <0 RK_PB3 1 &pcfg_pull_none>,
1700 <0 RK_PB4 1 &pcfg_pull_none>,
1702 <0 RK_PD0 1 &pcfg_pull_none>,
1704 <0 RK_PC3 1 &pcfg_pull_none>,
1706 <0 RK_PC0 1 &pcfg_pull_none>,
1708 <0 RK_PC1 1 &pcfg_pull_none>;
1713 fephyled_speed100: fephyled-speed100 {
1714 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1717 fephyled_speed10: fephyled-speed10 {
1718 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1721 fephyled_duplex: fephyled-duplex {
1722 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1725 fephyled_rxm0: fephyled-rxm0 {
1726 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1729 fephyled_txm0: fephyled-txm0 {
1730 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1733 fephyled_linkm0: fephyled-linkm0 {
1734 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1737 fephyled_rxm1: fephyled-rxm1 {
1738 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1741 fephyled_txm1: fephyled-txm1 {
1742 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1745 fephyled_linkm1: fephyled-linkm1 {
1746 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1751 tsadc_int: tsadc-int {
1752 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1754 tsadc_gpio: tsadc-gpio {
1755 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1760 hdmi_cec: hdmi-cec {
1761 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1764 hdmi_hpd: hdmi-hpd {
1765 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1770 dvp_d2d9_m0:dvp-d2d9-m0 {
1773 <3 RK_PA4 2 &pcfg_pull_none>,
1775 <3 RK_PA5 2 &pcfg_pull_none>,
1777 <3 RK_PA6 2 &pcfg_pull_none>,
1779 <3 RK_PA7 2 &pcfg_pull_none>,
1781 <3 RK_PB0 2 &pcfg_pull_none>,
1783 <3 RK_PB1 2 &pcfg_pull_none>,
1785 <3 RK_PB2 2 &pcfg_pull_none>,
1787 <3 RK_PB3 2 &pcfg_pull_none>,
1789 <3 RK_PA1 2 &pcfg_pull_none>,
1791 <3 RK_PA0 2 &pcfg_pull_none>,
1793 <3 RK_PA3 2 &pcfg_pull_none>,
1795 <3 RK_PA2 2 &pcfg_pull_none>;
1800 dvp_d2d9_m1:dvp-d2d9-m1 {
1803 <3 RK_PA4 2 &pcfg_pull_none>,
1805 <3 RK_PA5 2 &pcfg_pull_none>,
1807 <3 RK_PA6 2 &pcfg_pull_none>,
1809 <3 RK_PA7 2 &pcfg_pull_none>,
1811 <3 RK_PB0 2 &pcfg_pull_none>,
1813 <2 RK_PC0 4 &pcfg_pull_none>,
1815 <2 RK_PC1 4 &pcfg_pull_none>,
1817 <2 RK_PC2 4 &pcfg_pull_none>,
1819 <3 RK_PA1 2 &pcfg_pull_none>,
1821 <3 RK_PA0 2 &pcfg_pull_none>,
1823 <2 RK_PB7 4 &pcfg_pull_none>,
1825 <3 RK_PA2 2 &pcfg_pull_none>;