arch/arm64/boot/dts/rockchip/px30.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/px30-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/px30-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,px30";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &uart2;
  30                 serial3 = &uart3;
  31                 serial4 = &uart4;
  32                 serial5 = &uart5;
  33                 spi0 = &spi0;
  34                 spi1 = &spi1;
  35         };
  36
  37         cpus {
  38                 #address-cells = <2>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a35";
  44                         reg = <0x0 0x0>;
  45                         enable-method = "psci";
  46                         clocks = <&cru ARMCLK>;
  47                         #cooling-cells = <2>;
  48                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  49                         dynamic-power-coefficient = <90>;
  50                         operating-points-v2 = <&cpu0_opp_table>;
  51                 };
  52
  53                 cpu1: cpu@1 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a35";
  56                         reg = <0x0 0x1>;
  57                         enable-method = "psci";
  58                         clocks = <&cru ARMCLK>;
  59                         #cooling-cells = <2>;
  60                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  61                         dynamic-power-coefficient = <90>;
  62                         operating-points-v2 = <&cpu0_opp_table>;
  63                 };
  64
  65                 cpu2: cpu@2 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a35";
  68                         reg = <0x0 0x2>;
  69                         enable-method = "psci";
  70                         clocks = <&cru ARMCLK>;
  71                         #cooling-cells = <2>;
  72                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  73                         dynamic-power-coefficient = <90>;
  74                         operating-points-v2 = <&cpu0_opp_table>;
  75                 };
  76
  77                 cpu3: cpu@3 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a35";
  80                         reg = <0x0 0x3>;
  81                         enable-method = "psci";
  82                         clocks = <&cru ARMCLK>;
  83                         #cooling-cells = <2>;
  84                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  85                         dynamic-power-coefficient = <90>;
  86                         operating-points-v2 = <&cpu0_opp_table>;
  87                 };
  88
  89                 idle-states {
  90                         entry-method = "psci";
  91
  92                         CPU_SLEEP: cpu-sleep {
  93                                 compatible = "arm,idle-state";
  94                                 local-timer-stop;
  95                                 arm,psci-suspend-param = <0x0010000>;
  96                                 entry-latency-us = <120>;
  97                                 exit-latency-us = <250>;
  98                                 min-residency-us = <900>;
  99                         };
 100
 101                         CLUSTER_SLEEP: cluster-sleep {
 102                                 compatible = "arm,idle-state";
 103                                 local-timer-stop;
 104                                 arm,psci-suspend-param = <0x1010000>;
 105                                 entry-latency-us = <400>;
 106                                 exit-latency-us = <500>;
 107                                 min-residency-us = <2000>;
 108                         };
 109                 };
 110         };
 111
 112         cpu0_opp_table: opp-table-0 {
 113                 compatible = "operating-points-v2";
 114                 opp-shared;
 115
 116                 opp-600000000 {
 117                         opp-hz = /bits/ 64 <600000000>;
 118                         opp-microvolt = <950000 950000 1350000>;
 119                         clock-latency-ns = <40000>;
 120                         opp-suspend;
 121                 };
 122                 opp-816000000 {
 123                         opp-hz = /bits/ 64 <816000000>;
 124                         opp-microvolt = <1050000 1050000 1350000>;
 125                         clock-latency-ns = <40000>;
 126                 };
 127                 opp-1008000000 {
 128                         opp-hz = /bits/ 64 <1008000000>;
 129                         opp-microvolt = <1175000 1175000 1350000>;
 130                         clock-latency-ns = <40000>;
 131                 };
 132                 opp-1200000000 {
 133                         opp-hz = /bits/ 64 <1200000000>;
 134                         opp-microvolt = <1300000 1300000 1350000>;
 135                         clock-latency-ns = <40000>;
 136                 };
 137                 opp-1296000000 {
 138                         opp-hz = /bits/ 64 <1296000000>;
 139                         opp-microvolt = <1350000 1350000 1350000>;
 140                         clock-latency-ns = <40000>;
 141                 };
 142         };
 143
 144         arm-pmu {
 145                 compatible = "arm,cortex-a35-pmu";
 146                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 150                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 151         };
 152
 153         display_subsystem: display-subsystem {
 154                 compatible = "rockchip,display-subsystem";
 155                 ports = <&vopb_out>, <&vopl_out>;
 156                 status = "disabled";
 157         };
 158
 159         gmac_clkin: external-gmac-clock {
 160                 compatible = "fixed-clock";
 161                 clock-frequency = <50000000>;
 162                 clock-output-names = "gmac_clkin";
 163                 #clock-cells = <0>;
 164         };
 165
 166         psci {
 167                 compatible = "arm,psci-1.0";
 168                 method = "smc";
 169         };
 170
 171         timer {
 172                 compatible = "arm,armv8-timer";
 173                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 174                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 175                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 176                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 177         };
 178
 179         thermal_zones: thermal-zones {
 180                 soc_thermal: soc-thermal {
 181                         polling-delay-passive = <20>;
 182                         polling-delay = <1000>;
 183                         sustainable-power = <750>;
 184                         thermal-sensors = <&tsadc 0>;
 185
 186                         trips {
 187                                 threshold: trip-point-0 {
 188                                         temperature = <70000>;
 189                                         hysteresis = <2000>;
 190                                         type = "passive";
 191                                 };
 192
 193                                 target: trip-point-1 {
 194                                         temperature = <85000>;
 195                                         hysteresis = <2000>;
 196                                         type = "passive";
 197                                 };
 198
 199                                 soc_crit: soc-crit {
 200                                         temperature = <115000>;
 201                                         hysteresis = <2000>;
 202                                         type = "critical";
 203                                 };
 204                         };
 205
 206                         cooling-maps {
 207                                 map0 {
 208                                         trip = <&target>;
 209                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 210                                         contribution = <4096>;
 211                                 };
 212                         };
 213                 };
 214
 215                 gpu_thermal: gpu-thermal {
 216                         polling-delay-passive = <100>; /* milliseconds */
 217                         polling-delay = <1000>; /* milliseconds */
 218                         thermal-sensors = <&tsadc 1>;
 219
 220                         trips {
 221                                 gpu_threshold: gpu-threshold {
 222                                         temperature = <70000>;
 223                                         hysteresis = <2000>;
 224                                         type = "passive";
 225                                 };
 226
 227                                 gpu_target: gpu-target {
 228                                         temperature = <85000>;
 229                                         hysteresis = <2000>;
 230                                         type = "passive";
 231                                 };
 232
 233                                 gpu_crit: gpu-crit {
 234                                         temperature = <115000>;
 235                                         hysteresis = <2000>;
 236                                         type = "critical";
 237                                 };
 238                         };
 239
 240                         cooling-maps {
 241                                 map0 {
 242                                         trip = <&gpu_target>;
 243                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 244                                 };
 245                         };
 246                 };
 247         };
 248
 249         xin24m: xin24m {
 250                 compatible = "fixed-clock";
 251                 #clock-cells = <0>;
 252                 clock-frequency = <24000000>;
 253                 clock-output-names = "xin24m";
 254         };
 255
 256         pmu: power-management@ff000000 {
 257                 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
 258                 reg = <0x0 0xff000000 0x0 0x1000>;
 259
 260                 power: power-controller {
 261                         compatible = "rockchip,px30-power-controller";
 262                         #power-domain-cells = <1>;
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265
 266                         /* These power domains are grouped by VD_LOGIC */
 267                         power-domain@PX30_PD_USB {
 268                                 reg = <PX30_PD_USB>;
 269                                 clocks = <&cru HCLK_HOST>,
 270                                          <&cru HCLK_OTG>,
 271                                          <&cru SCLK_OTG_ADP>;
 272                                 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
 273                                 #power-domain-cells = <0>;
 274                         };
 275                         power-domain@PX30_PD_SDCARD {
 276                                 reg = <PX30_PD_SDCARD>;
 277                                 clocks = <&cru HCLK_SDMMC>,
 278                                          <&cru SCLK_SDMMC>;
 279                                 pm_qos = <&qos_sdmmc>;
 280                                 #power-domain-cells = <0>;
 281                         };
 282                         power-domain@PX30_PD_GMAC {
 283                                 reg = <PX30_PD_GMAC>;
 284                                 clocks = <&cru ACLK_GMAC>,
 285                                          <&cru PCLK_GMAC>,
 286                                          <&cru SCLK_MAC_REF>,
 287                                          <&cru SCLK_GMAC_RX_TX>;
 288                                 pm_qos = <&qos_gmac>;
 289                                 #power-domain-cells = <0>;
 290                         };
 291                         power-domain@PX30_PD_MMC_NAND {
 292                                 reg = <PX30_PD_MMC_NAND>;
 293                                 clocks = <&cru HCLK_NANDC>,
 294                                          <&cru HCLK_EMMC>,
 295                                          <&cru HCLK_SDIO>,
 296                                          <&cru HCLK_SFC>,
 297                                          <&cru SCLK_EMMC>,
 298                                          <&cru SCLK_NANDC>,
 299                                          <&cru SCLK_SDIO>,
 300                                          <&cru SCLK_SFC>;
 301                                 pm_qos = <&qos_emmc>, <&qos_nand>,
 302                                          <&qos_sdio>, <&qos_sfc>;
 303                                 #power-domain-cells = <0>;
 304                         };
 305                         power-domain@PX30_PD_VPU {
 306                                 reg = <PX30_PD_VPU>;
 307                                 clocks = <&cru ACLK_VPU>,
 308                                          <&cru HCLK_VPU>,
 309                                          <&cru SCLK_CORE_VPU>;
 310                                 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
 311                                 #power-domain-cells = <0>;
 312                         };
 313                         power-domain@PX30_PD_VO {
 314                                 reg = <PX30_PD_VO>;
 315                                 clocks = <&cru ACLK_RGA>,
 316                                          <&cru ACLK_VOPB>,
 317                                          <&cru ACLK_VOPL>,
 318                                          <&cru DCLK_VOPB>,
 319                                          <&cru DCLK_VOPL>,
 320                                          <&cru HCLK_RGA>,
 321                                          <&cru HCLK_VOPB>,
 322                                          <&cru HCLK_VOPL>,
 323                                          <&cru PCLK_MIPI_DSI>,
 324                                          <&cru SCLK_RGA_CORE>,
 325                                          <&cru SCLK_VOPB_PWM>;
 326                                 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
 327                                          <&qos_vop_m0>, <&qos_vop_m1>;
 328                                 #power-domain-cells = <0>;
 329                         };
 330                         power-domain@PX30_PD_VI {
 331                                 reg = <PX30_PD_VI>;
 332                                 clocks = <&cru ACLK_CIF>,
 333                                          <&cru ACLK_ISP>,
 334                                          <&cru HCLK_CIF>,
 335                                          <&cru HCLK_ISP>,
 336                                          <&cru SCLK_ISP>;
 337                                 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
 338                                          <&qos_isp_wr>, <&qos_isp_m1>,
 339                                          <&qos_vip>;
 340                                 #power-domain-cells = <0>;
 341                         };
 342                         power-domain@PX30_PD_GPU {
 343                                 reg = <PX30_PD_GPU>;
 344                                 clocks = <&cru SCLK_GPU>;
 345                                 pm_qos = <&qos_gpu>;
 346                                 #power-domain-cells = <0>;
 347                         };
 348                 };
 349         };
 350
 351         pmugrf: syscon@ff010000 {
 352                 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
 353                 reg = <0x0 0xff010000 0x0 0x1000>;
 354                 #address-cells = <1>;
 355                 #size-cells = <1>;
 356
 357                 pmu_io_domains: io-domains {
 358                         compatible = "rockchip,px30-pmu-io-voltage-domain";
 359                         status = "disabled";
 360                 };
 361
 362                 reboot-mode {
 363                         compatible = "syscon-reboot-mode";
 364                         offset = <0x200>;
 365                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 366                         mode-fastboot = <BOOT_FASTBOOT>;
 367                         mode-loader = <BOOT_BL_DOWNLOAD>;
 368                         mode-normal = <BOOT_NORMAL>;
 369                         mode-recovery = <BOOT_RECOVERY>;
 370                 };
 371         };
 372
 373         uart0: serial@ff030000 {
 374                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 375                 reg = <0x0 0xff030000 0x0 0x100>;
 376                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 377                 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
 378                 clock-names = "baudclk", "apb_pclk";
 379                 dmas = <&dmac 0>, <&dmac 1>;
 380                 dma-names = "tx", "rx";
 381                 reg-shift = <2>;
 382                 reg-io-width = <4>;
 383                 pinctrl-names = "default";
 384                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 385                 status = "disabled";
 386         };
 387
 388         i2s0_8ch: i2s@ff060000 {
 389                 compatible = "rockchip,px30-i2s-tdm";
 390                 reg = <0x0 0xff060000 0x0 0x1000>;
 391                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 392                 clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
 393                 clock-names = "mclk_tx", "mclk_rx", "hclk";
 394                 dmas = <&dmac 16>, <&dmac 17>;
 395                 dma-names = "tx", "rx";
 396                 rockchip,grf = <&grf>;
 397                 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
 398                 reset-names = "tx-m", "rx-m";
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
 401                              &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx
 402                              &i2s0_8ch_sdo0 &i2s0_8ch_sdi0
 403                              &i2s0_8ch_sdo1 &i2s0_8ch_sdi1
 404                              &i2s0_8ch_sdo2 &i2s0_8ch_sdi2
 405                              &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>;
 406                 #sound-dai-cells = <0>;
 407                 status = "disabled";
 408         };
 409
 410         i2s1_2ch: i2s@ff070000 {
 411                 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 412                 reg = <0x0 0xff070000 0x0 0x1000>;
 413                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 414                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
 415                 clock-names = "i2s_clk", "i2s_hclk";
 416                 dmas = <&dmac 18>, <&dmac 19>;
 417                 dma-names = "tx", "rx";
 418                 pinctrl-names = "default";
 419                 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
 420                              &i2s1_2ch_sdi &i2s1_2ch_sdo>;
 421                 #sound-dai-cells = <0>;
 422                 status = "disabled";
 423         };
 424
 425         i2s2_2ch: i2s@ff080000 {
 426                 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 427                 reg = <0x0 0xff080000 0x0 0x1000>;
 428                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 429                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
 430                 clock-names = "i2s_clk", "i2s_hclk";
 431                 dmas = <&dmac 20>, <&dmac 21>;
 432                 dma-names = "tx", "rx";
 433                 pinctrl-names = "default";
 434                 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
 435                              &i2s2_2ch_sdi &i2s2_2ch_sdo>;
 436                 #sound-dai-cells = <0>;
 437                 status = "disabled";
 438         };
 439
 440         gic: interrupt-controller@ff131000 {
 441                 compatible = "arm,gic-400";
 442                 #interrupt-cells = <3>;
 443                 #address-cells = <0>;
 444                 interrupt-controller;
 445                 reg = <0x0 0xff131000 0 0x1000>,
 446                       <0x0 0xff132000 0 0x2000>,
 447                       <0x0 0xff134000 0 0x2000>,
 448                       <0x0 0xff136000 0 0x2000>;
 449                 interrupts = <GIC_PPI 9
 450                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 451         };
 452
 453         grf: syscon@ff140000 {
 454                 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
 455                 reg = <0x0 0xff140000 0x0 0x1000>;
 456                 #address-cells = <1>;
 457                 #size-cells = <1>;
 458
 459                 io_domains: io-domains {
 460                         compatible = "rockchip,px30-io-voltage-domain";
 461                         status = "disabled";
 462                 };
 463
 464                 lvds: lvds {
 465                         compatible = "rockchip,px30-lvds";
 466                         phys = <&dsi_dphy>;
 467                         phy-names = "dphy";
 468                         rockchip,grf = <&grf>;
 469                         rockchip,output = "lvds";
 470                         status = "disabled";
 471
 472                         ports {
 473                                 #address-cells = <1>;
 474                                 #size-cells = <0>;
 475
 476                                 lvds_in: port@0 {
 477                                         reg = <0>;
 478                                         #address-cells = <1>;
 479                                         #size-cells = <0>;
 480
 481                                         lvds_vopb_in: endpoint@0 {
 482                                                 reg = <0>;
 483                                                 remote-endpoint = <&vopb_out_lvds>;
 484                                         };
 485
 486                                         lvds_vopl_in: endpoint@1 {
 487                                                 reg = <1>;
 488                                                 remote-endpoint = <&vopl_out_lvds>;
 489                                         };
 490                                 };
 491
 492                                 lvds_out: port@1 {
 493                                         reg = <1>;
 494                                 };
 495                         };
 496                 };
 497         };
 498
 499         uart1: serial@ff158000 {
 500                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 501                 reg = <0x0 0xff158000 0x0 0x100>;
 502                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 503                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 504                 clock-names = "baudclk", "apb_pclk";
 505                 dmas = <&dmac 2>, <&dmac 3>;
 506                 dma-names = "tx", "rx";
 507                 reg-shift = <2>;
 508                 reg-io-width = <4>;
 509                 pinctrl-names = "default";
 510                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 511                 status = "disabled";
 512         };
 513
 514         uart2: serial@ff160000 {
 515                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 516                 reg = <0x0 0xff160000 0x0 0x100>;
 517                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 518                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 519                 clock-names = "baudclk", "apb_pclk";
 520                 dmas = <&dmac 4>, <&dmac 5>;
 521                 dma-names = "tx", "rx";
 522                 reg-shift = <2>;
 523                 reg-io-width = <4>;
 524                 pinctrl-names = "default";
 525                 pinctrl-0 = <&uart2m0_xfer>;
 526                 status = "disabled";
 527         };
 528
 529         uart3: serial@ff168000 {
 530                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 531                 reg = <0x0 0xff168000 0x0 0x100>;
 532                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 533                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 534                 clock-names = "baudclk", "apb_pclk";
 535                 dmas = <&dmac 6>, <&dmac 7>;
 536                 dma-names = "tx", "rx";
 537                 reg-shift = <2>;
 538                 reg-io-width = <4>;
 539                 pinctrl-names = "default";
 540                 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
 541                 status = "disabled";
 542         };
 543
 544         uart4: serial@ff170000 {
 545                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 546                 reg = <0x0 0xff170000 0x0 0x100>;
 547                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 548                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 549                 clock-names = "baudclk", "apb_pclk";
 550                 dmas = <&dmac 8>, <&dmac 9>;
 551                 dma-names = "tx", "rx";
 552                 reg-shift = <2>;
 553                 reg-io-width = <4>;
 554                 pinctrl-names = "default";
 555                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 556                 status = "disabled";
 557         };
 558
 559         uart5: serial@ff178000 {
 560                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 561                 reg = <0x0 0xff178000 0x0 0x100>;
 562                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 563                 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
 564                 clock-names = "baudclk", "apb_pclk";
 565                 dmas = <&dmac 10>, <&dmac 11>;
 566                 dma-names = "tx", "rx";
 567                 reg-shift = <2>;
 568                 reg-io-width = <4>;
 569                 pinctrl-names = "default";
 570                 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
 571                 status = "disabled";
 572         };
 573
 574         i2c0: i2c@ff180000 {
 575                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 576                 reg = <0x0 0xff180000 0x0 0x1000>;
 577                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 578                 clock-names = "i2c", "pclk";
 579                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&i2c0_xfer>;
 582                 #address-cells = <1>;
 583                 #size-cells = <0>;
 584                 status = "disabled";
 585         };
 586
 587         i2c1: i2c@ff190000 {
 588                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 589                 reg = <0x0 0xff190000 0x0 0x1000>;
 590                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 591                 clock-names = "i2c", "pclk";
 592                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 593                 pinctrl-names = "default";
 594                 pinctrl-0 = <&i2c1_xfer>;
 595                 #address-cells = <1>;
 596                 #size-cells = <0>;
 597                 status = "disabled";
 598         };
 599
 600         i2c2: i2c@ff1a0000 {
 601                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 602                 reg = <0x0 0xff1a0000 0x0 0x1000>;
 603                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 604                 clock-names = "i2c", "pclk";
 605                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 606                 pinctrl-names = "default";
 607                 pinctrl-0 = <&i2c2_xfer>;
 608                 #address-cells = <1>;
 609                 #size-cells = <0>;
 610                 status = "disabled";
 611         };
 612
 613         i2c3: i2c@ff1b0000 {
 614                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 615                 reg = <0x0 0xff1b0000 0x0 0x1000>;
 616                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 617                 clock-names = "i2c", "pclk";
 618                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 619                 pinctrl-names = "default";
 620                 pinctrl-0 = <&i2c3_xfer>;
 621                 #address-cells = <1>;
 622                 #size-cells = <0>;
 623                 status = "disabled";
 624         };
 625
 626         spi0: spi@ff1d0000 {
 627                 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
 628                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 629                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 630                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 631                 clock-names = "spiclk", "apb_pclk";
 632                 dmas = <&dmac 12>, <&dmac 13>;
 633                 dma-names = "tx", "rx";
 634                 pinctrl-names = "default";
 635                 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
 636                 #address-cells = <1>;
 637                 #size-cells = <0>;
 638                 status = "disabled";
 639         };
 640
 641         spi1: spi@ff1d8000 {
 642                 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
 643                 reg = <0x0 0xff1d8000 0x0 0x1000>;
 644                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 645                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 646                 clock-names = "spiclk", "apb_pclk";
 647                 dmas = <&dmac 14>, <&dmac 15>;
 648                 dma-names = "tx", "rx";
 649                 pinctrl-names = "default";
 650                 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
 651                 #address-cells = <1>;
 652                 #size-cells = <0>;
 653                 status = "disabled";
 654         };
 655
 656         wdt: watchdog@ff1e0000 {
 657                 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
 658                 reg = <0x0 0xff1e0000 0x0 0x100>;
 659                 clocks = <&cru PCLK_WDT_NS>;
 660                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 661                 status = "disabled";
 662         };
 663
 664         pwm0: pwm@ff200000 {
 665                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 666                 reg = <0x0 0xff200000 0x0 0x10>;
 667                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 668                 clock-names = "pwm", "pclk";
 669                 pinctrl-names = "default";
 670                 pinctrl-0 = <&pwm0_pin>;
 671                 #pwm-cells = <3>;
 672                 status = "disabled";
 673         };
 674
 675         pwm1: pwm@ff200010 {
 676                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 677                 reg = <0x0 0xff200010 0x0 0x10>;
 678                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 679                 clock-names = "pwm", "pclk";
 680                 pinctrl-names = "default";
 681                 pinctrl-0 = <&pwm1_pin>;
 682                 #pwm-cells = <3>;
 683                 status = "disabled";
 684         };
 685
 686         pwm2: pwm@ff200020 {
 687                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 688                 reg = <0x0 0xff200020 0x0 0x10>;
 689                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 690                 clock-names = "pwm", "pclk";
 691                 pinctrl-names = "default";
 692                 pinctrl-0 = <&pwm2_pin>;
 693                 #pwm-cells = <3>;
 694                 status = "disabled";
 695         };
 696
 697         pwm3: pwm@ff200030 {
 698                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 699                 reg = <0x0 0xff200030 0x0 0x10>;
 700                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 701                 clock-names = "pwm", "pclk";
 702                 pinctrl-names = "default";
 703                 pinctrl-0 = <&pwm3_pin>;
 704                 #pwm-cells = <3>;
 705                 status = "disabled";
 706         };
 707
 708         pwm4: pwm@ff208000 {
 709                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 710                 reg = <0x0 0xff208000 0x0 0x10>;
 711                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 712                 clock-names = "pwm", "pclk";
 713                 pinctrl-names = "default";
 714                 pinctrl-0 = <&pwm4_pin>;
 715                 #pwm-cells = <3>;
 716                 status = "disabled";
 717         };
 718
 719         pwm5: pwm@ff208010 {
 720                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 721                 reg = <0x0 0xff208010 0x0 0x10>;
 722                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 723                 clock-names = "pwm", "pclk";
 724                 pinctrl-names = "default";
 725                 pinctrl-0 = <&pwm5_pin>;
 726                 #pwm-cells = <3>;
 727                 status = "disabled";
 728         };
 729
 730         pwm6: pwm@ff208020 {
 731                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 732                 reg = <0x0 0xff208020 0x0 0x10>;
 733                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 734                 clock-names = "pwm", "pclk";
 735                 pinctrl-names = "default";
 736                 pinctrl-0 = <&pwm6_pin>;
 737                 #pwm-cells = <3>;
 738                 status = "disabled";
 739         };
 740
 741         pwm7: pwm@ff208030 {
 742                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 743                 reg = <0x0 0xff208030 0x0 0x10>;
 744                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 745                 clock-names = "pwm", "pclk";
 746                 pinctrl-names = "default";
 747                 pinctrl-0 = <&pwm7_pin>;
 748                 #pwm-cells = <3>;
 749                 status = "disabled";
 750         };
 751
 752         rktimer: timer@ff210000 {
 753                 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
 754                 reg = <0x0 0xff210000 0x0 0x1000>;
 755                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 756                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
 757                 clock-names = "pclk", "timer";
 758         };
 759
 760         dmac: dma-controller@ff240000 {
 761                 compatible = "arm,pl330", "arm,primecell";
 762                 reg = <0x0 0xff240000 0x0 0x4000>;
 763                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 764                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 765                 arm,pl330-periph-burst;
 766                 clocks = <&cru ACLK_DMAC>;
 767                 clock-names = "apb_pclk";
 768                 #dma-cells = <1>;
 769         };
 770
 771         tsadc: tsadc@ff280000 {
 772                 compatible = "rockchip,px30-tsadc";
 773                 reg = <0x0 0xff280000 0x0 0x100>;
 774                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 775                 assigned-clocks = <&cru SCLK_TSADC>;
 776                 assigned-clock-rates = <50000>;
 777                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 778                 clock-names = "tsadc", "apb_pclk";
 779                 resets = <&cru SRST_TSADC>;
 780                 reset-names = "tsadc-apb";
 781                 rockchip,grf = <&grf>;
 782                 rockchip,hw-tshut-temp = <120000>;
 783                 pinctrl-names = "init", "default", "sleep";
 784                 pinctrl-0 = <&tsadc_otp_pin>;
 785                 pinctrl-1 = <&tsadc_otp_out>;
 786                 pinctrl-2 = <&tsadc_otp_pin>;
 787                 #thermal-sensor-cells = <1>;
 788                 status = "disabled";
 789         };
 790
 791         saradc: saradc@ff288000 {
 792                 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
 793                 reg = <0x0 0xff288000 0x0 0x100>;
 794                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 795                 #io-channel-cells = <1>;
 796                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 797                 clock-names = "saradc", "apb_pclk";
 798                 resets = <&cru SRST_SARADC_P>;
 799                 reset-names = "saradc-apb";
 800                 status = "disabled";
 801         };
 802
 803         otp: nvmem@ff290000 {
 804                 compatible = "rockchip,px30-otp";
 805                 reg = <0x0 0xff290000 0x0 0x4000>;
 806                 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
 807                          <&cru PCLK_OTP_PHY>;
 808                 clock-names = "otp", "apb_pclk", "phy";
 809                 resets = <&cru SRST_OTP_PHY>;
 810                 reset-names = "phy";
 811                 #address-cells = <1>;
 812                 #size-cells = <1>;
 813
 814                 /* Data cells */
 815                 cpu_id: id@7 {
 816                         reg = <0x07 0x10>;
 817                 };
 818                 cpu_leakage: cpu-leakage@17 {
 819                         reg = <0x17 0x1>;
 820                 };
 821                 performance: performance@1e {
 822                         reg = <0x1e 0x1>;
 823                         bits = <4 3>;
 824                 };
 825         };
 826
 827         cru: clock-controller@ff2b0000 {
 828                 compatible = "rockchip,px30-cru";
 829                 reg = <0x0 0xff2b0000 0x0 0x1000>;
 830                 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
 831                 clock-names = "xin24m", "gpll";
 832                 rockchip,grf = <&grf>;
 833                 #clock-cells = <1>;
 834                 #reset-cells = <1>;
 835
 836                 assigned-clocks = <&cru PLL_NPLL>,
 837                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 838                         <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
 839                         <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
 840
 841                 assigned-clock-rates = <1188000000>,
 842                         <200000000>, <200000000>,
 843                         <150000000>, <150000000>,
 844                         <100000000>, <200000000>;
 845         };
 846
 847         pmucru: clock-controller@ff2bc000 {
 848                 compatible = "rockchip,px30-pmucru";
 849                 reg = <0x0 0xff2bc000 0x0 0x1000>;
 850                 clocks = <&xin24m>;
 851                 clock-names = "xin24m";
 852                 rockchip,grf = <&grf>;
 853                 #clock-cells = <1>;
 854                 #reset-cells = <1>;
 855
 856                 assigned-clocks =
 857                         <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
 858                         <&pmucru SCLK_WIFI_PMU>;
 859                 assigned-clock-rates =
 860                         <1200000000>, <100000000>,
 861                         <26000000>;
 862         };
 863
 864         usb2phy_grf: syscon@ff2c0000 {
 865                 compatible = "rockchip,px30-usb2phy-grf", "syscon",
 866                              "simple-mfd";
 867                 reg = <0x0 0xff2c0000 0x0 0x10000>;
 868                 #address-cells = <1>;
 869                 #size-cells = <1>;
 870
 871                 u2phy: usb2phy@100 {
 872                         compatible = "rockchip,px30-usb2phy";
 873                         reg = <0x100 0x20>;
 874                         clocks = <&pmucru SCLK_USBPHY_REF>;
 875                         clock-names = "phyclk";
 876                         #clock-cells = <0>;
 877                         assigned-clocks = <&cru USB480M>;
 878                         assigned-clock-parents = <&u2phy>;
 879                         clock-output-names = "usb480m_phy";
 880                         status = "disabled";
 881
 882                         u2phy_host: host-port {
 883                                 #phy-cells = <0>;
 884                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 885                                 interrupt-names = "linestate";
 886                                 status = "disabled";
 887                         };
 888
 889                         u2phy_otg: otg-port {
 890                                 #phy-cells = <0>;
 891                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 892                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 893                                              <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 894                                 interrupt-names = "otg-bvalid", "otg-id",
 895                                                   "linestate";
 896                                 status = "disabled";
 897                         };
 898                 };
 899         };
 900
 901         dsi_dphy: phy@ff2e0000 {
 902                 compatible = "rockchip,px30-dsi-dphy";
 903                 reg = <0x0 0xff2e0000 0x0 0x10000>;
 904                 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
 905                 clock-names = "ref", "pclk";
 906                 resets = <&cru SRST_MIPIDSIPHY_P>;
 907                 reset-names = "apb";
 908                 #phy-cells = <0>;
 909                 power-domains = <&power PX30_PD_VO>;
 910                 status = "disabled";
 911         };
 912
 913         csi_dphy: phy@ff2f0000 {
 914                 compatible = "rockchip,px30-csi-dphy";
 915                 reg = <0x0 0xff2f0000 0x0 0x4000>;
 916                 clocks = <&cru PCLK_MIPICSIPHY>;
 917                 clock-names = "pclk";
 918                 #phy-cells = <0>;
 919                 power-domains = <&power PX30_PD_VI>;
 920                 resets = <&cru SRST_MIPICSIPHY_P>;
 921                 reset-names = "apb";
 922                 rockchip,grf = <&grf>;
 923                 status = "disabled";
 924         };
 925
 926         usb20_otg: usb@ff300000 {
 927                 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
 928                              "snps,dwc2";
 929                 reg = <0x0 0xff300000 0x0 0x40000>;
 930                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 931                 clocks = <&cru HCLK_OTG>;
 932                 clock-names = "otg";
 933                 dr_mode = "otg";
 934                 g-np-tx-fifo-size = <16>;
 935                 g-rx-fifo-size = <280>;
 936                 g-tx-fifo-size = <256 128 128 64 32 16>;
 937                 phys = <&u2phy_otg>;
 938                 phy-names = "usb2-phy";
 939                 power-domains = <&power PX30_PD_USB>;
 940                 status = "disabled";
 941         };
 942
 943         usb_host0_ehci: usb@ff340000 {
 944                 compatible = "generic-ehci";
 945                 reg = <0x0 0xff340000 0x0 0x10000>;
 946                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 947                 clocks = <&cru HCLK_HOST>;
 948                 phys = <&u2phy_host>;
 949                 phy-names = "usb";
 950                 power-domains = <&power PX30_PD_USB>;
 951                 status = "disabled";
 952         };
 953
 954         usb_host0_ohci: usb@ff350000 {
 955                 compatible = "generic-ohci";
 956                 reg = <0x0 0xff350000 0x0 0x10000>;
 957                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 958                 clocks = <&cru HCLK_HOST>;
 959                 phys = <&u2phy_host>;
 960                 phy-names = "usb";
 961                 power-domains = <&power PX30_PD_USB>;
 962                 status = "disabled";
 963         };
 964
 965         gmac: ethernet@ff360000 {
 966                 compatible = "rockchip,px30-gmac";
 967                 reg = <0x0 0xff360000 0x0 0x10000>;
 968                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 969                 interrupt-names = "macirq";
 970                 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
 971                          <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
 972                          <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
 973                          <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
 974                 clock-names = "stmmaceth", "mac_clk_rx",
 975                               "mac_clk_tx", "clk_mac_ref",
 976                               "clk_mac_refout", "aclk_mac",
 977                               "pclk_mac", "clk_mac_speed";
 978                 rockchip,grf = <&grf>;
 979                 phy-mode = "rmii";
 980                 pinctrl-names = "default";
 981                 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
 982                 power-domains = <&power PX30_PD_GMAC>;
 983                 resets = <&cru SRST_GMAC_A>;
 984                 reset-names = "stmmaceth";
 985                 status = "disabled";
 986         };
 987
 988         sdmmc: mmc@ff370000 {
 989                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 990                 reg = <0x0 0xff370000 0x0 0x4000>;
 991                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 992                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 993                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 994                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 995                 bus-width = <4>;
 996                 fifo-depth = <0x100>;
 997                 max-frequency = <150000000>;
 998                 pinctrl-names = "default";
 999                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1000                 power-domains = <&power PX30_PD_SDCARD>;
1001                 status = "disabled";
1002         };
1003
1004         sdio: mmc@ff380000 {
1005                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1006                 reg = <0x0 0xff380000 0x0 0x4000>;
1007                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1008                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1009                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1010                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1011                 bus-width = <4>;
1012                 fifo-depth = <0x100>;
1013                 max-frequency = <150000000>;
1014                 pinctrl-names = "default";
1015                 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1016                 power-domains = <&power PX30_PD_MMC_NAND>;
1017                 status = "disabled";
1018         };
1019
1020         emmc: mmc@ff390000 {
1021                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1022                 reg = <0x0 0xff390000 0x0 0x4000>;
1023                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1024                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1025                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1026                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1027                 bus-width = <8>;
1028                 fifo-depth = <0x100>;
1029                 max-frequency = <150000000>;
1030                 pinctrl-names = "default";
1031                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1032                 power-domains = <&power PX30_PD_MMC_NAND>;
1033                 status = "disabled";
1034         };
1035
1036         sfc: spi@ff3a0000 {
1037                 compatible = "rockchip,sfc";
1038                 reg = <0x0 0xff3a0000 0x0 0x4000>;
1039                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1040                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1041                 clock-names = "clk_sfc", "hclk_sfc";
1042                 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1043                 pinctrl-names = "default";
1044                 power-domains = <&power PX30_PD_MMC_NAND>;
1045                 status = "disabled";
1046         };
1047
1048         nfc: nand-controller@ff3b0000 {
1049                 compatible = "rockchip,px30-nfc";
1050                 reg = <0x0 0xff3b0000 0x0 0x4000>;
1051                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1052                 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
1053                 clock-names = "ahb", "nfc";
1054                 assigned-clocks = <&cru SCLK_NANDC>;
1055                 assigned-clock-rates = <150000000>;
1056                 pinctrl-names = "default";
1057                 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1058                              &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
1059                 power-domains = <&power PX30_PD_MMC_NAND>;
1060                 status = "disabled";
1061         };
1062
1063         gpu_opp_table: opp-table-1 {
1064                 compatible = "operating-points-v2";
1065
1066                 opp-200000000 {
1067                         opp-hz = /bits/ 64 <200000000>;
1068                         opp-microvolt = <950000>;
1069                 };
1070                 opp-300000000 {
1071                         opp-hz = /bits/ 64 <300000000>;
1072                         opp-microvolt = <975000>;
1073                 };
1074                 opp-400000000 {
1075                         opp-hz = /bits/ 64 <400000000>;
1076                         opp-microvolt = <1050000>;
1077                 };
1078                 opp-480000000 {
1079                         opp-hz = /bits/ 64 <480000000>;
1080                         opp-microvolt = <1125000>;
1081                 };
1082         };
1083
1084         gpu: gpu@ff400000 {
1085                 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1086                 reg = <0x0 0xff400000 0x0 0x4000>;
1087                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1088                              <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1089                              <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1090                 interrupt-names = "job", "mmu", "gpu";
1091                 clocks = <&cru SCLK_GPU>;
1092                 #cooling-cells = <2>;
1093                 power-domains = <&power PX30_PD_GPU>;
1094                 operating-points-v2 = <&gpu_opp_table>;
1095                 status = "disabled";
1096         };
1097
1098         vpu: video-codec@ff442000 {
1099                 compatible = "rockchip,px30-vpu";
1100                 reg = <0x0 0xff442000 0x0 0x800>;
1101                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
1102                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1103                 interrupt-names = "vepu", "vdpu";
1104                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1105                 clock-names = "aclk", "hclk";
1106                 iommus = <&vpu_mmu>;
1107                 power-domains = <&power PX30_PD_VPU>;
1108         };
1109
1110         vpu_mmu: iommu@ff442800 {
1111                 compatible = "rockchip,iommu";
1112                 reg = <0x0 0xff442800 0x0 0x100>;
1113                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1114                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1115                 clock-names = "aclk", "iface";
1116                 #iommu-cells = <0>;
1117                 power-domains = <&power PX30_PD_VPU>;
1118         };
1119
1120         dsi: dsi@ff450000 {
1121                 compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi";
1122                 reg = <0x0 0xff450000 0x0 0x10000>;
1123                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1124                 clocks = <&cru PCLK_MIPI_DSI>;
1125                 clock-names = "pclk";
1126                 phys = <&dsi_dphy>;
1127                 phy-names = "dphy";
1128                 power-domains = <&power PX30_PD_VO>;
1129                 resets = <&cru SRST_MIPIDSI_HOST_P>;
1130                 reset-names = "apb";
1131                 rockchip,grf = <&grf>;
1132                 #address-cells = <1>;
1133                 #size-cells = <0>;
1134                 status = "disabled";
1135
1136                 ports {
1137                         #address-cells = <1>;
1138                         #size-cells = <0>;
1139
1140                         dsi_in: port@0 {
1141                                 reg = <0>;
1142                                 #address-cells = <1>;
1143                                 #size-cells = <0>;
1144
1145                                 dsi_in_vopb: endpoint@0 {
1146                                         reg = <0>;
1147                                         remote-endpoint = <&vopb_out_dsi>;
1148                                 };
1149
1150                                 dsi_in_vopl: endpoint@1 {
1151                                         reg = <1>;
1152                                         remote-endpoint = <&vopl_out_dsi>;
1153                                 };
1154                         };
1155
1156                         dsi_out: port@1 {
1157                                 reg = <1>;
1158                         };
1159                 };
1160         };
1161
1162         vopb: vop@ff460000 {
1163                 compatible = "rockchip,px30-vop-big";
1164                 reg = <0x0 0xff460000 0x0 0xefc>;
1165                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1166                 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1167                          <&cru HCLK_VOPB>;
1168                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1169                 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1170                 reset-names = "axi", "ahb", "dclk";
1171                 iommus = <&vopb_mmu>;
1172                 power-domains = <&power PX30_PD_VO>;
1173                 status = "disabled";
1174
1175                 vopb_out: port {
1176                         #address-cells = <1>;
1177                         #size-cells = <0>;
1178
1179                         vopb_out_dsi: endpoint@0 {
1180                                 reg = <0>;
1181                                 remote-endpoint = <&dsi_in_vopb>;
1182                         };
1183
1184                         vopb_out_lvds: endpoint@1 {
1185                                 reg = <1>;
1186                                 remote-endpoint = <&lvds_vopb_in>;
1187                         };
1188                 };
1189         };
1190
1191         vopb_mmu: iommu@ff460f00 {
1192                 compatible = "rockchip,iommu";
1193                 reg = <0x0 0xff460f00 0x0 0x100>;
1194                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1195                 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1196                 clock-names = "aclk", "iface";
1197                 power-domains = <&power PX30_PD_VO>;
1198                 #iommu-cells = <0>;
1199                 status = "disabled";
1200         };
1201
1202         vopl: vop@ff470000 {
1203                 compatible = "rockchip,px30-vop-lit";
1204                 reg = <0x0 0xff470000 0x0 0xefc>;
1205                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1206                 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1207                          <&cru HCLK_VOPL>;
1208                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1209                 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1210                 reset-names = "axi", "ahb", "dclk";
1211                 iommus = <&vopl_mmu>;
1212                 power-domains = <&power PX30_PD_VO>;
1213                 status = "disabled";
1214
1215                 vopl_out: port {
1216                         #address-cells = <1>;
1217                         #size-cells = <0>;
1218
1219                         vopl_out_dsi: endpoint@0 {
1220                                 reg = <0>;
1221                                 remote-endpoint = <&dsi_in_vopl>;
1222                         };
1223
1224                         vopl_out_lvds: endpoint@1 {
1225                                 reg = <1>;
1226                                 remote-endpoint = <&lvds_vopl_in>;
1227                         };
1228                 };
1229         };
1230
1231         vopl_mmu: iommu@ff470f00 {
1232                 compatible = "rockchip,iommu";
1233                 reg = <0x0 0xff470f00 0x0 0x100>;
1234                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1235                 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1236                 clock-names = "aclk", "iface";
1237                 power-domains = <&power PX30_PD_VO>;
1238                 #iommu-cells = <0>;
1239                 status = "disabled";
1240         };
1241
1242         isp: isp@ff4a0000 {
1243                 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
1244                 reg = <0x0 0xff4a0000 0x0 0x8000>;
1245                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1246                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1247                              <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1248                 interrupt-names = "isp", "mi", "mipi";
1249                 clocks = <&cru SCLK_ISP>,
1250                          <&cru ACLK_ISP>,
1251                          <&cru HCLK_ISP>,
1252                          <&cru PCLK_ISP>;
1253                 clock-names = "isp", "aclk", "hclk", "pclk";
1254                 iommus = <&isp_mmu>;
1255                 phys = <&csi_dphy>;
1256                 phy-names = "dphy";
1257                 power-domains = <&power PX30_PD_VI>;
1258                 status = "disabled";
1259
1260                 ports {
1261                         #address-cells = <1>;
1262                         #size-cells = <0>;
1263
1264                         port@0 {
1265                                 reg = <0>;
1266                                 #address-cells = <1>;
1267                                 #size-cells = <0>;
1268                         };
1269                 };
1270         };
1271
1272         isp_mmu: iommu@ff4a8000 {
1273                 compatible = "rockchip,iommu";
1274                 reg = <0x0 0xff4a8000 0x0 0x100>;
1275                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1276                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1277                 clock-names = "aclk", "iface";
1278                 power-domains = <&power PX30_PD_VI>;
1279                 rockchip,disable-mmu-reset;
1280                 #iommu-cells = <0>;
1281         };
1282
1283         qos_gmac: qos@ff518000 {
1284                 compatible = "rockchip,px30-qos", "syscon";
1285                 reg = <0x0 0xff518000 0x0 0x20>;
1286         };
1287
1288         qos_gpu: qos@ff520000 {
1289                 compatible = "rockchip,px30-qos", "syscon";
1290                 reg = <0x0 0xff520000 0x0 0x20>;
1291         };
1292
1293         qos_sdmmc: qos@ff52c000 {
1294                 compatible = "rockchip,px30-qos", "syscon";
1295                 reg = <0x0 0xff52c000 0x0 0x20>;
1296         };
1297
1298         qos_emmc: qos@ff538000 {
1299                 compatible = "rockchip,px30-qos", "syscon";
1300                 reg = <0x0 0xff538000 0x0 0x20>;
1301         };
1302
1303         qos_nand: qos@ff538080 {
1304                 compatible = "rockchip,px30-qos", "syscon";
1305                 reg = <0x0 0xff538080 0x0 0x20>;
1306         };
1307
1308         qos_sdio: qos@ff538100 {
1309                 compatible = "rockchip,px30-qos", "syscon";
1310                 reg = <0x0 0xff538100 0x0 0x20>;
1311         };
1312
1313         qos_sfc: qos@ff538180 {
1314                 compatible = "rockchip,px30-qos", "syscon";
1315                 reg = <0x0 0xff538180 0x0 0x20>;
1316         };
1317
1318         qos_usb_host: qos@ff540000 {
1319                 compatible = "rockchip,px30-qos", "syscon";
1320                 reg = <0x0 0xff540000 0x0 0x20>;
1321         };
1322
1323         qos_usb_otg: qos@ff540080 {
1324                 compatible = "rockchip,px30-qos", "syscon";
1325                 reg = <0x0 0xff540080 0x0 0x20>;
1326         };
1327
1328         qos_isp_128: qos@ff548000 {
1329                 compatible = "rockchip,px30-qos", "syscon";
1330                 reg = <0x0 0xff548000 0x0 0x20>;
1331         };
1332
1333         qos_isp_rd: qos@ff548080 {
1334                 compatible = "rockchip,px30-qos", "syscon";
1335                 reg = <0x0 0xff548080 0x0 0x20>;
1336         };
1337
1338         qos_isp_wr: qos@ff548100 {
1339                 compatible = "rockchip,px30-qos", "syscon";
1340                 reg = <0x0 0xff548100 0x0 0x20>;
1341         };
1342
1343         qos_isp_m1: qos@ff548180 {
1344                 compatible = "rockchip,px30-qos", "syscon";
1345                 reg = <0x0 0xff548180 0x0 0x20>;
1346         };
1347
1348         qos_vip: qos@ff548200 {
1349                 compatible = "rockchip,px30-qos", "syscon";
1350                 reg = <0x0 0xff548200 0x0 0x20>;
1351         };
1352
1353         qos_rga_rd: qos@ff550000 {
1354                 compatible = "rockchip,px30-qos", "syscon";
1355                 reg = <0x0 0xff550000 0x0 0x20>;
1356         };
1357
1358         qos_rga_wr: qos@ff550080 {
1359                 compatible = "rockchip,px30-qos", "syscon";
1360                 reg = <0x0 0xff550080 0x0 0x20>;
1361         };
1362
1363         qos_vop_m0: qos@ff550100 {
1364                 compatible = "rockchip,px30-qos", "syscon";
1365                 reg = <0x0 0xff550100 0x0 0x20>;
1366         };
1367
1368         qos_vop_m1: qos@ff550180 {
1369                 compatible = "rockchip,px30-qos", "syscon";
1370                 reg = <0x0 0xff550180 0x0 0x20>;
1371         };
1372
1373         qos_vpu: qos@ff558000 {
1374                 compatible = "rockchip,px30-qos", "syscon";
1375                 reg = <0x0 0xff558000 0x0 0x20>;
1376         };
1377
1378         qos_vpu_r128: qos@ff558080 {
1379                 compatible = "rockchip,px30-qos", "syscon";
1380                 reg = <0x0 0xff558080 0x0 0x20>;
1381         };
1382
1383         pinctrl: pinctrl {
1384                 compatible = "rockchip,px30-pinctrl";
1385                 rockchip,grf = <&grf>;
1386                 rockchip,pmu = <&pmugrf>;
1387                 #address-cells = <2>;
1388                 #size-cells = <2>;
1389                 ranges;
1390
1391                 gpio0: gpio@ff040000 {
1392                         compatible = "rockchip,gpio-bank";
1393                         reg = <0x0 0xff040000 0x0 0x100>;
1394                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1395                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1396                         gpio-controller;
1397                         #gpio-cells = <2>;
1398
1399                         interrupt-controller;
1400                         #interrupt-cells = <2>;
1401                 };
1402
1403                 gpio1: gpio@ff250000 {
1404                         compatible = "rockchip,gpio-bank";
1405                         reg = <0x0 0xff250000 0x0 0x100>;
1406                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1407                         clocks = <&cru PCLK_GPIO1>;
1408                         gpio-controller;
1409                         #gpio-cells = <2>;
1410
1411                         interrupt-controller;
1412                         #interrupt-cells = <2>;
1413                 };
1414
1415                 gpio2: gpio@ff260000 {
1416                         compatible = "rockchip,gpio-bank";
1417                         reg = <0x0 0xff260000 0x0 0x100>;
1418                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1419                         clocks = <&cru PCLK_GPIO2>;
1420                         gpio-controller;
1421                         #gpio-cells = <2>;
1422
1423                         interrupt-controller;
1424                         #interrupt-cells = <2>;
1425                 };
1426
1427                 gpio3: gpio@ff270000 {
1428                         compatible = "rockchip,gpio-bank";
1429                         reg = <0x0 0xff270000 0x0 0x100>;
1430                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1431                         clocks = <&cru PCLK_GPIO3>;
1432                         gpio-controller;
1433                         #gpio-cells = <2>;
1434
1435                         interrupt-controller;
1436                         #interrupt-cells = <2>;
1437                 };
1438
1439                 pcfg_pull_up: pcfg-pull-up {
1440                         bias-pull-up;
1441                 };
1442
1443                 pcfg_pull_down: pcfg-pull-down {
1444                         bias-pull-down;
1445                 };
1446
1447                 pcfg_pull_none: pcfg-pull-none {
1448                         bias-disable;
1449                 };
1450
1451                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1452                         bias-disable;
1453                         drive-strength = <2>;
1454                 };
1455
1456                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1457                         bias-pull-up;
1458                         drive-strength = <2>;
1459                 };
1460
1461                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1462                         bias-pull-up;
1463                         drive-strength = <4>;
1464                 };
1465
1466                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1467                         bias-disable;
1468                         drive-strength = <4>;
1469                 };
1470
1471                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1472                         bias-pull-down;
1473                         drive-strength = <4>;
1474                 };
1475
1476                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1477                         bias-disable;
1478                         drive-strength = <8>;
1479                 };
1480
1481                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1482                         bias-pull-up;
1483                         drive-strength = <8>;
1484                 };
1485
1486                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1487                         bias-disable;
1488                         drive-strength = <12>;
1489                 };
1490
1491                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1492                         bias-pull-up;
1493                         drive-strength = <12>;
1494                 };
1495
1496                 pcfg_pull_none_smt: pcfg-pull-none-smt {
1497                         bias-disable;
1498                         input-schmitt-enable;
1499                 };
1500
1501                 pcfg_output_high: pcfg-output-high {
1502                         output-high;
1503                 };
1504
1505                 pcfg_output_low: pcfg-output-low {
1506                         output-low;
1507                 };
1508
1509                 pcfg_input_high: pcfg-input-high {
1510                         bias-pull-up;
1511                         input-enable;
1512                 };
1513
1514                 pcfg_input: pcfg-input {
1515                         input-enable;
1516                 };
1517
1518                 i2c0 {
1519                         i2c0_xfer: i2c0-xfer {
1520                                 rockchip,pins =
1521                                         <0 RK_PB0 1 &pcfg_pull_none_smt>,
1522                                         <0 RK_PB1 1 &pcfg_pull_none_smt>;
1523                         };
1524                 };
1525
1526                 i2c1 {
1527                         i2c1_xfer: i2c1-xfer {
1528                                 rockchip,pins =
1529                                         <0 RK_PC2 1 &pcfg_pull_none_smt>,
1530                                         <0 RK_PC3 1 &pcfg_pull_none_smt>;
1531                         };
1532                 };
1533
1534                 i2c2 {
1535                         i2c2_xfer: i2c2-xfer {
1536                                 rockchip,pins =
1537                                         <2 RK_PB7 2 &pcfg_pull_none_smt>,
1538                                         <2 RK_PC0 2 &pcfg_pull_none_smt>;
1539                         };
1540                 };
1541
1542                 i2c3 {
1543                         i2c3_xfer: i2c3-xfer {
1544                                 rockchip,pins =
1545                                         <1 RK_PB4 4 &pcfg_pull_none_smt>,
1546                                         <1 RK_PB5 4 &pcfg_pull_none_smt>;
1547                         };
1548                 };
1549
1550                 tsadc {
1551                         tsadc_otp_pin: tsadc-otp-pin {
1552                                 rockchip,pins =
1553                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1554                         };
1555
1556                         tsadc_otp_out: tsadc-otp-out {
1557                                 rockchip,pins =
1558                                         <0 RK_PA6 1 &pcfg_pull_none>;
1559                         };
1560                 };
1561
1562                 uart0 {
1563                         uart0_xfer: uart0-xfer {
1564                                 rockchip,pins =
1565                                         <0 RK_PB2 1 &pcfg_pull_up>,
1566                                         <0 RK_PB3 1 &pcfg_pull_up>;
1567                         };
1568
1569                         uart0_cts: uart0-cts {
1570                                 rockchip,pins =
1571                                         <0 RK_PB4 1 &pcfg_pull_none>;
1572                         };
1573
1574                         uart0_rts: uart0-rts {
1575                                 rockchip,pins =
1576                                         <0 RK_PB5 1 &pcfg_pull_none>;
1577                         };
1578                 };
1579
1580                 uart1 {
1581                         uart1_xfer: uart1-xfer {
1582                                 rockchip,pins =
1583                                         <1 RK_PC1 1 &pcfg_pull_up>,
1584                                         <1 RK_PC0 1 &pcfg_pull_up>;
1585                         };
1586
1587                         uart1_cts: uart1-cts {
1588                                 rockchip,pins =
1589                                         <1 RK_PC2 1 &pcfg_pull_none>;
1590                         };
1591
1592                         uart1_rts: uart1-rts {
1593                                 rockchip,pins =
1594                                         <1 RK_PC3 1 &pcfg_pull_none>;
1595                         };
1596                 };
1597
1598                 uart2-m0 {
1599                         uart2m0_xfer: uart2m0-xfer {
1600                                 rockchip,pins =
1601                                         <1 RK_PD2 2 &pcfg_pull_up>,
1602                                         <1 RK_PD3 2 &pcfg_pull_up>;
1603                         };
1604                 };
1605
1606                 uart2-m1 {
1607                         uart2m1_xfer: uart2m1-xfer {
1608                                 rockchip,pins =
1609                                         <2 RK_PB4 2 &pcfg_pull_up>,
1610                                         <2 RK_PB6 2 &pcfg_pull_up>;
1611                         };
1612                 };
1613
1614                 uart3-m0 {
1615                         uart3m0_xfer: uart3m0-xfer {
1616                                 rockchip,pins =
1617                                         <0 RK_PC0 2 &pcfg_pull_up>,
1618                                         <0 RK_PC1 2 &pcfg_pull_up>;
1619                         };
1620
1621                         uart3m0_cts: uart3m0-cts {
1622                                 rockchip,pins =
1623                                         <0 RK_PC2 2 &pcfg_pull_none>;
1624                         };
1625
1626                         uart3m0_rts: uart3m0-rts {
1627                                 rockchip,pins =
1628                                         <0 RK_PC3 2 &pcfg_pull_none>;
1629                         };
1630                 };
1631
1632                 uart3-m1 {
1633                         uart3m1_xfer: uart3m1-xfer {
1634                                 rockchip,pins =
1635                                         <1 RK_PB6 2 &pcfg_pull_up>,
1636                                         <1 RK_PB7 2 &pcfg_pull_up>;
1637                         };
1638
1639                         uart3m1_cts: uart3m1-cts {
1640                                 rockchip,pins =
1641                                         <1 RK_PB4 2 &pcfg_pull_none>;
1642                         };
1643
1644                         uart3m1_rts: uart3m1-rts {
1645                                 rockchip,pins =
1646                                         <1 RK_PB5 2 &pcfg_pull_none>;
1647                         };
1648                 };
1649
1650                 uart4 {
1651                         uart4_xfer: uart4-xfer {
1652                                 rockchip,pins =
1653                                         <1 RK_PD4 2 &pcfg_pull_up>,
1654                                         <1 RK_PD5 2 &pcfg_pull_up>;
1655                         };
1656
1657                         uart4_cts: uart4-cts {
1658                                 rockchip,pins =
1659                                         <1 RK_PD6 2 &pcfg_pull_none>;
1660                         };
1661
1662                         uart4_rts: uart4-rts {
1663                                 rockchip,pins =
1664                                         <1 RK_PD7 2 &pcfg_pull_none>;
1665                         };
1666                 };
1667
1668                 uart5 {
1669                         uart5_xfer: uart5-xfer {
1670                                 rockchip,pins =
1671                                         <3 RK_PA2 4 &pcfg_pull_up>,
1672                                         <3 RK_PA1 4 &pcfg_pull_up>;
1673                         };
1674
1675                         uart5_cts: uart5-cts {
1676                                 rockchip,pins =
1677                                         <3 RK_PA3 4 &pcfg_pull_none>;
1678                         };
1679
1680                         uart5_rts: uart5-rts {
1681                                 rockchip,pins =
1682                                         <3 RK_PA5 4 &pcfg_pull_none>;
1683                         };
1684                 };
1685
1686                 spi0 {
1687                         spi0_clk: spi0-clk {
1688                                 rockchip,pins =
1689                                         <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1690                         };
1691
1692                         spi0_csn: spi0-csn {
1693                                 rockchip,pins =
1694                                         <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1695                         };
1696
1697                         spi0_miso: spi0-miso {
1698                                 rockchip,pins =
1699                                         <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1700                         };
1701
1702                         spi0_mosi: spi0-mosi {
1703                                 rockchip,pins =
1704                                         <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1705                         };
1706
1707                         spi0_clk_hs: spi0-clk-hs {
1708                                 rockchip,pins =
1709                                         <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1710                         };
1711
1712                         spi0_miso_hs: spi0-miso-hs {
1713                                 rockchip,pins =
1714                                         <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1715                         };
1716
1717                         spi0_mosi_hs: spi0-mosi-hs {
1718                                 rockchip,pins =
1719                                         <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1720                         };
1721                 };
1722
1723                 spi1 {
1724                         spi1_clk: spi1-clk {
1725                                 rockchip,pins =
1726                                         <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1727                         };
1728
1729                         spi1_csn0: spi1-csn0 {
1730                                 rockchip,pins =
1731                                         <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1732                         };
1733
1734                         spi1_csn1: spi1-csn1 {
1735                                 rockchip,pins =
1736                                         <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1737                         };
1738
1739                         spi1_miso: spi1-miso {
1740                                 rockchip,pins =
1741                                         <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1742                         };
1743
1744                         spi1_mosi: spi1-mosi {
1745                                 rockchip,pins =
1746                                         <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1747                         };
1748
1749                         spi1_clk_hs: spi1-clk-hs {
1750                                 rockchip,pins =
1751                                         <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1752                         };
1753
1754                         spi1_miso_hs: spi1-miso-hs {
1755                                 rockchip,pins =
1756                                         <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1757                         };
1758
1759                         spi1_mosi_hs: spi1-mosi-hs {
1760                                 rockchip,pins =
1761                                         <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1762                         };
1763                 };
1764
1765                 pdm {
1766                         pdm_clk0m0: pdm-clk0m0 {
1767                                 rockchip,pins =
1768                                         <3 RK_PC6 2 &pcfg_pull_none>;
1769                         };
1770
1771                         pdm_clk0m1: pdm-clk0m1 {
1772                                 rockchip,pins =
1773                                         <2 RK_PC6 1 &pcfg_pull_none>;
1774                         };
1775
1776                         pdm_clk1: pdm-clk1 {
1777                                 rockchip,pins =
1778                                         <3 RK_PC7 2 &pcfg_pull_none>;
1779                         };
1780
1781                         pdm_sdi0m0: pdm-sdi0m0 {
1782                                 rockchip,pins =
1783                                         <3 RK_PD3 2 &pcfg_pull_none>;
1784                         };
1785
1786                         pdm_sdi0m1: pdm-sdi0m1 {
1787                                 rockchip,pins =
1788                                         <2 RK_PC5 2 &pcfg_pull_none>;
1789                         };
1790
1791                         pdm_sdi1: pdm-sdi1 {
1792                                 rockchip,pins =
1793                                         <3 RK_PD0 2 &pcfg_pull_none>;
1794                         };
1795
1796                         pdm_sdi2: pdm-sdi2 {
1797                                 rockchip,pins =
1798                                         <3 RK_PD1 2 &pcfg_pull_none>;
1799                         };
1800
1801                         pdm_sdi3: pdm-sdi3 {
1802                                 rockchip,pins =
1803                                         <3 RK_PD2 2 &pcfg_pull_none>;
1804                         };
1805
1806                         pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1807                                 rockchip,pins =
1808                                         <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1809                         };
1810
1811                         pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1812                                 rockchip,pins =
1813                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1814                         };
1815
1816                         pdm_clk1_sleep: pdm-clk1-sleep {
1817                                 rockchip,pins =
1818                                         <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1819                         };
1820
1821                         pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1822                                 rockchip,pins =
1823                                         <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1824                         };
1825
1826                         pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1827                                 rockchip,pins =
1828                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1829                         };
1830
1831                         pdm_sdi1_sleep: pdm-sdi1-sleep {
1832                                 rockchip,pins =
1833                                         <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1834                         };
1835
1836                         pdm_sdi2_sleep: pdm-sdi2-sleep {
1837                                 rockchip,pins =
1838                                         <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1839                         };
1840
1841                         pdm_sdi3_sleep: pdm-sdi3-sleep {
1842                                 rockchip,pins =
1843                                         <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1844                         };
1845                 };
1846
1847                 i2s0 {
1848                         i2s0_8ch_mclk: i2s0-8ch-mclk {
1849                                 rockchip,pins =
1850                                         <3 RK_PC1 2 &pcfg_pull_none>;
1851                         };
1852
1853                         i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1854                                 rockchip,pins =
1855                                         <3 RK_PC3 2 &pcfg_pull_none>;
1856                         };
1857
1858                         i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1859                                 rockchip,pins =
1860                                         <3 RK_PB4 2 &pcfg_pull_none>;
1861                         };
1862
1863                         i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1864                                 rockchip,pins =
1865                                         <3 RK_PC2 2 &pcfg_pull_none>;
1866                         };
1867
1868                         i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1869                                 rockchip,pins =
1870                                         <3 RK_PB5 2 &pcfg_pull_none>;
1871                         };
1872
1873                         i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1874                                 rockchip,pins =
1875                                         <3 RK_PC4 2 &pcfg_pull_none>;
1876                         };
1877
1878                         i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1879                                 rockchip,pins =
1880                                         <3 RK_PC0 2 &pcfg_pull_none>;
1881                         };
1882
1883                         i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1884                                 rockchip,pins =
1885                                         <3 RK_PB7 2 &pcfg_pull_none>;
1886                         };
1887
1888                         i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1889                                 rockchip,pins =
1890                                         <3 RK_PB6 2 &pcfg_pull_none>;
1891                         };
1892
1893                         i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1894                                 rockchip,pins =
1895                                         <3 RK_PC5 2 &pcfg_pull_none>;
1896                         };
1897
1898                         i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1899                                 rockchip,pins =
1900                                         <3 RK_PB3 2 &pcfg_pull_none>;
1901                         };
1902
1903                         i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1904                                 rockchip,pins =
1905                                         <3 RK_PB1 2 &pcfg_pull_none>;
1906                         };
1907
1908                         i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1909                                 rockchip,pins =
1910                                         <3 RK_PB0 2 &pcfg_pull_none>;
1911                         };
1912                 };
1913
1914                 i2s1 {
1915                         i2s1_2ch_mclk: i2s1-2ch-mclk {
1916                                 rockchip,pins =
1917                                         <2 RK_PC3 1 &pcfg_pull_none>;
1918                         };
1919
1920                         i2s1_2ch_sclk: i2s1-2ch-sclk {
1921                                 rockchip,pins =
1922                                         <2 RK_PC2 1 &pcfg_pull_none>;
1923                         };
1924
1925                         i2s1_2ch_lrck: i2s1-2ch-lrck {
1926                                 rockchip,pins =
1927                                         <2 RK_PC1 1 &pcfg_pull_none>;
1928                         };
1929
1930                         i2s1_2ch_sdi: i2s1-2ch-sdi {
1931                                 rockchip,pins =
1932                                         <2 RK_PC5 1 &pcfg_pull_none>;
1933                         };
1934
1935                         i2s1_2ch_sdo: i2s1-2ch-sdo {
1936                                 rockchip,pins =
1937                                         <2 RK_PC4 1 &pcfg_pull_none>;
1938                         };
1939                 };
1940
1941                 i2s2 {
1942                         i2s2_2ch_mclk: i2s2-2ch-mclk {
1943                                 rockchip,pins =
1944                                         <3 RK_PA1 2 &pcfg_pull_none>;
1945                         };
1946
1947                         i2s2_2ch_sclk: i2s2-2ch-sclk {
1948                                 rockchip,pins =
1949                                         <3 RK_PA2 2 &pcfg_pull_none>;
1950                         };
1951
1952                         i2s2_2ch_lrck: i2s2-2ch-lrck {
1953                                 rockchip,pins =
1954                                         <3 RK_PA3 2 &pcfg_pull_none>;
1955                         };
1956
1957                         i2s2_2ch_sdi: i2s2-2ch-sdi {
1958                                 rockchip,pins =
1959                                         <3 RK_PA5 2 &pcfg_pull_none>;
1960                         };
1961
1962                         i2s2_2ch_sdo: i2s2-2ch-sdo {
1963                                 rockchip,pins =
1964                                         <3 RK_PA7 2 &pcfg_pull_none>;
1965                         };
1966                 };
1967
1968                 sdmmc {
1969                         sdmmc_clk: sdmmc-clk {
1970                                 rockchip,pins =
1971                                         <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1972                         };
1973
1974                         sdmmc_cmd: sdmmc-cmd {
1975                                 rockchip,pins =
1976                                         <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1977                         };
1978
1979                         sdmmc_det: sdmmc-det {
1980                                 rockchip,pins =
1981                                         <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1982                         };
1983
1984                         sdmmc_bus1: sdmmc-bus1 {
1985                                 rockchip,pins =
1986                                         <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1987                         };
1988
1989                         sdmmc_bus4: sdmmc-bus4 {
1990                                 rockchip,pins =
1991                                         <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1992                                         <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1993                                         <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1994                                         <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1995                         };
1996                 };
1997
1998                 sdio {
1999                         sdio_clk: sdio-clk {
2000                                 rockchip,pins =
2001                                         <1 RK_PC5 1 &pcfg_pull_none>;
2002                         };
2003
2004                         sdio_cmd: sdio-cmd {
2005                                 rockchip,pins =
2006                                         <1 RK_PC4 1 &pcfg_pull_up>;
2007                         };
2008
2009                         sdio_bus4: sdio-bus4 {
2010                                 rockchip,pins =
2011                                         <1 RK_PC6 1 &pcfg_pull_up>,
2012                                         <1 RK_PC7 1 &pcfg_pull_up>,
2013                                         <1 RK_PD0 1 &pcfg_pull_up>,
2014                                         <1 RK_PD1 1 &pcfg_pull_up>;
2015                         };
2016                 };
2017
2018                 emmc {
2019                         emmc_clk: emmc-clk {
2020                                 rockchip,pins =
2021                                         <1 RK_PB1 2 &pcfg_pull_none_8ma>;
2022                         };
2023
2024                         emmc_cmd: emmc-cmd {
2025                                 rockchip,pins =
2026                                         <1 RK_PB2 2 &pcfg_pull_up_8ma>;
2027                         };
2028
2029                         emmc_rstnout: emmc-rstnout {
2030                                 rockchip,pins =
2031                                         <1 RK_PB3 2 &pcfg_pull_none>;
2032                         };
2033
2034                         emmc_bus1: emmc-bus1 {
2035                                 rockchip,pins =
2036                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>;
2037                         };
2038
2039                         emmc_bus4: emmc-bus4 {
2040                                 rockchip,pins =
2041                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2042                                         <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2043                                         <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2044                                         <1 RK_PA3 2 &pcfg_pull_up_8ma>;
2045                         };
2046
2047                         emmc_bus8: emmc-bus8 {
2048                                 rockchip,pins =
2049                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2050                                         <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2051                                         <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2052                                         <1 RK_PA3 2 &pcfg_pull_up_8ma>,
2053                                         <1 RK_PA4 2 &pcfg_pull_up_8ma>,
2054                                         <1 RK_PA5 2 &pcfg_pull_up_8ma>,
2055                                         <1 RK_PA6 2 &pcfg_pull_up_8ma>,
2056                                         <1 RK_PA7 2 &pcfg_pull_up_8ma>;
2057                         };
2058                 };
2059
2060                 flash {
2061                         flash_cs0: flash-cs0 {
2062                                 rockchip,pins =
2063                                         <1 RK_PB0 1 &pcfg_pull_none>;
2064                         };
2065
2066                         flash_rdy: flash-rdy {
2067                                 rockchip,pins =
2068                                         <1 RK_PB1 1 &pcfg_pull_none>;
2069                         };
2070
2071                         flash_dqs: flash-dqs {
2072                                 rockchip,pins =
2073                                         <1 RK_PB2 1 &pcfg_pull_none>;
2074                         };
2075
2076                         flash_ale: flash-ale {
2077                                 rockchip,pins =
2078                                         <1 RK_PB3 1 &pcfg_pull_none>;
2079                         };
2080
2081                         flash_cle: flash-cle {
2082                                 rockchip,pins =
2083                                         <1 RK_PB4 1 &pcfg_pull_none>;
2084                         };
2085
2086                         flash_wrn: flash-wrn {
2087                                 rockchip,pins =
2088                                         <1 RK_PB5 1 &pcfg_pull_none>;
2089                         };
2090
2091                         flash_csl: flash-csl {
2092                                 rockchip,pins =
2093                                         <1 RK_PB6 1 &pcfg_pull_none>;
2094                         };
2095
2096                         flash_rdn: flash-rdn {
2097                                 rockchip,pins =
2098                                         <1 RK_PB7 1 &pcfg_pull_none>;
2099                         };
2100
2101                         flash_bus8: flash-bus8 {
2102                                 rockchip,pins =
2103                                         <1 RK_PA0 1 &pcfg_pull_up_12ma>,
2104                                         <1 RK_PA1 1 &pcfg_pull_up_12ma>,
2105                                         <1 RK_PA2 1 &pcfg_pull_up_12ma>,
2106                                         <1 RK_PA3 1 &pcfg_pull_up_12ma>,
2107                                         <1 RK_PA4 1 &pcfg_pull_up_12ma>,
2108                                         <1 RK_PA5 1 &pcfg_pull_up_12ma>,
2109                                         <1 RK_PA6 1 &pcfg_pull_up_12ma>,
2110                                         <1 RK_PA7 1 &pcfg_pull_up_12ma>;
2111                         };
2112                 };
2113
2114                 sfc {
2115                         sfc_bus4: sfc-bus4 {
2116                                 rockchip,pins =
2117                                         <1 RK_PA0 3 &pcfg_pull_none>,
2118                                         <1 RK_PA1 3 &pcfg_pull_none>,
2119                                         <1 RK_PA2 3 &pcfg_pull_none>,
2120                                         <1 RK_PA3 3 &pcfg_pull_none>;
2121                         };
2122
2123                         sfc_bus2: sfc-bus2 {
2124                                 rockchip,pins =
2125                                         <1 RK_PA0 3 &pcfg_pull_none>,
2126                                         <1 RK_PA1 3 &pcfg_pull_none>;
2127                         };
2128
2129                         sfc_cs0: sfc-cs0 {
2130                                 rockchip,pins =
2131                                         <1 RK_PA4 3 &pcfg_pull_none>;
2132                         };
2133
2134                         sfc_clk: sfc-clk {
2135                                 rockchip,pins =
2136                                         <1 RK_PB1 3 &pcfg_pull_none>;
2137                         };
2138                 };
2139
2140                 lcdc {
2141                         lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2142                                 rockchip,pins =
2143                                         <3 RK_PA0 1 &pcfg_pull_none_12ma>;
2144                         };
2145
2146                         lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2147                                 rockchip,pins =
2148                                         <3 RK_PA1 1 &pcfg_pull_none_12ma>;
2149                         };
2150
2151                         lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2152                                 rockchip,pins =
2153                                         <3 RK_PA2 1 &pcfg_pull_none_12ma>;
2154                         };
2155
2156                         lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2157                                 rockchip,pins =
2158                                         <3 RK_PA3 1 &pcfg_pull_none_12ma>;
2159                         };
2160
2161                         lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2162                                 rockchip,pins =
2163                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2164                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2165                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2166                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2167                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2168                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2169                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2170                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2171                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2172                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2173                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2174                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2175                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2176                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2177                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2178                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2179                                         <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2180                                         <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2181                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2182                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2183                                         <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2184                                         <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2185                                         <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2186                                         <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2187                         };
2188
2189                         lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2190                                 rockchip,pins =
2191                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2192                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2193                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2194                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2195                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2196                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2197                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2198                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2199                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2200                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2201                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2202                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2203                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2204                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2205                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2206                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2207                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2208                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2209                         };
2210
2211                         lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2212                                 rockchip,pins =
2213                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2214                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2215                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2216                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2217                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2218                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2219                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2220                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2221                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2222                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2223                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2224                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2225                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2226                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2227                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2228                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2229                         };
2230
2231                         lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2232                                 rockchip,pins =
2233                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2234                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2235                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2236                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2237                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2238                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2239                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2240                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2241                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2242                                         <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2243                                         <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2244                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2245                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2246                                         <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2247                                         <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2248                                         <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2249                                         <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2250                         };
2251
2252                         lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2253                                 rockchip,pins =
2254                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2255                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2256                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2257                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2258                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2259                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2260                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2261                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2262                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2263                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2264                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2265                         };
2266
2267                         lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2268                                 rockchip,pins =
2269                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2270                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2271                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2272                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2273                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2274                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2275                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2276                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2277                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2278                         };
2279                 };
2280
2281                 pwm0 {
2282                         pwm0_pin: pwm0-pin {
2283                                 rockchip,pins =
2284                                         <0 RK_PB7 1 &pcfg_pull_none>;
2285                         };
2286                 };
2287
2288                 pwm1 {
2289                         pwm1_pin: pwm1-pin {
2290                                 rockchip,pins =
2291                                         <0 RK_PC0 1 &pcfg_pull_none>;
2292                         };
2293                 };
2294
2295                 pwm2 {
2296                         pwm2_pin: pwm2-pin {
2297                                 rockchip,pins =
2298                                         <2 RK_PB5 1 &pcfg_pull_none>;
2299                         };
2300                 };
2301
2302                 pwm3 {
2303                         pwm3_pin: pwm3-pin {
2304                                 rockchip,pins =
2305                                         <0 RK_PC1 1 &pcfg_pull_none>;
2306                         };
2307                 };
2308
2309                 pwm4 {
2310                         pwm4_pin: pwm4-pin {
2311                                 rockchip,pins =
2312                                         <3 RK_PC2 3 &pcfg_pull_none>;
2313                         };
2314                 };
2315
2316                 pwm5 {
2317                         pwm5_pin: pwm5-pin {
2318                                 rockchip,pins =
2319                                         <3 RK_PC3 3 &pcfg_pull_none>;
2320                         };
2321                 };
2322
2323                 pwm6 {
2324                         pwm6_pin: pwm6-pin {
2325                                 rockchip,pins =
2326                                         <3 RK_PC4 3 &pcfg_pull_none>;
2327                         };
2328                 };
2329
2330                 pwm7 {
2331                         pwm7_pin: pwm7-pin {
2332                                 rockchip,pins =
2333                                         <3 RK_PC5 3 &pcfg_pull_none>;
2334                         };
2335                 };
2336
2337                 gmac {
2338                         rmii_pins: rmii-pins {
2339                                 rockchip,pins =
2340                                         <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2341                                         <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2342                                         <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2343                                         <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2344                                         <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2345                                         <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2346                                         <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2347                                         <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2348                                         <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2349                         };
2350
2351                         mac_refclk_12ma: mac-refclk-12ma {
2352                                 rockchip,pins =
2353                                         <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2354                         };
2355
2356                         mac_refclk: mac-refclk {
2357                                 rockchip,pins =
2358                                         <2 RK_PB2 2 &pcfg_pull_none>;
2359                         };
2360                 };
2361
2362                 cif-m0 {
2363                         cif_clkout_m0: cif-clkout-m0 {
2364                                 rockchip,pins =
2365                                         <2 RK_PB3 1 &pcfg_pull_none>;
2366                         };
2367
2368                         dvp_d2d9_m0: dvp-d2d9-m0 {
2369                                 rockchip,pins =
2370                                         <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2371                                         <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2372                                         <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2373                                         <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2374                                         <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2375                                         <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2376                                         <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2377                                         <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2378                                         <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2379                                         <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2380                                         <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2381                                         <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2382                         };
2383
2384                         dvp_d0d1_m0: dvp-d0d1-m0 {
2385                                 rockchip,pins =
2386                                         <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2387                                         <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2388                         };
2389
2390                         dvp_d10d11_m0:d10-d11-m0 {
2391                                 rockchip,pins =
2392                                         <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2393                                         <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2394                         };
2395                 };
2396
2397                 cif-m1 {
2398                         cif_clkout_m1: cif-clkout-m1 {
2399                                 rockchip,pins =
2400                                         <3 RK_PD0 3 &pcfg_pull_none>;
2401                         };
2402
2403                         dvp_d2d9_m1: dvp-d2d9-m1 {
2404                                 rockchip,pins =
2405                                         <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2406                                         <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2407                                         <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2408                                         <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2409                                         <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2410                                         <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2411                                         <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2412                                         <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2413                                         <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2414                                         <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2415                                         <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2416                                         <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2417                         };
2418
2419                         dvp_d0d1_m1: dvp-d0d1-m1 {
2420                                 rockchip,pins =
2421                                         <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2422                                         <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2423                         };
2424
2425                         dvp_d10d11_m1:d10-d11-m1 {
2426                                 rockchip,pins =
2427                                         <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2428                                         <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2429                         };
2430                 };
2431
2432                 isp {
2433                         isp_prelight: isp-prelight {
2434                                 rockchip,pins =
2435                                         <3 RK_PD1 4 &pcfg_pull_none>;
2436                         };
2437                 };
2438         };
2439 };