arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Device Tree Source for the RZ/G2UL SMARC SOM common parts
   4  *
   5  * Copyright (C) 2022 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
  10
  11 / {
  12         aliases {
  13                 ethernet0 = &eth0;
  14                 ethernet1 = &eth1;
  15         };
  16
  17         chosen {
  18                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  19         };
  20
  21         memory@48000000 {
  22                 device_type = "memory";
  23                 /* first 128MB is reserved for secure area. */
  24                 reg = <0x0 0x48000000 0x0 0x38000000>;
  25         };
  26
  27         reg_1p8v: regulator0 {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "fixed-1.8V";
  30                 regulator-min-microvolt = <1800000>;
  31                 regulator-max-microvolt = <1800000>;
  32                 regulator-boot-on;
  33                 regulator-always-on;
  34         };
  35
  36         reg_3p3v: regulator1 {
  37                 compatible = "regulator-fixed";
  38                 regulator-name = "fixed-3.3V";
  39                 regulator-min-microvolt = <3300000>;
  40                 regulator-max-microvolt = <3300000>;
  41                 regulator-boot-on;
  42                 regulator-always-on;
  43         };
  44
  45 #if !(SW_SW0_DEV_SEL)
  46         vccq_sdhi0: regulator-vccq-sdhi0 {
  47                 compatible = "regulator-gpio";
  48
  49                 regulator-name = "SDHI0 VccQ";
  50                 regulator-min-microvolt = <1800000>;
  51                 regulator-max-microvolt = <3300000>;
  52                 states = <3300000 1>, <1800000 0>;
  53                 regulator-boot-on;
  54                 gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>;
  55                 regulator-always-on;
  56         };
  57 #endif
  58 };
  59
  60 #if (!SW_ET0_EN_N)
  61 &eth0 {
  62         pinctrl-0 = <&eth0_pins>;
  63         pinctrl-names = "default";
  64         phy-handle = <&phy0>;
  65         phy-mode = "rgmii-id";
  66         status = "okay";
  67
  68         phy0: ethernet-phy@7 {
  69                 compatible = "ethernet-phy-id0022.1640",
  70                              "ethernet-phy-ieee802.3-c22";
  71                 reg = <7>;
  72                 rxc-skew-psec = <2400>;
  73                 txc-skew-psec = <2400>;
  74                 rxdv-skew-psec = <0>;
  75                 txdv-skew-psec = <0>;
  76                 rxd0-skew-psec = <0>;
  77                 rxd1-skew-psec = <0>;
  78                 rxd2-skew-psec = <0>;
  79                 rxd3-skew-psec = <0>;
  80                 txd0-skew-psec = <0>;
  81                 txd1-skew-psec = <0>;
  82                 txd2-skew-psec = <0>;
  83                 txd3-skew-psec = <0>;
  84         };
  85 };
  86 #endif
  87
  88 &eth1 {
  89         pinctrl-0 = <&eth1_pins>;
  90         pinctrl-names = "default";
  91         phy-handle = <&phy1>;
  92         phy-mode = "rgmii-id";
  93         status = "okay";
  94
  95         phy1: ethernet-phy@7 {
  96                 compatible = "ethernet-phy-id0022.1640",
  97                              "ethernet-phy-ieee802.3-c22";
  98                 reg = <7>;
  99                 rxc-skew-psec = <2400>;
 100                 txc-skew-psec = <2400>;
 101                 rxdv-skew-psec = <0>;
 102                 txdv-skew-psec = <0>;
 103                 rxd0-skew-psec = <0>;
 104                 rxd1-skew-psec = <0>;
 105                 rxd2-skew-psec = <0>;
 106                 rxd3-skew-psec = <0>;
 107                 txd0-skew-psec = <0>;
 108                 txd1-skew-psec = <0>;
 109                 txd2-skew-psec = <0>;
 110                 txd3-skew-psec = <0>;
 111         };
 112 };
 113
 114 &extal_clk {
 115         clock-frequency = <24000000>;
 116 };
 117
 118 &ostm1 {
 119         status = "okay";
 120 };
 121
 122 &ostm2 {
 123         status = "okay";
 124 };
 125
 126 &pinctrl {
 127         eth0_pins: eth0 {
 128                 pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
 129                          <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
 130                          <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
 131                          <RZG2L_PORT_PINMUX(1, 0, 1)>, /* ET0_TXC */
 132                          <RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
 133                          <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
 134                          <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
 135                          <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
 136                          <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
 137                          <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
 138                          <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
 139                          <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
 140                          <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
 141                          <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
 142                          <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
 143         };
 144
 145         eth1_pins: eth1 {
 146                 pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */
 147                          <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
 148                          <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
 149                          <RZG2L_PORT_PINMUX(7, 0, 1)>, /* ET1_TXC */
 150                          <RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */
 151                          <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
 152                          <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
 153                          <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
 154                          <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
 155                          <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
 156                          <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
 157                          <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
 158                          <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
 159                          <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
 160                          <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */
 161         };
 162
 163         sdhi0_emmc_pins: sd0emmc {
 164                 sd0_emmc_data {
 165                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
 166                                "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
 167                         power-source = <1800>;
 168                 };
 169
 170                 sd0_emmc_ctrl {
 171                         pins = "SD0_CLK", "SD0_CMD";
 172                         power-source = <1800>;
 173                 };
 174
 175                 sd0_emmc_rst {
 176                         pins = "SD0_RST#";
 177                         power-source = <1800>;
 178                 };
 179         };
 180
 181         sdhi0_pins: sd0 {
 182                 sd0_data {
 183                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
 184                         power-source = <3300>;
 185                 };
 186
 187                 sd0_ctrl {
 188                         pins = "SD0_CLK", "SD0_CMD";
 189                         power-source = <3300>;
 190                 };
 191
 192                 sd0_mux {
 193                         pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
 194                 };
 195         };
 196
 197         sdhi0_pins_uhs: sd0_uhs {
 198                 sd0_data_uhs {
 199                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
 200                         power-source = <1800>;
 201                 };
 202
 203                 sd0_ctrl_uhs {
 204                         pins = "SD0_CLK", "SD0_CMD";
 205                         power-source = <1800>;
 206                 };
 207
 208                 sd0_mux_uhs {
 209                         pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
 210                 };
 211         };
 212 };
 213
 214 #if (SW_SW0_DEV_SEL)
 215 &sdhi0 {
 216         pinctrl-0 = <&sdhi0_emmc_pins>;
 217         pinctrl-1 = <&sdhi0_emmc_pins>;
 218         pinctrl-names = "default", "state_uhs";
 219
 220         vmmc-supply = <&reg_3p3v>;
 221         vqmmc-supply = <&reg_1p8v>;
 222         bus-width = <8>;
 223         mmc-hs200-1_8v;
 224         non-removable;
 225         fixed-emmc-driver-type = <1>;
 226         status = "okay";
 227 };
 228 #else
 229 &sdhi0 {
 230         pinctrl-0 = <&sdhi0_pins>;
 231         pinctrl-1 = <&sdhi0_pins_uhs>;
 232         pinctrl-names = "default", "state_uhs";
 233
 234         vmmc-supply = <&reg_3p3v>;
 235         vqmmc-supply = <&vccq_sdhi0>;
 236         bus-width = <4>;
 237         sd-uhs-sdr50;
 238         sd-uhs-sdr104;
 239         status = "okay";
 240 };
 241 #endif
 242
 243 &wdt0 {
 244         status = "okay";
 245         timeout-sec = <60>;
 246 };
 247
 248 &wdt2 {
 249         status = "okay";
 250         timeout-sec = <60>;
 251 };